LV5654T

Ordering number : ENA1360 LV5654T Overview Bi-CMOS IC 4-Channel Switching Regulator Controller The LV5654T is a 4-channel switching regulator controller. Features • Low-voltage (3V) operation. • Independent standby functions for each of the four channels. • Synchronous rectification : channel 1 and channel 2. • Reference voltage precision : ±1%. • Is capable of driving MOS transistors. • Supports inverting step-up operation (channel 3). Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Maximum clock input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VBVIAS max VCLKIN max Pd max Topr Tstg VCC pin VBIAS pin CLKIN pin Independent IC Conditions Ratings -0.3 to 16 -0.3 to 18 5.5 0.4 -30 to +85 -55 to +125 Unit V V V W °C °C Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Clock input voltage Timing resistor Timing capacitor Triangle wave frequency Symbol VCC VBIAS VCLKIN RT CT fOSC VCC pin VBIAS pin CLKIN pin Conditions Ratings 3 to 15 3 to 15 5 7 to 30 100 to 1000 0.1 to 1.3 Unit V V V kΩ pF MHz Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D2408 MS PC 20081030-S00001 No.A1360-1/10 LV5654T Electrical Characteristics at Ta = 25°C, VCC = VBIAS = 3.6V, SCP = 0V Parameter Error amplifier 1 IN+ pin internal bias voltage VB Value added to the error amplifier offset at the error amplifier + side Output low voltage Output high voltage Error amplifier 2 IN3-RE pin offset voltage Output low voltage Output high voltage Protection circuit Threshold voltage SCP pin current Short circuit detection signal pin Software start block (ch1 to ch4) Soft start current Soft start resistance Fixed duty Maximum on duty 1-2 Maximum on duty 3 Maximum on duty 4 Output block 1 to 6 OUT pin high side on resistance OUT pin high side on resistance Triangle wave oscillator block Current setting pin voltage Output current Output current ratio Oscillation frequency Reference voltage block Reference voltage Line regulation Control circuit On state voltage OFF state voltage Pin input current Standby circuit On voltage Off voltage Pin input current All circuits VCC current consumption Standby mode current consumption ICC IOFF IN1- to IN4- = 1V VSTBY = VCTL = 0V IOFF = ICC + IBIAS 4 5 1 mA µA VON STBY VOFF STBY IIN STBY VSTBY = 2V 2.0 0.6 60 V V µA VON CTL VOFF CTL IIN CTL 2.0 0.6 60 V V µA VREF VLN REF VCC = 3V to 15V 1.240 10 V mV VT RT IOH CT ∆IO CT fOSC1 CT pin, rise/fall RT = 10kΩ, CT = 270pF RT = 10kΩ 0.57 190 2.5 510 kHz V µA ROUT SOUR ROUT SINK IO = 10mA IO = 10mA 25 10 Ω Ω ch1 to ch2 ch3 ch4 Duty MAX 1-2 Duty MAX 3 Duty MAX 4 Out monitor, IN- = 0V Out monitor, IN- = 0V Out monitor, IN- = 0V 100 80 80 85 85 90 90 % % % ch1 to ch4 ch1 to ch4 ISF RSF CSOFT = 0V 3.2 160 4 200 4.8 240 µA kΩ VSCP ISCP VSCPOUT Open collector ISCPOUT = 100µA 1.1 1.25 4 0.2 1.4 V µA V VOF VLow FB3RE VHi FB3RE IN3-RE = 2.0V, IFB = 20µA IN3-RE = -10mV, IFB = 500µA 2.0 -6 6 0.2 mV V V ch1 to ch4 ch1 to ch4 VLow FB VHi FB voltage IN- = 2.0V, IFB = 20µA IN- = 0V IFB1 = -20µA 2.0 0.2 V V 0.504 0.51 0.516 V Symbol Conditions min Ratings typ max Unit No.A1360-2/10 LV5654T Package Dimensions unit : mm (typ) 3253B 9.75 36 19 5.6 7.6 (0.5) (0.63) 1 0.18 18 0.15 SANYO : TSSOP36(275mil) Pin Assignment 0.08 (1.0) 1.2max VBIAS 1 OUT3 2 OUT4 3 SCPOUT 4 CLKIN 5 STBY4 6 STBY3 7 STBY2 8 STBY1 9 SCP 10 CTL 11 IN4- 12 FB4 13 IN3+RE 14 IN3-RE 15 FB3RE 16 FB3 17 IN3- 18 0.5 36 OUT2 35 OUT2N 34 GND_P (VS) 33 OUT1 32 OUT1N 31 CSOFT1 30 CSOFT2 29 CSOFT3 28 CSOFT4 27 VCC 26 IN125 FB1 24 IN223 FB2 22 VREF 21 CT 20 RT 19 GND_S Top view LV5654T No.A1360-3/10 LV5654T Block Diagram and Sample Application Circuit VREF SCP SCP_OUT Signal system power supply FB1A IN1FB1 CSOFT1 VCC Pre-output stage VBIAS power supply + + - + OUT1 Step-down FB1A (DOWN) OUT1N VO1 3.3V/100mA FB2A IN2FB2 CSOFT2 OUT2N VO2 3.3V/100mA + + - + OUT2 Step-down FB2A (DOWN) FB3A IN3-RE IN3+RE FB3R IN3FB3 CSOFT3 + + + - + FB3A OUT3 Inversion (INVERT) VO3 -4V/100mA FB4A IN4FB4 CSOFT4 GND_P (VS) GND_S STBY1 STBY2 STBY3 STBY4 FB4A Step-up (UP) + + - + - OUT4 ON/OFF setting VO4 6V/100mA STBY OSC RT CT CLKIN CTL The CLKIN pin must be connected to GND, when the external clock synchronization (CLKIN) is not used. No.A1360-4/10 LV5654T Pin Function Block ch1 DOWN (Step-down) Pin No. 9 26 25 31 33 32 ch2 DOWN (Step-down) 8 24 23 30 36 35 ch3 (Inversion) 7 14 15 16 18 17 29 2 ch4 Step-up (UP) 6 12 13 28 3 POWER 27 1 19 34 22 CONTROL 11 10 4 OSC 21 20 5 Pin Name STBY1 IN1FB1 CSOFT1 OUT1 OUT1N STBY2 IN2FB2 CSOFT2 OUT2 OUT2N STBY3 IN3+RE IN3-RE FB3RE IN3FB3 CSOFT3 OUT3 STBY4 IN4FB4 CSOFT4 OUT4 VCC VBIAS GND_S GND_P (VS) VREF CTL SCP SCPOUT CT RT CLKIN Standby input. H/ch1 ; ON, L/ch1 ; OFF. Error amplifier Inverting input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor P-channel gate connection. Output. External transistor N-channel gate connection. Standby input. H/ch2 ; ON, L/ch2 ; OFF. Error amplifier Inverting input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor P-channel gate connection. Output. External transistor N-channel gate connection. Standby input. H/ch3 ; ON, L/ch3 ; OFF. Inversion amplifier, + (noninverting) input. Inversion amplifier, - (Inverting) input. Inversion amplifier output. Error amplifier, - (Inverting) input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor P-channel gate connection. Standby input. H/ch4 ; ON, L/ch4 ; OFF. Error amplifier Inverting input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor N-channel gate connection. Power supply input (signal system). Power supply input (pre-output stage). Ground (signal system). Ground (pre-output stage). Reference voltage output. Output control. Connection pin for the delay time setting capacitor of short circuit detection circuit. SCP_OUT pin (SCP output). Triangle wave oscillation frequency setting capacitor connection. Triangle wave oscillation frequency setting resistor connection. External clock input. Functions No.A1360-5/10 LV5654T Equivalent Circuits Pin No. 11 9 8 7 6 Pin Name CTL STBY1 STBY2 STBY3 STBY4 Equivalent Circuit CTRL/STBY* 120kΩ 30kΩ GND_S 26 24 18 12 IN1IN2IN3IN4- VREG (Internal constant voltage) IN*- 500Ω 5kΩ 5kΩ GND_S 25 23 17 13 FB1 FB2 FB3 FB4 VREG (Internal constant voltage) 20Ω FB* 500Ω GND_S 14 15 IN3+RE IN3-RE VREG (Internal constant voltage) IN3-RE IN3+RE 500Ω 500Ω 5kΩ 5kΩ GND_S 16 FB3R VREG (Internal constant voltage) FB3R GND_S 31 30 29 28 CSOFT1 CSOFT2 CSOFT3 CSOFT4 VREG (Internal constant voltage) 500Ω 10kΩ 200kΩ GND_S Continued on next page. CSOFT* No.A1360-6/10 LV5654T Continued from preceding page. Pin No. 33 32 36 35 2 3 Pin Name OUT1 OUT1N OUT2 OUT2N OUT3 OUT4 Equivalent Circuit VBIAS VOUT* VOUT*N GND_P (VS) 20 RT VREG (Internal constant voltage) 500Ω RT 500Ω GND_S 21 CT VREG (Internal constant voltage) CT GND_S 10 SCP VREG (Internal constant voltage) 1.5kΩ SCP 13kΩ GND_S 4 SCP_OUT VREG (Internal constant voltage) SCP_OUT GND_S Continued on next page. No.A1360-7/10 LV5654T Continued from preceding page. Pin No. 22 Pin Name VREF Equivalent Circuit VREG (Internal constant voltage) VREF 14.8kΩ GND_S 5 CLKIN VREG (Internal constant voltage) CLKIN 300Ω GND_S 27 VCC VBIAS GND_S GND_P (VS) VCC 1 19 34 VBIAS GND_S GND_P (VS) No.A1360-8/10 LV5654T Notes (1) Soft start time setting method The soft start time is set with the capacitor connected between CSOFT* and GND_S. This IC has an independent soft start function for each channel, so a capacitor must be connected for each channel to set the soft start (time). (Description of soft start operation) CSOFT* [V] CSOFT* voltage VB (= 0.515 [V] (TYP)) VREG (Internal constant voltage) (Outline of soft start pin) T [s] Soft start time (Tsoft [s]) CSOFT pin charging starts The output voltage reaches the set voltage (Output voltage constant) 200kΩ CSOFT* GND_S VB (TYP, 0.515 [V]) (2) Setting the oscillation frequency The internal oscillation frequency is set by the resistor connected to the RT pin and the capacitor connected to the CT pin. The waveform generated on CT is a triangular wave with the charging/discharging waveform determined by RT and CT. 1 fOSC = 1.32 × CT × RT [Hz] The actual internal oscillation frequency deviates from the calculated value due to overshoot, undershoot and other factors, so the frequency should be confirmed in an actual set. (3) External input CLK function (CLK_IN) Switching operation can be synchronized with external clock input (CLK_IN) by using the CLK_IN pin. • External clock (CLK_IN) frequency and input level When using external clock (CLK_IN) input, input a frequency equal to the internal oscillation frequency +20% or more to CLK_IN. In addition, the CLK_IN configuration is shown in the figure “CLK_IN (input) equivalent circuit (outline)” below. The 0.8V reference voltage and CLK_IN are compared to determine the edges, so input a signal of 0.8V or more (VCC voltage or less) as the external clock (CLK_IN). • External/internal clock switching Set the CTL pin Low before switching between the external clock and the internal clock. Switching clocks when running may give rise to output voltage fluctuations. • Maximum ON duty The maximum ON duty (Duty_MAX*) of channel 3 to channel 4 is the 85% (typ.) setting. When using the external clock (CLK_IN), the maximum ON duty (Duty_MAX*) becomes smaller, so care must be taken for the set output voltage. (CLK_IN (input) equivalent circuit (outline)) CLK_IN 0.8V No.A1360-9/10 LV5654T (4) SCP function • Description of operation When any one of FB1 to FB4 goes High due to the load being shorted or other reason, charging to the SCP pin starts. If output does not recover during the set time Tscp and the SCP pin voltage exceeds the threshold voltage, the protection circuit (SCP) operates, and all channel outputs are turned OFF. The SCP_OUT pin set from High to Low. All outputs are latched OFF by the protection circuit (SCP). This latched state (output OFF) is canceled by setting the CTL pin Low or by turning the power supply off. When not using the protection function (SCP), the SCP pin must be shorted to GND_S with a line that is as short as possible. • SCP_OUT The SCP_OUT pin functions to notify an external microcontroller or other component of the output status (Low when SCP operates). The output configuration is an open drain output, and a pull-up resistor is used. When not used, leave this pin open. • Switching time The SCP_OUT switching time is set by the capacitor connected to the SCP pin. (SCP charging operation) (SCP and SCP_OUT operation) ⋅When STBY* is regarded as High SCP [V] Charging with Iscp = 4 [µA] 1.25 [V] (TYP) CTL SCP (the output is turned on by setting CTL Low to High). Capacitor charging starts with the load being shorted Threshold voltage 1.25V (TYP) tscp Output short circuit T [s] SCP operation SCP_OUT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. 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Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice. PS No.A1360-10/10