LV7109E

Ordering number : ENA1992 Bi-CMOS IC LV7109E Overview AC Switch Europe SCART Standard The LV7109E is a rationalized IC of AC switch LV7108 complying with the Europe SCART standard. Features and functions • Video/Audio Canal-SW • 6dB-VideoAmp • 6MHz/12MHz/27MHz-LowPassFilter • 9ch VideoDriver (AV1/AV2/Line/RGB/Component) • V-Sync. Detection • 3ch Stereo Audio Input • 2ch Stereo Audio Output Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Recommended supply voltage 1 Recommended supply voltage 2 Operating supply range 1 Operating supply range 2 Allowable power dissipation Operating temperature Storage temperature Symbol VCC1 max VCC2 max VCC1 VCC2 VCC1 opg VCC2 opg Pd max Topr Tstg * With specified substrate Conditions Ratings 6.0 13.0 5.0 12.0 4.5 to 5.3 11.1 to 12.5 1070 -20 to +75 -40 to +150 Unit V V V V V V mW °C °C * With specified substrate : 76.1mm × 114.3mm × 1.6mm, glass epoxy. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. N1611 SY PC 20110207-S00003 No.A1992-1/24 LV7109E Electrical Characteristics at Ta = 25°C, VCCV = 5.0V, VCCA = 12V Parameter Current dissipation 1 (5V) Current dissipation 2 (ALL5V) Current dissipation 3 (12V) Video Canal SW part Output voltage 1 Voltage gain Frequency characteristics 1 Frequency characteristics 2 DG Differential gain DP Differential phase Cross talk between channel Picture S/N Maximum output level 1 VDCC VGC VFC1 VFC2 DGC DPC CTC VSNC VOMAXC1 17 19 12 14 17 38 40 19 38 40 14 12 AV1, AV2-OUT (Sync tip) VIN = 1Vp-p, f = 100kHz, AV1, AV2-OUT VIN = 1Vp-p, f = 10MHz/100kHz (P17, P19: Through) VIN = 1Vp-p, f = 6MHz/100kHz (P38, P40: 6MHz-LPF) VIN = Video : 1Vp-p VIN = Video : 1Vp-p Selected input = GND Non-selected input = 1Vp-p, f = 4.43MHz VIN = Video (50%White) Output level (Trough output) whose linearity exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Maximum output level 2 VOMAXC2 38 40 12 14 Output level (ENC output) whose linearity exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Video INPUT SW part Output voltage 1 Output voltage 2 Output voltage 3 Voltage gain 1 Frequency characteristics DG Differential Gain DP Differential Phase Cross talk between channel Picture S/N Maximum output level VDCI1 VDCI2 VDCI3 VGI1 VFI DGSW DPSW CTAD VSNC VOMAXSW 17, 19, 21 17, 19, 21 3 17, 19, 21 3 17, 19, 21 3 17, 19, 21 17, 19, 21 17, 19, 21 3 17, 19, 21 17, 19, 21 35 35 33 33 35 33 35 35 35 33 35 35 35 VIN = Video :1Vp-p VIN = Video :1Vp-p Selected input = GND Non-selected input = 1Vp-p, f = 4.43MHz VIN = Video (50%White) Output level (ENC output) whose linearity exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Video Driver part Output voltage 1 VDCD1 64, 46 1, 44 3, 42 Output voltage 2 Output voltage 3 VDCD2 VDCD3 40 3 46 42 Output voltage 4 Voltage gain 1 VDCD4 VGD1 40 64, 46 1, 44 3, 42 40, 38 6 8 10 16 27 10 23 25 27 6, 23 8, 27 10, 25 12, 14, 16 Continued on next page. Y (Sync tip) For VIN = 1Vp-p and f = 100kHz Line output only: 2 drives, Other outputs: 1drive 0.8 5.5 1.0 6.0 1.2 6.5 V dB CVBS (Sync tip) Y (Sync tip) C, Pr, Pb (Center) 1.7 2.0 2.3 V 0.5 0.7 0.9 V RGB (Pedestal) 0.6 0.8 1.0 V 1.8 -66 2.0 -60 dB Vp-p -1 -1.5 0 0 -60 +1 +1.5 -50 % °C dB VIN = 1Vp-p, f = 10MHz/100kHz -1.0 0.0 +1.0 dB Composite (Sync-Tip) Y (Sync-Tip) Chroma (Center) VIN = 1Vp-p, f = 100kHz, load = 10kΩ 0.8 0.8 1.8 -0.5 1.0 1.0 2.1 0.0 1.2 1.2 2.4 +0.5 V V V dB 2.6 2.7 Vp-p 2.8 -70 3.0 -65 dB Vp-p -1 -1.5 0 0 -60 +1 +1.5 -50 % °C dB -1.5 0.0 +1.5 dB 0.5 5.5 -1.0 0.7 6.0 0.0 0.9 6.5 +1.0 V dB dB ICC3 Non-signal 7.7 9.0 10.4 mA Symbol ICC1 ICC2 Input point Output point Non-signal Non-signal Ratings Test condition min 69.7 11.1 typ 82.0 13.0 max 94.3 15.0 mA mA Unit No.A1992-2/24 LV7109E Continued from preceding page. Parameter Frequency characteristics 1 Symbol VFD1 Input point 46, 44, 42 40, 38 Frequency characteristics 2 VFD2 46 44 42 Frequency characteristics 3 VFD3 46 44 42 Frequency characteristics 4 VFD4 46 44 42 Frequency characteristics 5 Frequency characteristics 6 Frequency characteristics 7 Frequency characteristics 8 Group delay 1 VFD5 VFD6 VFD7 VFD8 VGDD1 46 42 46 42 44 44 46, 44, 42 40, 38 Group delay 2 VGDD2 46 44 42 Group delay 3 Group delay 4 Mute attenuation DG Differential gain DP Differential phase Cross talk between channel Picture S/N Maximum output level 1 VGDD3 VGDD4 VMUD DG1 DP1 CTD VSND VOMAXD1 64, 46 1, 44 3, 42 Maximum output level 2 VOMAXD2 40 46 42 44 Output point 6, 8, 10 23, 27, 25 12, 14 16 6 8 10 23 27 25 23 27 25 23 25 23 25 27 27 6, 8, 10 23, 27, 25 12, 14 16 23 27 25 23 25 27 ALL ALL ALL ALL ALL 6 8 10 16 27 f = 27MHz/100kHz when 13.5MHzLPF is selected f = 27MHz/100kHz when 27MHzLPF is selected VIN = 1Vp-p, f=4.43MHz VIN = Video : 1Vp-p VIN = Video : 1Vp-p VIN = 1Vp-p, f=4.43MHz Driver output terminated with 75Ω VIN = Video (50%White) Output level (RGB) whose linearity exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Output level (brightness, CVBS) whose linearity exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Maximum output level 3 VOMAXD3 46 42 23 25 Output level (color difference) whose linearity exceeds 1% VIN = sin 10kHz Output level at linearity 1% Sync-SEP part V.SYNC output High voltage V.SYNC output Low voltage V.SYNC output delay time V.SYNC output pulse width Note 2) When pin 10 is open Continued on next page. TWVS 17, 19, 21 34 VIN = PAL Video : 1Vp-p Note 2) 125 155 185 μs TDVS 17, 19, 21 34 Note 2) 7 15 25 μs VVSL 17, 19, 21 34 0.0 0.3 0.6 V VVSH 17, 19, 21 34 4.3 4.7 5.0 V 2.0 2.5 Vp-p 2.6 2.8 Vp-p 2.5 -1 -1.5 -60 0 0 -60 -70 2.7 -50 +1 +1.5 -50 -65 dB % °C dB dB Vp-p 10 18 ns 10 18 ns f = 12MHz/100kHz when 12MHzLPF is selected 14 25 ns f = 13.5MHz/100kHz when 13.5MHzLPF is selected f = 74MHz/100kHz when 13.5MHzLPF is selected f = 25MHz/100kHz when 27MHzLPF is selected f = 74MHz/100kHz when 27MHzLPF is selected f = 6MHz/100kHz when 6MHzLPF is selected 20 35 ns -40 -30 dB -1.5 0.0 +1.5 dB -40 -30 dB -1.5 0.0 +1.5 dB f = 54MHz/100kHz when 12MHzLPF is selected -40 -30 dB f = 12MHz/100kHz when 12MHzLPF is selected -1.5 0.0 +1.5 dB f = 27MHz/100kHz when 6MHzLPF is selected -35 -25 dB Ratings Test condition min VIN = 1Vp-p, f = 6MHz/100kHz when 6MHzLPF is selected -1.5 typ 0.0 max +1.5 dB Unit No.A1992-3/24 LV7109E Continued from preceding page. Parameter Audio canal switches part Maximum output level VOMAXC AV1, AV2-OUT (L, R) Output level at f = 1kHz, THD = 1% BW = 400 to 30kHz Channel balance Total harmonic distortion Output noise voltage Mute attenuation CVSW THDAC VNAC VMUAC L-Ch. 54, 55, 56 Input impedance Cross talk between channel and selctors Output off set voltage External control part I2C-BUS High level input voltage I2C-BUS Low level input voltage FSS output H voltage VHFSS VIL VIH 36 37 36 37 7 Serial control select FSS OUT H, load = 10kΩ external output resistor 470 recommended FSS output M voltage VMFSS 7 Serial control select FSS OUT M, load = 10kΩ external output resistor 470 recommended FSS output L voltage FSS risinge time FB output H voltage FB output L voltage FB external control L range FB external control H range External control output H voltage External control output L voltage Internal reference regulator REG2.5V REG9.0V VRE4.5 VREG25 VREG90 VREG45 2 31 52 57 48 4.3 4.5 4.7 V 8.7 9.0 9.3 V 2.3 2.5 2.7 V VEXTL 26 2kΩ load for data 0 0.0 0.3 1.0 V VLFSS TFSSLH VHFB VLFB VLFBIN VHFBIN VEXTH 20 20 7 7 18 18 18 18 26 Serial control select FB OUT H, load = 150Ω Serial control select FB OUT L, load = 150Ω Pin 20 input voltage range at which the pin 18 output becomes “L”. Pin 20 input voltage range at which the pin 18 output becomes “H”. 2kΩ load for data 1 4.0 4.5 5.0 V 1.0 3.0 V 0.0 0.5 V 0.0 0.2 0.4 V 3.0 4.0 Serial control select FSS OUT, load = 10kΩ 1.0 5.0 ms V 0.0 0.1 0.5 V 5.5 6.3 7.0 V 10.6 11.1 11.6 V GND 0.8 V 2.5 VCC5 V VOFSET ZIN CTSW VIN = 2Vrms, f = 1kHz Rg = 0Ω, BW = JIS-A Off set voltage at the time of changeover SW. -20 0 +20 mV L-Ch. 59, 62 VIN = 2Vrms, f = 1kHz Lch Gain-Rch Gain R-Ch. 49, 50, 51 R-Ch. 58, 61 VIN = 2Vrms, f = 1kHz, BW = 400 to 30kHz Rg = 0Ω, BW = JIS-A VIN = 2Vrms, f = 1kHz, BW = JIS-A 20log (VOUT/VIN) 80 -1.5 0.0 0.003 -100 -90 +1.5 0.01 -80 -75 dB % dBV dB kΩ dB 2.2 2.5 Vrms Symbol Input point Output point Ratings Test condition min typ max Unit 100 -110 120 -80 No.A1992-4/24 LV7109E Package Dimensions unit : mm (typ) 3159A 17.2 14.0 48 49 33 32 14.0 64 1 0.8 (1.0) (2.7) 17 16 0.35 0.15 3.0max 0.1 SANYO : QIP64E(14X14) AudioPower Supply Block Diagram VCC12V_A 29 REG9V_AR 52 A-DAC_R_IN 49 100kΩ 9V-Reg. Buf. R-ch Input Bias R-ch Circuit Power Supply REF4.5V 48 4.5V-Ref. Buf. R-ch Output Ref. AV1_R_OUT 61 100kΩ 100kΩ AV2_R_OUT 58 AV2_R_IN 50 AV1_R_IN 51 17.2 0.8 Buffer Switch Buf. Mute Switch Buf. Mute VCC5V_ALL 28 Power Mute Switch Buf. Mute AV2_L_OUT 59 Buf. REG9V_AL 57 L-ch Output Ref. 9V-Reg. L-ch Circuit Power Supply 100kΩ Buf. L-ch Input Bias 100kΩ 100kΩ AV1_L_OUT 62 Buffer Switch Buf. Mute 54 A-DAC_L_IN 55 AV2_L_IN 56 AV1_L_IN No.A1992-5/24 LV7109E Video Power Supply Block Diagram The thick line indicates the circuit operative in the power save mode. Applied power to VCC5_All, VCC5V_SW and VCC_LOGIC only in the power save mode. VCC5V_VD 24 Input Bias/Clamp GND_VD 22 VCC5V_VC 4 Input Bias/Clamp Low Pass Filter Low Pass Filter Switch 6dB. DR. GND_RGB 11 VCC5V_VL 13 VCC5V_RGB 9 RGB/ Component Switch 6dB. DR. Line Output Input Bias/Clamp GND_VC 5 Low Pass Filter Switch 6dB. Canal AV1/AV2 DR. GND_VL 15 VCC5V_ALL 28 Input Bias/Clamp Switch ADC Output 0dB VCC5V_SW 43 V-Sync. Detector V-Sync.Output 34 GND_SW 41 VCC12V_A 29 FB Control FSS Control Canal FB FB Output Canal FSS FSS Output 7 18 VCC5V_LOGIC 30 36 Serial 37 EXT-CTL 26 GND_LOGIC 39 Serial Control No.A1992-6/24 Audio_Mute_Filter 0.1μF 180kΩ X LV7109 PIN (for Power Save) X LV7109 PIN (always Power ON) X SCART PIN C_ADC REF4.5V 0.1μF 0.1μF 0.1μF ENC_R_IN ENC_C_IN ENC_G_IN ENC_B_IN ENC_Y_IN Y/V_ADC SDA_IN SCL_IN GND_LOGIC GND_V_SW V-Sync._OUT VCC5V_SW GND_REF 22μF + 42 Clamp/ Bias Clamp Bias 0.1μF 0.1μF 48 0dB 0dB Serial Control V-Sync. Sep. REG2.5V_ALL REG LPF V-Sync. Sep. Sync._Sep._Filter 33pF 47 46 45 44 43 41 40 39 38 37 36 35 34 33 Block Diagram A-DAC_R_IN 6M 0.01μF 6M REF Clamp/ Bias Clamp 1μF 49 Bias 32 AV2_R_IN Marks of switches are assigned alphabetically from LSB. ex.) assign 3bit register a=000, b=001, c=010, d=011, e=100, f=101 Pin List Bold parts are for Always Power ON 6M 6M 6M 12M/27M 12M/13.5M 12M/13.5M 2 SV7 1μF 50 Bias + 31 AV1_R_IN 2 VCC5V_LOGIC 1μF 51 b a cd Bias 30 Mute REG9V_AR a b,c d,e Mute + 52 29 VCC12V_A REG SA1R 10μF GND_REG VCC5V_ALL 1000μF 6dB SV12a a 53 ENC_Y ENC_PY ENC_PR ENC_PB a b,c b,d,e Mute 28 75Ω A-DAC_L_IN SV4 f Mute b c d e SA2R 1μF 54 + PY_OUT(Component) EXT_CTL1 330μF 6dB ae Bias 27 a b c d AV2_L_IN Mute 6 Serial SV11a bcdf Mute 75Ω SV3 1μF 55 + a c d b Bias AV1_L_IN a b,c d,e Mute EXTCTL1 26 SA1L 6 + VCC5V_VD 330μF 6dB 75Ω PR_OUT(Component) 1μF 56 Mute Mute SV13a bcdf Mute ae AV3_V AV2_V/Y AV1_V Bias 25 REG9V_AL c c LV7109E + 57 SV5 SV6 REG abde abde AV1_V AV3_V 10μF a b,c b,d,e Mute 24 SA2L AV2_V/Y AV2_R_OUT Mute LPF 1 23 + + 58 Buf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AV2_G_IN REG2.5V AV2_R/C_IN GND_VC VCC5V_VC AV1_B_OUT AV1_FSS_OUT AV1_G_OUT VCC5V_RGB AV1_R/C_OUT GND_RGB AV2_V_OUT VCC5V_VL AV1_V/Y_OUT GND_VL V_OUT (Line) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C_ADC V-Sync._OUT Y/V_ADC SDA_IN SCL_IN ENC_C_IN GND_LOGIC ENC_Y_IN GND_V_SW ENC_R_IN VCC5V_SW ENC_G_IN GND_REF ENC_B_IN Audio_Mute_Filter REF4.5V Mute Mute 1kΩ 10μF AV2_L_OUT SA2R PB_OUT(Component) GND_VD ENC_C ENC_Y+C ENC_Y Mute LPF 3 1kΩ Clamp 10μF + 59 Buf SA2L 22 GND_AR 60 ENC_R ENC_G ENC_B 21 0.1μF AV3_V_IN AV1_R_OUT Mute LPF 1 + 61 Buf 1kΩ 10μF AV1_L_OUT SA1R AV2_B AV2_G AV2_R/C 20 75Ω 16 AV2_FB_IN Clamp Mute Mute Mute LPF 3 Mute Mute Mute 1kΩ 10μF + 62 Buf SA1L 19 cd a: 0V b: 4V b 0.1μF 20 AV2_V/Y_IN Drv a c bed a b c def f c Mute b d e a f bcde a f bcde a GND_AL SV12b Serial SV11b SV2 SV1 a 63 18 SV14 Clamp 75Ω 16 AV1_FB_OUT AV2_B_IN SV13b 7 6dB 6dB 6dB FSS OUT 0.1μF 64 Clamp 17 6dB 6dB 0.1μF 20 AV1_V_IN 6dB Clamp REG SV16 Clamp/ Bias 1 75Ω 680Ω 75Ω 75Ω 2 3 4 5 6 7 8 9 10 11 VCC5V_VL 12 75Ω 13 VCC5V_VL 14 75Ω 15 GND_VL 16 + 1000μF 75Ω 75Ω GND_VC VCC5V_VC VCC5V_RGB 0.1μF 0.1μF 0.1μF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 V_OUT(Line) AV1_V\Y_OUT AV2_V_OUT AV1_V_IN AV1_FB_OUT AV2_V/Y_IN AV2_FB_IN AV3_V_IN GND_VD PB_OUT (Component) VCC5V_VD PR_OUT (Component) EXT_CTL1 PY_OUT (Component) VCC5V_ALL VCC12V_A VCC5V_LOGIC REG2.5V_ALL Sync_Sep._Filter 15 19 19 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A-DAC_R_IN AV2_R_IN AV1_R_IN REG9V_AR GND_REG A-DAC_L_IN AV2_L_IN AV1_L_IN REG9V_AL AV2_R_OUT AV2_L_OUT GND_AR AV1_R_OUT AV1_L_OUT GND_AL AV2_B_IN AV1_R/C_OUT AV1_B_OUT AV2_R/C_IN AV1_FSS_OUT AV1_G_OUT AV2_G_IN REG2.5V No.A1992-7/24 8 11 11 15 7 10kΩ 3mA 10kΩ 10kΩ 10kΩ SERIAL CLOCK 75Ω 75Ω 180kΩ 75Ω 0.1μF T93 T91 T83 T82 T81 0.1μF 0.1μF T97 T95 0.1μF 0.1μF 75Ω 75Ω 22μF T16 T99 0.1μF SERIAL DATA + T49 Test Circuit 48 C_ADC REF4.5V T10 47 SCL_IN SDA_IN Y/V_ADC 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1kΩ T56 T56A 0.22μF GND_REF ENC_Y_IN ENC_C_IN GND_VSW V-Sync_OUT GND_LOGIC ENC_G/Y_IN VCC5V_VSW ENC_B/B-Y_IN ENC_R/R-Y_IN 100kΩ T2 0.01μF T53A T53 0.22μF 49 A-DAC_R_IN 32 SYNC_SEP_LPF Audio_Mute_Filte 1kΩ 100kΩ T52A T52 0.22μF 50 AV2_R_IN REG2.5V_ALL 31 1kΩ 100kΩ T57 51 AV1_R_IN VCC_LOGIC 30 47μF + 0.01μF 12V + 10μF + 52 REG9V_AR VCC12V_A 29 53 GND_REG VCC_ALL5V 28 5V T14 + 47μF 1kΩ T64A T64 0.22μF 100kΩ T61A T61 0.22μF 54 A-DAC_L_IN Y_OUT(component) 27 T13 1000μF 150Ω + + 0.01μF 2kΩ 1kΩ 100kΩ T60A T60 0.22μF 55 AV2_L_IN EXT_CTL1 26 T7 1kΩ 100kΩ T65 56 AV1_L_IN R-Y_OUT(component) 25 330μF 150Ω + LV7109E 10μF + LV7109E 57 REG9V_AL VCC5V_VD 24 T11 10kΩ T74A T74 4.7μF + 58 AV2_R_OUT B-Y_OUT(component) 23 330μF 150Ω + 10kΩ T73A T73 4.7μF + 59 AV2_L_OUT GND_VD 22 T37 0.1μF 60 GND_AR AV3_V_IN 21 T32 75Ω 10kΩ T72A T72 4.7μF + 61 AV1_R_OUT AV2_FB_IN 20 T31 0.1μF 75Ω 10kΩ T71A T71 4.7μF + 62 AV1_L_OUT AV2_V/Y_IN 19 T34 75Ω 63 GND_AL T5 AV1_FB_OUT 18 T33 150Ω AV1_R/C_OUT VCC5V_RGB AV1_G_OUT AV1_FSS_OUT AV1_B_OUT AV2_V_OUT AV1_V_OUT AV2_R/C_IN VCC5V_VL VCC5V_VC GND_RGB V_OUT(Line) 75Ω 0.1μF AV2_B_IN 64 GND_VC REG 2.5V AV2_G_IN AV1_V_IN 17 GND_VL 0.1μF 75Ω 1 T3 T100 0.01μF 75Ω 0.1μF 0.1μF T1 2 3 4 5 T12 6 T27 7 T17 8 9 T9 10 11 12 T28 13 14 T26 15 16 T23 1000μF + 75Ω 150Ω 10Ω 150Ω 150Ω 150Ω 150Ω 150Ω No.A1992-8/24 LV7109E LV7109E Serial Control Table ADDRESS 8 7 6 5 4 3 2 1 Symbol 000 001 010 SV1 011 100 101 Group 1 0000 0001 VIDEO CANAL-SW VIDEO 11X 000 001 010 SV2 011 100 1 0 1 and after 00 01 SV3 10 11 c d N/A N/A d e a b P17 P19 MUTE MUTE PROHIBIT AV1_V_IN AV2_V/Y_IN SV4 * a b C d e f a b c P19 P40 P17 AV2_V/Y_IN ENC_Y+C_MIX ENC_Y MUTE MUTE MUTE PROHIBIT AV1_V_IN MUTE ENC_Y+C_MIX P12: AV2_V_OUT * P10: AV1_R/C_OUT Input Output * indicates initial. Remarks * ADDRESS 8 7 6 5 4 3 2 1 Symbol 00 01 SV4 10 11 000 001 C d a b c d e a b c d P19 SV5 SV4 SV5/6 MIX MUTE MUTE AV2_V/Y_IN MUTE MUTE PROHIBIT Y Composit Video a b P21 AV3_V_IN N/A Input Output Remarks SV7 According to SV3 control * MUTE MUTE AV2_R/C_IN MUTE MUTE PROHIBIT Y+C MIX SV7 P33: C_ADC * Group 2 0000 0010 VIDEO INPUT-SW 010 SV2 011 100 and 1 0 1 after 00 01 SV3 10 11 SV16 Note 1) 0 1 P35: Y/V_ADC MUTE MUTE THROUGH CLAMP input * * ADDRESS 12/27MHz LPF SW 8 7 6 5 4 3 2 1 Symbol 0 1 0 RGB output 1 000 001 SV11a SV12a SV13a 010 011 100 101 a b c d e f a b c d e f a b a b P42 P42 P42 P42 P42 P38 P3 MUTE ENC_R_IN ENC_R_IN ENC_R_IN MUTE ENC_R_IN PROHIBIT ENC_R_IN MUTE ENC_C_IN MUTE MUTE AV2_R/C_IN PROHIBIT ENC_Y+C - Input Output Remarks x = 12MHz x = 27MHz * According to G3D3-5 control Switch of SV11b-13b set to “f” P40 P44 P44 P44 P44 P44 P1 ENC_Y_IN ENC_G_IN ENC_G_IN ENC_G_IN MUTE ENC_G_IN PROHIBIT ENC_G_IN MUTE MUTE MUTE MUTE AV2_G_IN PROHIBIT P46 P46 P46 P46 P46 P64 MUTE ENC_B_IN ENC_B_IN ENC_B_IN MUTE ENC_B_IN PROHIBIT ENC_B_IN MUTE MUTE MUTE MUTE AV2_B_IN PROHIBIT P16: V_OUT (Line) P10: AV1_R/C_OUT P8: AV1_G_OUT P6: AV1_B_OUT a: ENC_RGB (6MLPF) b: mute c: ENC_C d: mute e: mute f: AV2_RGB (EXTERNAL) * P25: PR_OUT P27: PY_OUT P23: PB_OUT f: AV2_RGB (EXTERNAL) a: ENC_Y b: Component (× MLPF) c: Component (× MLPF) d: Component (× MLPF) e: mute f: Component (× MLPF) * * Group 3 0000 0011 VIDEO OTHER-1 11X 000 001 SV11b SV12b SV13b * effective at G3D2 = “0” 010 011 100 101 11X 0 SV14 1 0 N/A 1 SV16 Note 1) 0 1 MUTE THROUGH BIAS input - * * * Note 1) G2D8/G3D8 = “11” is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH. AV2_16pin SV16 H a : Clamp input (RGB) L b : Bias input (Y+C) No.A1992-9/24 LV7109E * indicates initial. ADDRESS N/A 1 0 N/A 1 00 Group 4 0000 0100 VIDEO & AUDIO OTHER-1 FB AV1 (16) Note 2) 01 10 11 00 FSS AV1 (8) 01 10 11 0 N/A 1 0 A-MUTE 1 MUTE P58,59,61,62 output MUTE * THROUGH b a b c d P20 P20 N/A 0V 5V P18: AV1_FB_OUT THROUGH THROUGH LOW (0.5V) MID (6.0V) P7: AV1_FSS_OUT HIGH (11.0V) HIGH (11.0V) * * * N/A b a N/A N/A N/A N/A * 8 7 6 5 4 3 2 1 Symbol 0 a N/A Input N/A Output Remarks * Note 2) Same polarity as the AV2 (16) FB_IN (Pin20) control in case of THROUGH. ADDRESS 8 7 6 5 4 3 2 1 Symbol 000 001 010 SA1L/R 011 100 and after 1 0 1 Group 5 0000 0101 AUDIO CANAL-SW 000 001 010 SA2L/R 011 100 1 0 1 and after 00 01 N/A 10 11 c d N/A N/A N/A N/A * d e a b MUTE MUTE PROHIBIT N/A N/A MUTE MUTE PROHIBIT N/A N/A d e f a b c P56 P54 MUTE MUTE PROHIBIT AV1_L_IN MUTE A-DAC_L_IN P51 P49 MUTE MUTE PROHIBIT AV1_R_IN MUTE A-DAC_R_IN P59: AV2_L_OUT P58: AV2_R_OUT * a b c P55 P54 P54 AV2_L_IN A-DAC_L_IN A-DAC_L_IN P50 P49 P49 Input AV2_R_IN A-DAC_R_IN A-DAC_R_IN P62: AV1_L_OUT P61: AV1_R_OUT Output Remarks * ADDRESS 8 7 6 5 4 3 2 1 Symbol 000 001 010 N/A 011 100 and after 0 101 d e a b a b c a b c N/A N/A PROHIBIT N/A N/A N/A N/A N/A PROHIBIT N/A N/A N/A PROHIBIT a b c N/A N/A N/A - Input N/A N/A N/A N/A N/A PROHIBIT Output Remarks * Group 6 0000 0110 N/A N/A 1 00 01 N/A 10 11 00 01 N/A 10 11 * * * ADDRESS 8 7 6 5 4 3 2 1 Symbol 000000 001100 N/A 111111 Other than above P42 N/A PROHIBIT L N/A N/A Input Output Remarks * Group 7 0000 0111 0 EXT-CTL1 1 -Changeover of VIDEO input 0 BIAS/CLAMP 1 General purpose OUT1 P26: EXT_CTL1 * H ENC_R_IN BIAS input CLAMP input P44 ENC_G_IN CLAMP input CLAMP input P46 ENC_B_IN BIAS input CLAMP input Input changeover Component RGB * No.A1992-10/24 LV7109E * indicates initial. ADDRESS 8 7 6 5 4 3 2 1 Symbol 000000 001100 N/A 111111 Group 8 0000 1000 0 N/A N/A 1 0 N/A 1 N/A N/A N/A * Other than above N/A PROHIBIT N/A * * N/A N/A Input Output Remarks Cautions for Use 1. Drive capacity of video driver Line outputs can drive two systems through capacitive coupling. Component outputs can drive one systems through capacitive coupling. Scart output can drive one system only through DC coupling. 2. Audio Mute This IC incorporates a mute transistor to reduce the POP noise of audio output when power is turned ON/OFF. Mute control can be made by serial control. 3. Resistor to limit the Audio input When the large signal is input in the input pin with power OFF, cross-talke between input and output occurs through the protective diode and parasitic elements. Because of the structure of LSI, such cross-talke is difficult to avoid. If cross-talk at a time of power OFF presents a problem, the cross-talk amount can be reduced by inserting the limiting resistor in the input. In this case, the input signal level changes depending on the resistance value. Determine the constant while taking both the cross-talk amount and input level into account. 4. Pin treatment when external control is not to be used When external control pins (Pins 26) are not used, pull-down to GND is recommended. 5. Audio 9V_REG pin external capacitance Use the Audio 9V_REG pins (pins 52 and 57) external capacitance of 10μF or more and with the equivalent series resistance component of 7Ω or less. 6. Power application and disconnection sequences The recommended power application sequence to this IC is VCC_ALL5V (Pin28) → VCC5V (Pins 5, 9, 13, 24, 30 and 43), VCC12V (Pin29). (No particular order is established between VCC5V and VCC12V.) It is recommended to reverse the above sequence when power supply is turned OFF. No.A1992-11/24 LV7109E Serial Control Specification 1. Slave address MSB 1 0 0 1 0 1 0 LSB 0 Slave receiver One-way communication (this IC is dedicated to receive) 2. DATA TRANSFER MANUAL : [1] is High level. [0] is Low level. I2C-BUS control system is adopted in SW LSI. SW LSI is controlled by SCL (Serial Clock) and SDA (Serial Data) At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data, which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data transfer order (MSB→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the SDA terminal during SCL [1] period. So, please open the port of microprocessor during this period. LV7107M adopt auto-increment, so you input only first group-address and you can transfer data in order. As thus the Data transfer Stop condition*2 is finished. *1 SDA rise up during SCI is [1] *2 SDA fall down during SCL is [1] 3. TRANSFER DATA FORMAT The transfer data is composed by START condition, Slave address, Group address*4, data, and STOP condition. After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW LSI). Group and next control data (Please see the Fig.1) Slave Address is composed by 7bits, and this bit 8th bit*5 should be set as [0]. The both of Group address and control data are composed by 8bits, and the one control action is defined with combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LV7107M adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data. If you want to stop transfer action, please transfer the STOP condition without fail. *4 There are 8 control groups. *5 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally. But SW LSI is not equipped with such a data out function, please keep this bit as [0]. Fig. 1 DATA STRUCTURE START condition Start condition Slave address R/W ACK Group address Acknowledge ACK Control data ACK ..... STOP condition Stop condition No.A1992-12/24 LV7109E 4. INITIALIZE AND OTHERS SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”. Characteristics of the SDA and SCL 1/0 stages for SW LSI Parameter LOW level input voltage HIGH level input voltage LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time: Data set-up time Set-up time for STOP condition BUS fredd time between a STOP and START condition Symbol VIL VIH IOL fSCL tSU : STA tHD : STA tLOW tR tHIGH tF tHD : DAT tSU : DAT tSU : STO tBUF 0.6 0.6 1.3 0 0.6 0 0 100 0.6 1.3 0.3 0.9 0.3 Min 0 3.0 Max 0.8 5.0 3.0 400 Unit V V mA kHz μs μs μs μs μs μs μs ns μs μs Fig.2 Definition of timing. tHIGH SCL 37pin tSU:STA SDA 36pin tHD:STA tLOW tHD:DAT tSU:DAT tSU:STO tBUF tR tF No.A1992-13/24 LV7109E Pin Function Pin No. P1 Pin name AV2_G_IN DC voltage 1.6Vdc +Green Signal wave form Input/Output form Note 1kΩ 4kΩ 0.7Vp-p 300Ω 1.6Vdc 300Ω 4kΩ 1 P2 REG2.5V 2.5Vdc DC 10pF 50Ω 50Ω 300Ω 6.8kΩ 2 22.8kΩ 13kΩ 18.5kΩ 18.5kΩ 30kΩ 910Ω 23kΩ P3 AV2_R/C_IN 1.6Vdc +Red 0.7Vp-p 1.6Vdc 1kΩ 4kΩ 4kΩ 2.1Vdc +Chroma 20kΩ 0.7Vp-p 2.1Vdc 300Ω 300Ω 3 P4 P5 P6 GND_VC VCC5V_VC AV1_B_OUT 0.5V +Blue 100Ω 1.4Vp-p 2kΩ 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 3.3pF 0.5Vdc 6 Continued on next page. No.A1992-14/24 LV7109E Continued from preceding page. Pin No. P7 Pin name AV1_FSS_OUT DC voltage Low : 0.5V Mid : 6.0V High : 11.1V Signal wave form DC Input/Output form Note 7 100kΩ P8 AV1_G_OUT 0.5Vdc +Green 100Ω 1.4Vp-p 2kΩ 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 3.3pF 0.5Vdc 8 P9 P10 VCC_RGB AV1_R/C_OUT 0.5Vdc +Red 1.4Vp-p 100Ω 0.5Vdc 1.7Vdc +Chroma 2kΩ 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 3.3pF 1.4Vp-p 1.7Vdc 10 P11 P12 GND_RGB AV2_V_OUT 0.5Vdc +Video 100Ω 2.0Vp-p 2kΩ 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 3.3pF 0.5Vdc 12 P13 VCC5V_VL Continued on next page. No.A1992-15/24 LV7109E Continued from preceding page. Pin No. P14 Pin name AV1_V/Y_OUT DC voltage 0.5Vdc +Video Signal wave form Input/Output form Note 2.0Vp-p 100Ω 0.5Vdc 0.5Vdc +Y 2kΩ 10.7kΩ 1.25pF 200Ω 10kΩ 3.3pF 14 2.0Vp-p 1.25pF 0.5Vdc P15 P16 GND_VL V_OUT (Line_OUT) 0.7Vdc +CVBS 100Ω 2.0Vp-p 2kΩ 10.4kΩ 3pF 100Ω 10kΩ 3pF 100kΩ 3pF 0.7Vdc 16 P17 AV1_V_IN 1.6Vdc +CVBS 1kΩ 4kΩ 1.0Vp-p 300Ω 300Ω 4kΩ 1.6Vdc 17 P18 AV1_FB_OUT Low : 0V High : 4.0V Through : 0/4.0V 10Ω 4.0Vp-p 1kΩ 1kΩ 100kΩ 18 0Vdc 1kΩ 1kΩ Continued on next page. No.A1992-16/24 LV7109E Continued from preceding page. Pin No. P19 Pin name AV2_V/Y_IN DC voltage 1.6Vdc +CVBS Signal wave form Input/Output form Note 1.0Vp-p 1kΩ 4kΩ 1.6Vdc 1.6Vdc +Y 300Ω 1.0Vp-p 300Ω 4kΩ 1.6Vdc P20 AV1_FB_IN Low : 0V High : 2V 19 2Vdc 20 0Vdc 1kΩ P21 AV3_V_IN 1.6Vdc +CVBS 1kΩ 4kΩ 1.0Vp-p 300Ω 300Ω 4kΩ 1.6Vdc 21 P22 P23 GND_VD PB_OUT (Component) 1.7V +Pb 2kΩ 1.4Vp-p 1.7Vdc 100Ω 3.3pF 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 100kΩ 23 P24 VCC5V_VD Continued on next page. No.A1992-17/24 LV7109E Continued from preceding page. Pin No. P25 Pin name PR_OUT (Component) DC voltage 1.7V +Pr Signal wave form Input/Output form Note 2kΩ 1.4Vp-p 1.7Vdc 100Ω 3.3pF 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF 100kΩ 25 P26 EXT-CTL1 (OUT) Low : 0V High : 5V 26 P27 PY_OUT (Component) 0.7Vdc +Py 5kΩ 2.0Vp-p 27 0.7Vdc P28 P29 P30 P31 VCC5V_ALL VCC12V_A VCC5V_LOGIC REG2.5V_ALL 2.5Vdc DC 10pF 50Ω 50Ω 300Ω 6.8kΩ 13kΩ 30kΩ 18.5kΩ 18.5kΩ 22.8kΩ 31 910Ω 23kΩ P32 SYNC_SEP _FILTER 2.2Vdc +Y 32 1.0Vp-p 500Ω 40kΩ 2.2Vdc 500Ω 8pF Continued on next page. No.A1992-18/24 LV7109E Continued from preceding page. Pin No. P33 Pin name ADC_C_OUT DC voltage 2.1Vdc +Chroma Signal wave form Input/Output form Note 500Ω 0.7Vp-p 33 2.1Vdc P34 V_SYNC_OUT Low : 0.3V High : 4.7V 4.7Vdc 300Ω 34 0.3Vdc 300Ω P35 ADC_V/Y_OUT 1.0Vdc +CVBS 1.0Vp-p 500Ω 1.0Vdc 1.0Vdc +Y 35 1.0Vp-p 1.0Vdc P36 SDA_IN I C DATA 2 ACK_OUT 30kΩ 500Ω 36 P37 SCL_IN I2C CLOCK 30kΩ 500Ω 37 Continued on next page. No.A1992-19/24 LV7109E Continued from preceding page. Pin No. P38 Pin name ENC_C_IN DC voltage 2.1Vdc +Chroma Signal wave form Input/Output form Note 4kΩ 0.7Vp-p 4kΩ 2.1dc 20.3kΩ 300Ω 38 P39 P40 GNG_LOGIC ENC_Y_IN 1.6Vdc +Y 1kΩ 4kΩ 1.0Vp-p 300Ω 300Ω 4kΩ 1.6Vdc 40 P41 P42 GND_VSW ENC_R/PR_IN 1.6Vdc +Red 0.7Vp-p 1.6Vdc 2.1Vdc +Pr 1kΩ 4kΩ 20kΩ 0.7Vp-p 2.1Vdc 300Ω 300Ω 4kΩ 42 P43 P44 VCC5V_SW ENC_G/PY_IN 1.6Vdc +Green 0.7Vp-p 1.6Vdc 1.6Vdc +Py 1kΩ 4kΩ 300Ω 300Ω 4kΩ 1.0Vp-p 1.6Vdc P45 GNG_REF 44 Continued on next page. No.A1992-20/24 LV7109E Continued from preceding page. Pin No. P46 Pin name ENC_B/PB_IN DC voltage 1.6Vdc +Blue Signal wave form Input/Output form Note 0.7Vp-p 1.6Vdc 2.1Vdc +Pb 1kΩ 4kΩ 20kΩ 0.7Vp-p 2.1Vdc 300Ω 300Ω 4kΩ 46 P47 Audio_Mute_Filter 140kΩ 47 500Ω 60kΩ P48 REF4.5V 4.5Vdc DC 52 60kΩ 1kΩ 60kΩ 48 P49 A-DAC_R_IN 4.5Vdc +Right 4.5V 5.6Vp-p-MAX 100kΩ 49 1kΩ 4.5Vdc P50 AV2_R_IN 4.5Vdc +Right 4.5V 5.6Vp-p-MAX 100kΩ 50 1kΩ 4.5Vdc Continued on next page. No.A1992-21/24 LV7109E Continued from preceding page. Pin No. P51 Pin name AV1_R_IN DC voltage 4.5Vdc +Right Signal wave form Input/Output form Note 4.5V 5.6Vp-p-MAX 100kΩ 51 1kΩ 4.5Vdc P52 REG9V_AR 9Vdc DC 50Ω 100Ω 141kΩ 23kΩ 52 P53 P54 GND_REG A-DAC_L_IN 4.5Vdc +Left 4.5V 5.6Vp-p-MAX 100kΩ 54 1kΩ 4.5Vdc P55 AV2_L_IN 4.5Vdc +Left 4.5V 5.6Vp-p-MAX 100kΩ 55 1kΩ 4.5Vdc P56 AV1_L_IN 4.5Vdc +Left 4.5V 5.6Vp-p-MAX 100kΩ 56 1kΩ 4.5Vdc Continued on next page. No.A1992-22/24 LV7109E Continued from preceding page. Pin No. P57 Pin name REG9V_AL DC voltage 9Vdc Signal wave form DC Input/Output form Note 50Ω 100Ω 141kΩ 23kΩ 57 P58 AV2_R_OUT 4.5Vdc +Right 4.5V 5.6Vp-p-MAX 20kΩ 700Ω 100Ω 4.5Vdc 58 P59 AV2_L_OUT 4.5Vdc +Left 4.5V 5.6Vp-p-MAX 20kΩ 700Ω 100Ω 4.5Vdc 59 P60 P61 GND_AR AV1_R_OUT 4.5Vdc +Right 4.5V 5.6Vp-p-MAX 20kΩ 700Ω 100Ω 4.5Vdc 61 P62 AV1_L_OUT 4.5Vdc +Left 4.5V 5.6Vp-p-MAX 20kΩ 700Ω 100Ω 4.5Vdc 62 P63 GND_AL Continued on next page. No.A1992-23/24 LV7109E Continued from preceding page. Pin No. P64 Pin name AV2_B_IN DC voltage 1.6Vdc +Blue Signal wave form Input/Output form Note 1kΩ 4kΩ 0.7Vp-p 300Ω 1.6Vdc 300Ω 4kΩ 64 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2011. Specifications and information herein are subject to change without notice. PS No.A1992-24/24