LV766116C

Ordering number : ENA1877 LV766116C Overview Monolithic Linear IC For PAL/NTSC Color Television Sets VIF/SIF/Y/C/Deflection /CbCr IN Implemented in a Single Chip The LV766116C is VIF/SIF/Y/C/D/Deflection /CbCr IN Implemented in a single chip for PAL/NTSC color television sets.(*1) Functions • VIF / SIF / Y / C / Deflection / CbCr IN / Implemented in a Single Chip with CPU • I2C Bus Control Specifications BIP Chip Maximum Ratings at Ta=25°C Parameter Allowable power dissipation Operating temperature Storage temperature Maximum supply voltage Symbol Pd max Topr Tstg V62 max V4 max I9 max Maximum supply current I20 max I49 max Conditions Ta ≤65°C (*2) Ratings 1.3 -10 to +65 -55 to +150 6.0 6.0 15 20 40 Unit W °C °C V V mA mA mA (*1) μ-Controller Chip：LC873664A , C：MASKROM=64Kbyte(Program_ROM:48Kbyte／character_ROM:16Kbyte) (This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc.) (*2) Provided with a glass epoxy board (230×150×1.6 mm) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D0810 SY 20101102-S00001 No.A1877-1/42 LV766116C BIP Operating Conditions at Ta=25°C Parameter Recommended supply voltage Symbol V62 V4 I9 Recommended supply current I20 I49 Operating supply voltage range V62 V4 I9 Operating supply current range I20 I49 Conditions Ratings 5.0 5.0 10 13 30 4.7 to 5.3 4.7 to 5.3 7 to 13 11 to 15 28 to 35 Unit V V mA mA mA V V mA mA mA Package Dimensions unit : mm (typ) 3300 57.2 64 33 0.95 5.1max 0.51min 3.8 (4.25) 1.78 (1.01) 0.5 SANYO : DIP64S(600mil) 0.2 1 32 15.24 13.8 No.A1877-2/42 LV766116C μ-Controller Chip Absolute maximum ratings at Ta=25°C, VSS=0V Parameter Maximum Supply voltage Input voltage Output voltage Symbol VDD max VI VO1 VO2 Input/output voltage Peak output current Mean Output current Total output current Peak output current Mean output current Total output Current VIO IOPH IOMH ΣIOAH IOPL IOML1 IOML2 ΣIOAL1 ΣIOAL2 Pins CpuVDD XT1,RES# XT2,FILT CpuVDD2 Ports0,1 Ports04~07,1 Ports04~07,1 Ports04~07,1 Ports0,1 P02,P03,P06,P07 Ports1 P00,P01,P04,P05 P02,P03,P06,P07 Ports1 P00,P01,P04,P05 ･CMOS output ･For each pin. ･CMOS output ･For each pin. The total of all pins. For each pin For each pin For each pin The total of all pins. The total of all pins. Conditions Limits VDD[V] min -0.3 -0.3 -0.3 -0.3 -0.3 -10 -1 -25 20 1 8 45 16 typ ~ ~ ~ ~ ~ max +6.0 VDD+0.3 VDD+0.3 3.3V+0.3 VDD+0.3 mA unit V High level output current Low level output current μ-Conttoller Chip Recommended operating range at Ta=-10°C to +65°C, VSS=0V Parameter Operating supply voltage range Hold voltage High level input Voltage Symbol VDD VHD VIH1 VIH2 VIH3 Low level input Voltage VIL1 VIL2 VIL3 Operation cycle time (*3) tCYC1 tCYC2 Oscillation frequency range FmVCO1 FmVCO2 (*4) FmRC FsX’tal (*4) tmsVCO XT1(P07), XT2(P06) Pins CpuVDD CpuVDD Ports0,1, P00 port input /interrupt Port00 Watch-dog timer RES# Ports0,1, P00 port input /interrupt Port00 Watch-dog timer RES# All functions operating OSD and Data slicer are not operating Built-in VCO1 Oscillation System clock Built-in VCO2 OCKSEL=0 oscillation OCKSEL=1 OSD clock Built-in RC oscillation At the 32.768KHz crystal Oscillating See the figure1 ･after the HOLD mode ･Power-On Conditions 0.229µs≤tCYC≤200µs RAMs and the registers data are kept in HOLD mode. 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 0.231 13.0 12.5 16.6 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 0.3 1.0 32.768 300 2.0 KHz mS Limits VDD[V] min. 4.5 2.0 0.3VDD +0.7 0.9VDD 0.75VDD VSS VSS VSS 0.231 200 MHz typ. max. 5.5 5.5 VDD VDD VDD 0.1VDD +0.4 0.8VDD -1.0 0.25VDD µs unit V Oscillation stabilizing time (*3) Relational expression between Tcyc and oscillation frequency; 1/1 frequency dividing: 3/FmVCO1, 1/2 frequency dividing: 6/FVCO1. (*4) OCKSEL is the selectable register for OSD clock frequency. (See the LC873600 users manual for details.) (*5)When the base timer count of clock accuracy is necessary , use the port terminal (two ports) as the crystal oscillation. (See the [11 μ-Controller Chip Crystal Oscillation Circuit and Sample Characteristics] for details.) No.A1877-3/42 LV766116C BIP Chip Electrical Characteristics at Ta=25°C, ICC=I9=10mA ICC=I20=13mA ICC=I49=30mA VCC=V62= V4=5.0V Parameter [Circuit voltage, current] Horizontal supply voltage Logic supply voltage RGB supply voltage IF supply current Video supply current [VIF block] Maximum RFAGC voltage Minimum RFAGC voltage RF AGC Delay Pt (@DAC=0) RF AGC Delay Pt (@DAC=63) Input sensitivity Sync signal tip level Video output amplitude Video S/N C-S beat level Differential gain Differential phase APC pull-in range(U) APC pull-in range(L) NTSC Trap1(4.5MHz) BG Trap1(5.5MHz) I Trap1(6.0MHz) DK Trap1(6.5MHz) [SIF block] FM detection output voltage FM limiting sensitivity FM detection output f characteristics FM detection output distortion SIF S/N [AUDIO block] Volume gain (Stereo mode) AVGT AFREQT ATHDT ANOT ACTT AVGM AFREQM ATHDM ANOM AMUTE ABT DIN Audio DIN Audio DIN Audio 1kHz DIN Audio DIN Audio DIN Audio 1kHz 1kHz -3.0 − − − − -3.0 − − − − -0.5 0.0 20 0.2 -75 -80 0.0 20 0.2 -75 -80 0 +3.0 30 0.7 -70 -70 +3.0 30 0.7 -70 -70 0.5 dB kHz % dBV dB dB kHz % dBV dB dB SOADJ SLS SF STHD SSN FM=±50kHz Output -3dB fm=100kHz FM=±50kHz DIN Audio 500 － -1.0 － 45.0 640 － 0 － － 780 60 5.0 3.0 － mVrms dBµ dB % dB VRFH VRFL RFAGC0 RFAGC63 Vi VOtip VO S/N IC-S DG DP fPU fPL NTR1 BTR1 ITR1 DTR1 CW=80 dBµ, DAC=0 CW=80 dBµ, DAC=63 DAC=0 DAC=63 Output-3db CW=80 dBµ 80dBu,AM=78%,fm=15kHz CW=80 dBµ V4.43MHz/V1.07MHz 80 dBµ, 87.5% Video MOD 80 dBµ, 87.5% Video MOD 4.3 0 90 − − 1.1 1.90 40 35 − − 2.0 1.5 − − − − 4.7 0.3 − − − 1.4 2.00 45 − 5.0 5.0 − − − − − − 5 0.7 − 80 46 1.7 2.10 − − 15 10.0 − − -27 -27 -27 -27 Vdc Vdc dBµ dBµ dBµ Vdc Vp_p dB dB % deg MHz MHz dB dB dB dB V20 V9 V49 I62 I4 I20=13mA I9=10mA I49=30mA V62=5.0V V4=5.0V 4.7 3.0 7.8 56 65 5.0 3.3 8.15 65 77 5.3 3.6 8.5 74 89 V V V mA mA Symbol Conditions min typ max Unit Frequency characteristic (Stereo mode) Total harmonic distortion (Stereo mode) Output voltage noise Cross talk Volume gain (Stereo mode) (Stereo mode) (Mono mode) Frequency characteristic (Mono mode) Total harmonic distortion (Mono mode) Output voltage noise Mute L/R Balance (Mono mode) No.A1877-4/42 LV766116C Parameter [Video block] Video overall gain (Contrast max) Contrast adjustment Characteristics (Normal/max) Contrast adjustment characteristics (Min/max) Video frequency Characteristics 1 NTSC Video frequency characteristics 2 PAL Video frequency characteristics 3 WIDE Video frequency characteristics 4 APF Chroma trap amount PAL Chroma trap amount NTSC DC restoration rate 1 DC restoration rate 2 DC restoration rate 3 DC restoration rate 4 Y-DL TIME1 Y-DL TIME2 Y-DL TIME3 Y-DL TIME4 Y-DL TIME Ajust1 Y-DL TIME Ajust2 Black stretch gain max Black stretch gain mid Black stretch gain min Black stretch start point max (70IRE ΔV) Black stretch start point mid (50IRE ΔV) Black stretch start point min (40IRE ΔV) Sharpness variability range NTSC CONT127 CONT64 CONT0 BW1 BW2 BW3 BW4 CtrapP CtrapN ClampG1 ClampG2 ClampG3 ClampG4 TdY1 TdY2 TdY3 TdY4 TdYa1 TdYa2 BKSTmax BKSTmid BKSTmin BKSTTHmax BKSTTHmid BKSTTHmin Sharp32T1 (trap 1 mid) Sharp63T1 (trap 1 max) (trap 1 min) Sharp0T1 Sharp32T2 (trap 2 mid) Sharp63T2 (trap 2 max) (trap 2 min) Sharp0T2 Sharp32T4 Sharpness variability range 6MHz TRAP (trap 4 mid) Sharp63T4 (trap 4 max) (trap 4 min) Sharp0T4 1.8MHz/100kHz , Y Filter.sys = 00 2.2MHz/100kHz , Y Filter.sys = 01 2.3MHz/100kHz , Y Filter.sys = 10 3.4MHz/100kHz , Y Filter.sys = 00,Y APF=1 Y Filter.sys = 01 Y Filter.sys = 00 DC.Rest=00 DC.Rest=01 DC.Rest=10 DC.Rest=11 Y Filter.Sys=00 Y Delay Ajust=0100 Y Filter.Sys=01 Y Delay Ajust=0100 Y Filter.Sys=11,Delay Test=1 Y Delay Ajust=0100 Y Filter.Sys=10 Y Delay Ajust=0100 Y Filter.Sys=00 Y Delay Ajust=0000 Y Filter.Sys=00 Y Delay Ajust=0111 Blk.Str.Gain=10 ,Blk.Str.Start=01 Blk.Str.Gain=01 ,Blk.Str.Start=01 Blk.Str.Gain=00 ,Blk.Str.Start=01 Blk.Str.Gain=01 ,Blk.Str.Start=10 Blk.Str.Gain=01 ,Blk.Str.Start=01 Blk.Str.Gain=01 ,Blk.Str.Start=00 F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 17.0 8.0 1.0 -4.0 -5.0 -5.0 1.5 9.0 -14.0 1.5 8.5 -14.0 1.5 10.0 -14.0 95.0 102.0 105.0 118.0 11.0 -7.0 -18.0 -6.0 -6.0 -6.0 -6.0 13.5 -4.5 -15.5 -3.0 -3.0 -3.0 -3.0 -26.0 -26.0 100.0 107.0 112.0 128.0 1.40 1.20 1.60 1.15 1.25 1.45 26.0 19.0 11.0 0.0 0.0 0.0 3.0 12.0 -9.0 3.0 11.5 -11.0 5.0 13.5 -11.0 42.0 33.0 26.0 6.0 5.0 5.0 6.0 15.0 -7.5 6.0 15.0 -8.0 8.0 17.0 -7.0 16.0 -2.0 -11.0 0.0 0.0 0.0 0.0 -20.0 -20.0 105.0 112.0 120.0 136.0 dB dB dB dB dB dB dB dB dB % % % % ns ns ns ns ns ns IRE IRE IRE IRE IRE IRE dB dB dB dB dB dB dB dB dB Symbol Conditions min typ max Unit Sharpness variability range PAL No.A1877-5/42 LV766116C Parameter White peak limiter effective point1 White peak limiter effective point2 White peak limiter effective point3 White peak limiter effective point4 Y gamma Start effective point 1 Y gamma Start effective point 2 Y gamma Start effective point 3 Y gamma gain 1 Y gamma gain 2 Y gamma gain 3 Gray Mode Level Horizontal/vertical blanking output level Pre-shoot adjust1 Pre-shoot adjust2 Over-shoot adjust [RGB output(cutoff drive)block] Brightness control (Normal) Brightness control (Normal-H) Hi brightness (max) Low brightness (min) Cutoff control (Bias control) Resolution Sub-bias control Resolution RGB Drive adjustment Maximum output RGB Output attenuation [Video SW block] Video signal input 1DC voltage Video signal input 1AC voltage Video signal input 2DC voltage Video signal input 2AC voltage Video signal input 3DC voltage Video signal input 3AC voltage Video signal input 4DC voltage Video signal input 4AC voltage SVO pin DC voltage SVO pin AC voltage SVO pin Ycmix AC Voltage VIN1DC VIN1AC VIN2DC VIN2AC VIN3DC VIN3AC VIN4DC VIN4AC SVODC SVOAC SVOYC Video SW.=00 Video SW.=00 Video SW.=01 Video SW.=01 Video SW.=10 Video SW.=10 Video SW.=11 Video SW.=11 Video SW.=01,SVO SW=1 YCMIX=0 Video SW.=01,SVO SW=1 YCMIX=0 Video SW.=01,SVO SW=1 YCMIX=1 1.6 1.7 0.1 1.9 1.9 1.9 1.9 2.2 1 2.2 1 2.2 1 2.2 1 1.9 2 0.14 2.2 2.3 0.18 2.5 2.5 2.5 2.5 V Vpp V Vpp V Vpp V Vpp V Vpp Vpp (min) (max) BRT64 BRT64H BRT127 BRT0 Vbias0 Vbias255 Vbiassns Vsbiassns RGBout127 RGBout0 1.8 3.3 40.0 -60.0 2.3 3.1 － 1.5 5 2.3 3.7 50.0 -50.0 2.8 3.6 3.5 7 1.7 10 2.7 4.1 60.0 -40.0 3.3 4.1 － 2.3 13 V V IRE IRE V V mV/Bit mV/Bit Vpp dB Symbol WPL1 WPL2 WPL3 WPL4 YGST1 YGST2 YGST3 YGGA1 YGGA2 YGGA3 GRAY RGBBLK PreShoot1 PreShoot2 OverShoot Pre-shoot adj.=00 Pre-shoot adj.=11 Over-shoot adj.=11 Conditions APL=100% WPL=00 APL=100% WPL=01 APL=100% WPL=10 APL=100% WPL=11 Y Gamma Start=00 Y Gamma GAIN=01 Y Gamma Start=01 Y Gamma GAIN=01 Y Gamma Start=10 Y Gamma GAIN=01 Y Gamma Start=01 Y Gamma GAIN=00 Y Gamma Start=01 Y Gamma GAIN=01 Y Gamma Start=01 Y Gamma GAIN=10 GLAY MODE=1, Cross B/W=10 12.5 0.0 0.92 1.08 1.08 min 130.0 90.0 70.0 50.0 typ 160.0 125.0 105.0 85.0 55 65 68 220 250 260 16.0 0.1 0.97 1.13 1.13 19.5 0.5 1.02 1.18 1.18 max 190.0 140.0 130.0 120.0 Unit IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE V No.A1877-6/42 LV766116C Parameter [Chroma block]: PAL/NTSC common B-Y/Y amplitude ratio Color control characteristics 1 Color control characteristics 2 Color control sensitivity fsc output level Residual higher harmonic level B Residual higher harmonic level R Residual higher harmonic level G [Chroma block]: PAL ACC amplitude characteristics 1 ACC amplitude characteristics 2 Demodulation output ratio R-Y/B-Y:PAL Demodulation output ratio G-Y/B-Y :PAL Demodulation output ratio G-Y/R-Y :PAL Demodulation angle R-Y/B-Y :PAL Killer operating point 0 (PAL) Killer operating point 3 (PAL) ACCM1_P ACCM2_P RB_P GB_P Input:+6dB/0dB 0dB=40IRE Input:-20dB/0dB R-Y/B-Y_GainBalance, R-Y/B-Y_Angle=Center R-Y/B-Y_GainBalance， R-Y/B-Y_Angle=Center, R-Y= no-signal R-Y/B-Y_GainBalance， R-Y/B-Y_Angle=Center, B-Y= no-signal R-Y/B-Y_GainBalance， R-Y/B-Y_Angle=Center 0dB=40IRE 0dB=40IRE KILLP0-KILLP3 0.7 0.7 0.50 -0.24 1.0 1.0 0.56 -0.19 1.2 1.1 0.67 -0.17 ratio ratio ratio ratio CLRBY CLRMN CLRMM CLRSE FSC40 E_CAR_B E_CAR_R E_CAR_G a reference value Color MAX/CEN Color MAX/MIN 75 1.6 30 1 100 2.0 40 2 350 300 300 300 150 2.4 50 4 % ratio dB %/bit mVpp mVpp mVpp mVpp Symbol Conditions min typ max Unit GR_P ANGRB_P KILLP0 KILLP3 -0.56 85 -35 -38 0.5 350 -0.51 90 -0.46 95 -22 -24 6.0 ratio °C dB dB dB Hz Difference between two Killer operating points DKILLP (PAL) APC pull-in range (+) APC pull-in range (-) [Chroma block]:NTSC ACC amplitude characteristics 1 ACC amplitude characteristics 2 Demodulation output ratio R-Y/B-Y: NTSC Demodulation output ratio G-Y/B-Y: NTSC Demodulation angle B-Y/R-Y : NTSC Demodulation angle G-Y/B-Y : NTSC Killer operating point 0 (NTSC) Killer operating point 3 (NTSC) ACCM1_N ACCM2_N RB_N GB_N ANGBR_N ANGGB_N KILLN0 KILLN3 PULIN+_P PULIN-_P -350 Hz Input:+6dB/0dB 0dB=40IRE Input:-20dB/0dB R-Y/B-Y_GainBalance， R-Y/B-Y_Angle =Center R-Y/B-Y_GainBalance， R-Y/B-Y_Angle =Center R-Y/B-Y_GainBalance， R-Y/B-Y_Angle =Center R-Y/B-Y_GainBalance， R-Y/B-Y_Angle =Center 0dB=40IRE 0dB=40IRE KILLN0-KILLN3 0.7 0.7 0.80 0.22 95 230 -40 -43 0.5 350 1.0 1.0 0.90 0.27 105 240 1.2 1.1 1.00 0.38 111 250 -27 -29 6.0 ratio ratio ratio ratio °C °C dB dB dB Hz Difference between two Killer operating points DKILLN (NTSC) APC pull-in range (+) APC pull-in range (-) Tint center Tint variable range (+) Tint variable range (-) Cr Output amplitude Cb Output amplitude PULIN+_N PULIN-_N TINCEN TINT+ TINTCBCR-R CBCR-B -350 -10 0 10 -35 35 CbCr_IN=1 ,Cross B/W=01 CbCr_IN=1 ,Cross B/W=01 2.5 3.25 5.0 5.75 Hz deg deg deg Vpp Vpp No.A1877-7/42 LV766116C Parameter [Filter block]:Chroma BPF Characteristic C-BPF1A (3.93MHz) C-BPF1B (4.73/4.13MHz) C-BPF1C (4.93/3.93MHz) C-BPF2A (3.93MHz) C-BPF2B (4.73/4.13MHz) C-BPF2C (4.93/3.93MHz) APC pull-in range (+) APC pull-in range (-) Tint center Tint variable range (+) Tint variable range (-) Cr Output amplitude Cb Output amplitude [Filter block]:Chroma BPF Characteristic C-BPF1A (3.93MHz) C-BPF1B (4.73/4.13MHz) C-BPF1C (4.93/3.93MHz) C-BPF2A (3.93MHz) C-BPF2B (4.73/4.13MHz) C-BPF2C (4.93/3.93MHz) [Deflection block] Horizontal free-running frequency Horizontal pull-in range Horizontal output pulse width Horizontal output pulse saturation voltage Vertical free-running cycle 50 Vertical free-running cycle 60 Horizontal output pulse phase Horizontal output pulse phase Horizontal position adjustment range Horizontal position adjustment maximum variability width Horizontal blanking left @0 Horizontal blanking left @7 Horizontal blanking right @0 Horizontal blanking right @7 Horizontal output stop voltage Horizontal phase bow correction @16 Horizontal phase bow correction @0 Horizontal phase bow correction @31 Horizontal phase angle correction @16 Horizontal phase angle correction @0 Horizontal phase angle correction @31 FH FH PULL H duty V Hsat VFR50 VFR60 HPHCENpal HPHCENnt HPH range HPH step BLKL0 BLKL7 BLKR0 BLKR7 H stop HBOW16 HBOW0 HBOW31 HANG16 HANG0 HANG31 H.BLK.L:000 H.BLK.L:111 H.BLK.R:000 H.BLK.R:111 reference 8000 11500 -1600 1800 3.30 -0.5 0.7 -1.5 -0.5 0.4 -1.3 9000 12500 -600 2800 3.60 0 1.2 -1.0 0 0.9 -0.8 5bit 15470 ±400 36.1 0 312.0 262.0 3.8 3.8 37.6 0.2 312.5 262.5 5.8 5.8 ±1.8 180.0 10000 13500 400 3800 3.90 0.5 1.7 -0.5 0.5 1.4 -0.3 39.1 0.4 313.0 263.0 7.8 7.8 15670 15870 Hz Hz µs V H H µs µs µs ns ns ns ns ns V µs µs µs µs µs µs CBPF1A CBPF1B CBPF1C CBPF2A CBPF2B CBPF2C Reference: 4.43MHz C.Filter.Sys=10 Reference: 4.13MHz C.Filter.Sys=10 Reference: 3.93MHz C.Filter.Sys=10 Reference: 4.43MHz C.Filter.Sys=11 Reference: 4.13MHz C.Filter.Sys=11 Reference: 3.93MHz C.Filter.Sys=11 -6.0 -2.5 -3.5 -6.0 -4.0 -5.5 -3.0 1.5 2.0 -3.0 0.0 0.0 -1.0 5.5 7.5 -1.0 4.0 5.5 dB dB dB dB dB dB CBPF1A CBPF1B CBPF1C CBPF2A CBPF2B CBPF2C PULIN+_N PULIN-_N TINCEN TINT+ TINTCBCR-R CBCR-B CbCr_IN=1 ,Cross B/W=01 CbCr_IN=1 ,Cross B/W=01 40 1.7 1.8 3.4 3.7 -10 0 Reference: 4.43MHz C.Filter.Sys=10 Reference: 4.13MHz C.Filter.Sys=10 Reference: 3.93MHz C.Filter.Sys=10 Reference: 4.43MHz C.Filter.Sys=11 Reference: 4.13MHz C.Filter.Sys=11 Reference: 3.93MHz C.Filter.Sys=11 -7.5 -2.5 -3.5 -6.0 -4.0 -5.5 350 -350 10 -40 -3.0 1.5 2.0 -3.0 0.0 0.0 -1.0 5.5 7.5 -1.0 4.0 5.5 dB dB dB dB dB dB Hz Hz °C °C °C Vpp Vpp Symbol Conditions min typ max Unit No.A1877-8/42 LV766116C Parameter Vertical ramp output amplitude PAL @64 Vertical ramp output amplitude NTSC @64 Vertical ramp output amplitude PAL @0 Vertical ramp output amplitude NTSC @0 Vertical ramp output amplitude PAL @127 Vertical ramp output amplitude NTSC @127 Vertical ramp DC voltage @32 Vertical ramp DC voltage @0 Vertical ramp DC voltage @63 Vertical position @8 Vertical position @0 Vertical position @15 Vertical size Correction @0 Vertical linearity @16 Vertical linearity @0 Vertical linearity @31 Vertical S-shaped correction @16 Vertical S-shaped correction @0 Vertical S-shaped correction @31 Horizontal size correction @0 East/West DC Voltage@64 East/West DC Voltage@0 East/West DC Voltage@127 East/West amplitude@64 East/West amplitude@0 East/West amplitude@127 East/West tilt@64 East/West tilt@0 East/West tilt@127 East/West corner top East/West corner bottom EWcorTOP EWcorBOT EWDC:1111111,EWCORSW:1 EWCORTOP:00000-11111 EWDC:1111111,EWCORSW:1 EWCORBOTTOM: 00000-11111 0.55 0.95 1.10 1.50 1.65 2.05 V V Ewtilt64 EWtilt0 Ewtilt127 EWDC:1111111,EWCORSW:1 EWTILT:1000000 EWDC:1111111,EWCORSW:1 EWTILT:0000000 EWDC:1111111,EWCORSW:1 EWTILT:1111111 -0.20 -1.10 0.80 0.30 -0.60 1.30 0.80 -0.10 1.80 V V V EWamp64 EWamp0 EWamp127 EWDC:1111111 EWAMP:1000000 EWDC:1111111 EWAMP:0000000 EWDC:1111111 EWAMP:1111111 1.70 -0.5 2.00 2.20 0.00 2.50 2.70 0.50 3.00 Vp-p Vp-p Vp-p EWdc64 Ewdc0 Ewdc127 EWDC:1000000 EWDC:0000000 EWDC:1111111 1.80 0.80 2.80 2.30 1.30 3.30 2.80 1.80 3.80 Vdc Vdc Vdc H size comp H.COMP:000 0.18 0.28 0.38 V Vlin16 Vlin0 Vlin31 Vscor16 Vscor0 Vscor31 V.LIN:10000 V.LIN:00000 V.LIN:11111 V.SC:10000 V.SC:00000 V.SC:11111 0.7 1.30 0.35 0.70 1.10 0.30 1.00 1.60 0.65 1.00 1.40 0.60 1.30 1.90 0.95 1.30 1.70 0.90 ratio ratio ratio ratio ratio ratio Vpsizecomp V.COMP:000 0.89 0.93 0.97 ratio Vdc32 Vdc0 Vdc63 Vshift8 Vshift0 Vshift15 V.DC:10000 V.DC:00000 V.DC:11111 V.SHIFT:1000 V.SHIFT:0000 V.SHIFT:1111 2.10 1.80 2.55 500 0 950 2.40 2.10 2.85 550 50 1000 2.70 2.40 3.15 600 100 1050 Vdc Vdc Vdc µs µs µs Vspal64 Vsnt64 Vspal0 Vsnt0 Vspal127 Vsnt127 V.SIZE:1000000 V.SIZE:1000000 V.SIZE:0000000 V.SIZE:0000000 V.SIZE:1111111 V.SIZE:1111111 0.75 0.75 0.30 0.30 1.25 1.25 1.05 1.05 0.60 0.60 1.55 1.55 1.35 1.35 0.9 0.9 1.85 1.85 Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Symbol Conditions min typ max Unit No.A1877-9/42 LV766116C Test Conditions at Ta=25°C, ICC=I9=10mA, ICC=I20=13mA, ICC=I49=30mA, VCC=V62= V4=5.0V Parameter [Circuit voltage,current] Horizontal supply voltage (pin 20) Logic supply voltage (pin 9) RGB supply voltage(pin 49) IF supply current(pin 62) Video / vertical supply current (pin 4) V20 V9 I49 I62 I4 Symbol Test point Input signal Test method Bus conditions 20 9 49 62 4 No signal No signal No signal No signal No signal Apply a current of 13mA to pin 20 and measure the voltage at pin 20. Initial Apply a current of 11mA to pin 9 and measure Initial the voltage at pin 9. Apply a current of 12mA to pin 49 and measure the voltage (V) at pin49. Initial Apply a voltage of 5.0V to pin 62 and measure Initial the incoming DC current (mA). (IF AGC 2.5V applied) Apply a voltage of 5.0V to pin 4 and measure Initial the incoming DC current (mA). • VIF Block Input Signals and Test Conditions 1. Input signals must be input to the PIF IN (pin 56) in the Test Circuit. 2. Input signal voltage values are the levels at the VIF IN (pin 56) in the Test Circuit. 3. Signal contents and signal levels 4. Bus control condition: VIF SYS.SW=”000”, APC.SIS.TEST="0",SVO.SW="0",VIDEO LEVEL=”ADJ Input signal SG1 CW SG2 CW SG3 CW SG4 CW SG5 38.9MHz 87.5% Video Mod. 10-stairstep wave (Subcarrier: 4.43MHz) Frequency variable 33.4MHz 34.47MHz Waveform Conditions 38.9MHz SG6 38.9MHz fm=15kHz,AM=78% SG7 50IRE 50IRE Luma 38.9MHz, 90dBu 87.5% Video Mod. 50IRE Luma (Carrier: variable) No.A1877-10/42 LV766116C Parameter [VIF block ] Maximum RF AGC voltage Minimum RF AGC voltage RF AGC Delay Pt (@DAC=0) RF AGC Delay Pt (@DAC=63) Input sensitivity Sync tip level Video output amplitude Video S/N C-S beat level VRFH VRFL RFAGC0 RFAGC63 Vi VOtip VO Symbol Test point Input signal Test method Bus conditions 58 58 58 58 61 61 61 61 SG1 80dBμ SG1 80dBμ SG1 SG1 SG6 SG1 80dBμ SG6 80dBμ SG1 80dBμ SG1 SG2 SG3 SG5 80dBμ SG5 80dBμ SG4 80dBμ Measure the DC voltage at pin 58. Measure the DC voltage at pin 58. Obtain the input level at which the DC voltage at pin 58 becomes 2.5V. Obtain the input level at which the DC voltage at pin 58 becomes 2.5V. Using an oscilloscope, observe the level at pin 61 and obtain the input level at which the waveform's amplitude becomes 1.4Vp-p. Measure the DC voltage at pin 61. Using an oscilloscope, adjust the waveform's amplitude at pin 61 to about 2Vpp and measure the waveform’s amplitude. * After this measurement, set "Video Level DAC" to the value adjusted . Measure the noise voltage (Vsn) at pin 61 with an RMS voltmeter through a 10kHz to 5.0MHz band-pass filter and calculate 20log(1.43/Vsn). Input a 80dBμ SG1 signal and measure the DC voltage (V60) at pin 60. Mix SG1=74dBμ, SG2=64dBμ, and SG3=64dBμ to enter the mixture in the VIF IN. Apply V60 to pin 60 from an external DC power supply. Using a spectrum analyzer, measure the difference between pin 61’s 4.43MHz component and 1.07MHz component. Using a vector scope, measure the level at Pin 61. Using a vector scope, measure the level at Pin 61. RF.AGC=”000000” RF.AGC=”111111” RF.AGC=”000000” RF.AGC=”111111” S/N IC-S 61 Differential gain Differential phase APC pull-in range (U),(L) DG DP fPU, fPL 61 61 61 NT Trap1 (4.5MHz) BG Trap 1 (5.5MHz) I Trap1 (6.0MHz) DK Trap1 (6.5MHz) NTR1 BTR1 ITR1 DTR1 61 61 61 61 SG7 SG7 SG7 SG7 Connect an oscilloscope to pin 61 and adjust the SG4 frequency to a frequency higher than 38.9MHz to bring the PLL into unlocked mode. (A beat signal appears.) Lower the SG4 frequency and measure the frequency at which the PLL locks again. In the same manner, adjust the SG4 frequency to a lower frequency to bring the PLL into unlocked mode. Higher the SG4 frequency and measure the frequency at which the PLL locks again. Determine the output level difference between carrier frequencies SIF.SYS=”00” of 1MHz and 4.5MHz.(Reference:1MHz) Determine the output level difference between carrier frequencies of 1MHz and 5.5MHz.(Reference:1MHz) Determine the output level difference between carrier frequencies of 1MHz and 6.0MHz.(Reference:1MHz) Determine the output level difference between carrier frequencies of 1MHz and 6.5MHz.(Reference:1MHz) SIF.SYS=”01” SIF.SYS=”10” SIF.SYS=”11” No.A1877-11/42 LV766116C •SIF Block (FM block) Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: IF.AGC.SW=“1”, SIF.SYS=”01”,DEEM-TC=”0”,FM.GAIN=”0” 2. SW: IF1=“ON”, pin 19=5V 3. Input signals are input to pin 52 and the carrier frequency is 5.5MHz. Parameter FM detection output voltage FM limiting sensitivity FM detection output ｆ characteristics (fm=100kHz) FM detection output distortion SIF.S/N Symbol SOADJ SLS SF Test point Input signal 90dBμ, fm=400Hz, FM=±50kHz fm=400Hz, FM=±50kHz 90dBμ, fm=100kHz FM=±50kHz 90dBμ, fm=400Hz, FM=±50kHz 90dBμ, CW Test method Measure the 400 Hz component (SV1:mVrms) of the FM detection output at pin 64. Measure the input level (dBμ) at which the 400Hz component of the FM detection output at pin 64 becomes -3dB relative to SV1. Set SW: IF1="OFF". Measure (SV2: mVrms) the FM detection output of pin 64. Calculate as follows: SF=20log(SV1/SV2) [dB] Measure the distortion factor of the 400Hz component of the FM detection output at pin 64. Measure the noise level (DIN AUDIO, SV4:mVrms) at pin 64. Calculate as follows: SSN=20log(SV1/SV4) [dB] Bus conditions 64 64 64 64 64 STHD SSN •Audio Block Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: Audio Mute ="0", A.MONI.SW="1", FM MUTE="1", Audio SW ="00", VOL FIL="0", IF AGC="1"MONO Mode="0", Volume (L/MONO) ="0000000" 2. Enter an input signal EXT1/EXT2-LIN from pin 2/pin8. 3. Enter an input signal EXT1/EXT2-RIN from pin 1/pin7. 4. Output signal LOUT is output to pin 50. 5. Output signal ROUT is output to pin 51. Parameter [AUDIO block] Volume gain (Stereo mode) Maximum output voltage (Stereo mode) Frequency characteristic (Stereo mode) Total harmonic distortion (Stereo mode) Output voltage noise (Stereo mode) Cross talk (Stereo mode) Volume gain (Mono mode) Maximum output voltage (Mono mode) Frequency characteristic (Mono mode) Total harmonic distortion (Mono mode) Output voltage noise (Mono mode) Mute L/R Balance ABT AVGT AVOT Symbol Test point Input signal Test method Bus conditions 50 2 2 50 50 51 50 2 2 50 50 50 51 AFREQT EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz EXT1-LIN(2PIN) EXT2-LIN(8PIN) =300mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms No signal EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz EXT1-LIN(2PIN) EXT2-LIN(8PIN) =300mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms No signal EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms EXT1-LIN(2PIN) EXT1-RIN(1PIN) EXT2-LIN(8PIN) EXT2-RIN(7PIN) =1KHz,300mVrms Measure the 1kHz component (V1:mVrms) at the LOUT(50PIN) and calculate as follows: AVGT=20log(V1/300) [dB] When the distortion (DIN.AUDIO) of the LOUT(pin50) is 1%, Measure the voltage level at the EXT-LIN (pin 2). Measure the voltage level (V2:mVrms) at the LOUT(pin50) and calculate as follows: AFT=20log(V2/300) [dB] When the AFT is –3dB, Measure the frequency at the EXT-LIN (pin 2). Measure the distortion (DIN.AUDIO) of the 1kHz component at the LOUT (50PIN). Measure the noise level (DIN AUDIO) at the LOUT (pin50). Measure the 1kHz component (V3:mVrms) at the ROUT (pin51) and calculate as follows: ACTT=20log(V3/300) [dB] Measure the 1kHz component (V4:mVrms) at the LOUT (pin50) Audio SW=10 Mono Mode=1 and calculate as follows: AVGM=20log(V4/300) [dB] When the distortion (DIN.AUDIO) of the LOUT(pin50) is 1%, Measure the voltage level at the EXT-LIN (PIN 2). Measure the voltage level (V5:mVrms) at the LOUT (pin50) and calculate as follows: AFM=20log(V5/300) [dB] When the AFM is –3dB, Measure the frequency at the EXT-LIN (PIN 2). Measure the distortion (DIN.AUDIO) of the 1kHz component at the LOUT (pin50). Measure the noise level (DIN AUDIO) at the LOUT (50PIN). Audio SW=10 Mono Mode=1 Audio SW=10 Mono Mode=1 Audio SW=10 Mono Mode=1 Mono Mode=1 ATHDT ANOT ACTT AVGM AVOM AFREQM ATHDM ANOM AMUTE Measure the 1kHz component (V8:mVrms) at the LOUT (PIN50) Audio.mute =1 and calculate as follows: AMUTE =20log(V8/300) [dB] Measure the 1KHz component(V9:mVrms) at the ROUT (PIN51) and calculate as follows: ABT=20Log(V1/V9) [dB] No.A1877-12/42 LV766116C • Video Block Input Signals and Test Conditions 1. C IN Input*chroma burst signal: 40 IRE 2. Y IN input signal 3. Bus control bit conditions: Initial test state ·l0IRE signal (L-0): NTSC standard sync signal 100IRE:714mV PEDESTAL LEVEL H SYNC 4.7μs (H/V SYNC: 40IRE: 286mV) · XIRE signal (L-X) XIRE (X= 0 to 100) 0 IRE · CW signal (L-CW) 20 IRE CW signal 50 IRE · BLACK STRETCH A point (0IRE to 99IRE) signal (L-BK) 60μs 100IRE …100IRE white signal as other H … 5 μs Point A · R/G/B IN Input signal · RGB Input signal 1 (0-1) to each 20μs 0.7V 0.35V 0.0VDC AB · RGB Input signal 2 (0-2) 20μs 30μs 5.0V 0.0VDC No.A1877-13/42 LV766116C Parameter [Video block] Video overall gain (Contrast max) Contrast adjustment characteristics (normal/max) Contrast adjustment characteristics (min/max) Video frequency Characteristics 1 (NTSC) BW1 L-CW CONT0 CONT64 CONT127 Symbol Test point Input signal Test method Bus conditions 46 46 46 L-50 L-50 Measure the output signal’s 50IRE amplitude (CNTHB Vp-p) CONTRAST:1111111 and calculate CONT127= 20log (CNTHB/0.357). and calculate CONT63= 20log (CNTCB/CNTHB). Y Gamma Start=11 Y Gamma Start=11 Measure the output signal’s 50IRE amplitude (CNTCB Vp-p) CONTRAST:1000000 L-50 Measure the output signal’s 50IRE amplitude (CNTLB Vp-p) CONTRAST:0000000 and calculate CONT0=20log (CNTLB/CNTHB). Y Gamma Start=11 SHARPNESS: 001010 With the input signal’s continuous wave=100kHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (PEAKDC Vpp). output signal’s continuous wave amplitude (CW1.8 Vpp). Calculate BW1=20Log (CW1.8/PEAKDC). With the input signal’s continuous wave=1.8MHz, measure the Y Gamma Start=11 46 Video frequency Characteristics 2 (PAL) Video frequency Characteristics 3 (6MHz TRAP) Video frequency Characteristics 4 (APF) Chroma trap amount PAL BW2 46 L-CW With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:01 output signal’s continuous wave amplitude (CW2.2 Vp-p). Calculate BW2=20Log (CW2.2/PEAKDC). SHARPNESS: 001010 Y Gamma Start=11 SHARPNESS: 001010 Y Gamma Start=11 SHARPNESS: 001010 Y APF:1 Y Gamma Start=11 BW3 L-CW With the input signal’s continuous wave=2.3MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (CW2.3 Vp-p). Calculate BW3=20Log (CW2.3/PEAKDC). 46 BW4 L-CW With the input signal’s continuous wave=3.4MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (CW3.4 Vp-p). Calculate BW3=20Log (CW3.4/PEAKDC). 46 CtraPP 46 L-CW With the input signal’s continuous wave=4.43MHz, measure Y Filter.sys:01 the output signal’s continuous wave amplitude (F0P Vp-p). Calculate CtraP=20Log (F0P/PEAKDC). Sharpness: 000000 Y Gamma Start=11 Chroma trap amount NTSC CtraPN L-CW With the input signal’s continuous wave=3.58MHz, measure Y Filter.sys:00 the output signal’s continuous wave amplitude (F0N Vp-p). Calculate CtraN=20Log (F0N/PEAKDC). Sharpness: 000000 Y Gamma Start=11 Sub.Bais:1111111 CONTRAST:0111111 Sub.Bais:1111111 Contrast:0111111 DCREST=00 BLK.STR.START=11 WPL=0 46 ClampG1 DC restoration rate 1 46 L-0 L-100 Measure the output signal’s 0IRE DC level (BRTPL V). Measure the output signal’s 0IRE DC level(DRVPH V) and 100IRE amplitude (DRVH Vp-p) and calculate ClampG=100×(1+(DRVPH-BRTPL)/DRVH). DC restoration rate 2 DC restoration rate 3 DC restoration rate 4 Y-DL TIME1 (NTSC) Y-DL TIME2 (PAL) Y-DL TIME3 ClampG2 ClampG3 ClampG4 TdY1 46 46 46 46 L-100 L-100 L-100 L-50 With DCREST = 01, carry out measurement similarly to the case of DCREST =01 the DC restoration rate 1. With DCREST = 10, carry out measurement similarly to the case of DCREST =10 the DC restoration rate 1. With DCREST = 11, carry out measurement similarly to the case of DCREST =11 the DC restoration rate 1. Obtain the time difference (the delay time) from when the rise Y Filter.sys:00 of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. YDELAY Ajust:100 TdY2 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:01 of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. YDELAY Ajust:100 TdY3 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:11 of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. YDELAY Ajust:100 Delay Test:1 YDELAY Ajust:100 Y-DL TIME4 (6MHz TRAP) Y-DL TIME Ajust1 TdY4 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:10 of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. TdYa1 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:00 of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. Y Delay Ajust:000 No.A1877-14/42 LV766116C Parameter Y-DL TIME Ajust2 Symbol TdYa2 Test point Input signal L-50 Test method Obtain the time difference (the delay time) from when the rise of the input signal's 50IRE amplitude to the output signal's 50IRE amplitude. Black stretch gain (MAX) BKST max L-BK Measure the 0IRE DC level(BKST1 V) at point A of the output signal in the Black Stretch Defeat (Black Stretch OFF) mode Measure the 0IRE DC level(BKST2 V) at point A of the output signal in the Black Stretch ON mode. Calculate BKST max=50 (BKST1-BKST2)/CNTHB. Black stretch gain (MID) Black stretch gain (MIN) Black stretch start max (60IRE ΔBlack) BKSTTH max BKST min BKST mid L-BK (A=0IRE) L-BK With Blk.str.gain = 01, carry out the same measurement as for the case of black stretch gain (MAX). With Blk.str.gain = 00, carry out the same measurement as for the case of black stretch gain (max). Measure the 60IRE DC level(BKST3 V) at point A of the output signal in the Black Stretch ON mode. Measure the 60IRE DC level(BKST4 V) at point A of the output signal in the Black Stretch Defeat (Black Stretch OFF) mode. Calculate BKSTTHmax=50 (BKST4-BKST3)/CNTHB. Black stretch start mid (50IRE ΔBlack) BKSTTH mid L-BK Measure the 50IRE DC level(BKST5 V) at point A of the output signal in the Black Stretch Defeat ON mode. Calculate BKSTTHmid=50 BKST6-BKST5)/CNTHB. Black stretch start min (40IRE ΔBlack) BKSTTH min L-BK Measure the 40IRE DC level(BKST7 V) at pointAof the output signal in the Black Stretch Defeat ON mode. Measure the 40IRE DC level(BKST8 V) at point A of the output signal in the Black Stretch Defeat (Black Stretch OFF) mode. Calculate BKSTTHmin=50 (BKST8-BKST7)/CNTHB. Sharpness variable range Sharp32T1 (NTSC) Blk.str.start=11 Y Filter.sys:10 Blk.str.gain=10 Blk.str.start=01 Y Filter.sys:10 Blk.str.gain=01 Blk.str.start=01 Y Filter.sys:10 Blk.str.gain=00 Blk.str.start=01 Y Filter.sys:10 L-BK Blk.str.gain=01 Blk.str.start=10 Y Filter.sys:10 Blk.str.gain=00 Blk.str.start=11 Y Filter.sys:10 Blk.str.gain=01 Blk.str.start=01 Y Filter.sys:10 Blk.str.gain=00 Blk.str.start=11 Y Filter.sys:10 Blk.str.gain=01 Blk.str.start=00 Y Filter.sys:10 Blk.str.gain=00 Blk.str.start=11 Y Filter.sys:10 Bus conditions Y Filter.sys:00 Y Delay Ajust:111 46 46 (A=0IRE) 46 46 (A=0IRE) 46 (A=60IRE) 46 (A=50IRE) 46 (A=40IRE) 46 L-CW With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (F01S32 Vp-p). Sharpness: 100000 Calculate Sharp32T1=20Log (F01S32/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 Y Filter.sys:00 Sharpness: 111111 Y Gamma Start=11 C_Kill.ON=1 Y Filter.sys:00 Sharpness: 000000 Y Gamma Start=11 C_Kill.ON=1 Y Filter.sys:01 Sharpness: 100000 Y Gamma Start=11 C_Kill.ON=1 Y Filter.sys:01 Sharpness: 111111 Y Gamma Start=11 C_Kill.ON=1 Y Filter.sys:01 Sharpness: 000000 Y Gamma Start=11 C_Kill.ON=1 (max) Sharp63T1 46 L-CW With the input signal’s continuous wave=2.2MHz, measure the output signal’s continuous wave amplitude (F01S63 Vpp). Calculate Sharp63T1=20Log (F01S63/PEAKDC). (min) Sharp0T1 46 L-CW With the input signal’s continuous wave=2.2MHz, measure the output signal’s continuous wave amplitude (F01S0 Vpp). Calculate Sharp0T1=20Log (F01S0/PEAKDC). Sharpness variable range Sharp32T2 (PAL) 46 L-CW With the input signal’s continuous wave=2.7MHz, measure the output signal’s continuous wave amplitude (F02S32 Vpp). Calculate Sharp32T3=20Log (F02S32/PEAKDC). (max) Sharp63T2 46 L-CW With the input signal’s continuous wave=2.7MHz, measure the output signal’s continuous wave amplitude (F02S63 Vpp). Calculate harp63T2=20Log (F02S63/PEAKDC). (min) Sharp0T2 46 L-CW With the input signal’s continuous wave=2.7MHz, measure the output signal’s continuous wave amplitude (F02S0 Vpp). Calculate Sharp0T2=20Log (F02S0/PEAKDC). No.A1877-15/42 LV766116C Parameter Symbol Test point Input signal L-CW Test method Bus conditions Sharpness variable range Sharp32T4 (6MHz TRAP) With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S32 Vpp). Calculate Sharp32T4=20Log (F04S32/PEAKDC). Sharpness: 100000 Y Gamma Start=11 C_Kill.ON=1 46 (max) Sharp63T4 L-CW With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S63 Vpp). Calculate Sharp63T4=20Log (F04S63/PEAKDC). Sharpness: 111111 Y Gamma Start=11 C_Kill.ON=1 46 (min) Sharp0T4 L-CW With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S0 Vpp). Calculate Sharp0T4=20Log (F04S0/PEAKDC). Sharpness: 000000 Y Gamma Start=11 C_Kill.ON=1 46 White peak limiter operating point 1 WPL1 L-100 Measure the ampritude(from pedestal to white) of the output signal WPL=00 with WPL=00. (PIN 45: 5V) Bigger the input signal and measure Y Gamma Start=11 the amplitude (from pedestal to white) of the output signal at which the output signal is clipped. (WP1) WPL1=WP1/CNTCB1*100 46 White peak limiter operating point 2 White peak limiter operating point 3 White peak limiter operating point 4 WPL2 L-100 Bigger the input signal and measure the amplitude(from pedestal to WPL=01 white) of the output signal at which the output signal is clipped with WPL=01. (WP2) WPL2=WP2/CNTCB1*100 Y Gamma Start=11 Y Gamma Start=11 46 WPL3 L-100 Bigger the input signal and measure the amplitude(from pedestal to WPL=10 white) of the output signal at which the output signal is clipped with WPL=10. (WP3) WPL3=WP3/CNTCB1*100 Y Gamma Start=11 Y Gamma GAIN=00 Y Gamma Start=11 46 WPL4 46 L-100 Bigger the input signal and measure the amplitude(from pedestal to WPL=11 white) of the output signal at which the output signal is clipped with WPL=11. (WP4) WPL4=WP4/CNTCB1*100 Y gamma start effective YGST1 point1 46 L-100 L-50 Measure the amplitude of the output signal (0 to 100IRE) with Y GAMMA START=3.Y GAMMA GAIN=0. (GAM0) Next measure the amplitude the output signal (0 to 50IRE) with Y Y Gamma GAIN=01 GAMMA START=1. Y GAMMA GAIN=1(GAM1) and calculate Y Gamma Start=00 YGS1= GAM1/GAM0*100 Y gamma start effective YGST2 point12 Y gamma start effective YGST3 point1 Y gamma gain 1 YGGA1 46 L-50 Measure the amplitude of the output signal (0 to 50IRE) with Y YGS2= GAM2/GAM0*100 Y Gamma GAIN=01 GAMMA START=1. Y GAMMA GAIN=1 (GAM2) and calculate Y Gamma Start=01 L-50 L-50 L-100 Measure the amplitude of the output signal (0 to 50IRE) (GAM3) and calculate YGS3= GAM3/GAM0*100 Y Gamma GAIN=01 Y Gamma Start=10 Y Gamma GAIN=00 46 46 Measure the amplitude of the output signal (0 to 50IRE).(GGAM1) Y Gamma Start =01 Measure the amplitude of the output signal (0 to 100IRE).(GGAM2) Calculate YGG1=100*GGAM1/(GGAM2-GGAM1) Y gamma gain 2 YGGA2 46 L-50 L-100 Measure the amplitude of the output signal (0 to 50IRE).(GGAM3) Y Gamma Start =01 Measure the amplitude of the output signal (0 to 100IRE).(GGAM4) Calculate YGG2=100*GGAM3/(GGAM4-GGAM3) Y Gamma GAIN=01 Y gamma gain 3 YGGA3 46 L-50 L-100 Measure the amplitude of the output signal (0 to 50IRE) .(GGAM5) Measure the amplitude of the output signal (0 to 100IRE).(GGAM6) Calculate YGG3=100*GGAM5/(GGAM6-GGAM5) Y Gamma Start =01 Y Gamma GAIN=10 GRAY MODE LEVEL GRAY Horizontal/vertical blanking output level Pre-shoot adjust1 PreShoot1 RGBBLK 46 46 L-100 Measure the DC level(deviation from pedestal)of pin46, and transfer IRE. Measure the DC level (RGBBLK V) for the output signal’s blanking period. L-100 Measure the pre-shoot width (Tpre) and over-shoot width (Tover) at rise of 100IRE amplitude of the output signal, and calculate PreShoot = Tpre / Tover. L-100 With Pre-shoot adj. = 11, carry out the same measurement as for the case of Pre-Shoot 1. CROSS B/W:10 GRAY MODE:1 46 Pre-shoot adj.=00 Y Filter.sys:00 Sharpness=111111 Pre-shoot adj.=11 Y Filter.sys:00 Sharpness=111111 Pre-shoot adjust2 PreShoot2 46 No.A1877-16/42 LV766116C Parameter Over-shoot adjust Symbol OverShoot Test point Input signal L-100 Test method Bus conditions 46 With Over-shoot adj. = 11Measure the pre-shoot width (Tpre) and Over-shoot adj.=11 over-shoot width (Tover) at rise of 100IRE amplitude of the output signal, and calculate OverShoot = Tover/Tpre Bus control bit conditions: Contrast=127 Y Filter.sys:00 Sharpness=111111 Contrast:1111111 [RGB output block] (Cutoff, drive block) Brightness control (normal) BRT64 48 47 46 L-0 Measure the 0IRE DC levels of the respective output signals of R Bright: 1000000 output (48), G output (47), and B output (46). Assign the measured values to BRTPCR, BRTPCG, and BRTPCB V, respectively. Calculate BRT63=(BRTPCR+BRTPCG+BRTPCB)/3 Brightness control (normal-H) Brightness control (max) Brightness control (min) Bias (cutoff) control (min) BRT64H BRT127 46 46 46 48 47 46 L-0 L-0 BRT0 Vbias0 L-0 L-50 Measure the 0IRE DC level of the output signal of B output (46) Bright: 1000000 and assign the measured value to BRTPCBH. B.BIAS: 11111111 Sub Bias: 1111111 Measure the 0IRE DC level of the output signal of B output (46) Bright: 1111111 and assign the measured value to BRTPHB. B.BIAS: 11111111 Sub Bias: 1111111 Calculate BRT127=50×(BRTPHBH-BRTPCB)/CNTHB. Measure the 0IRE DC level of the output signal of B output (46) Bright: 0000000 and assign the measured value to BRTPLB. B.BIAS: 11111111 Calculate BRT0=50 (BRTPLB-BRTPCBH)/CNTHB. Sub Bias: 1111111 Measure the 0IRE DC levels (Vbias0χV)of Sub.Bias: 1111111 the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) Bias (cutoff) control (max) Vbias255 48 47 46 L-50 Measure the 0IRE DC levels (Vbias255χV)of the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) Sub.Bias: 1111111 R/G/B.BIAS:11111111 Bias (cutoff) control resolution Vbiassns 48 47 46 L-50 Measure the 0IRE DC levels (BAS80χV) of the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) Measure the 0IRE DC levels (BAS48χV)of the respective output signals of R output (48), G output (47), and B output (46). Calculate Vbiassnsχ= (BAS80χ-BAS48χ)/32 Set Sub.Bias 64 and measure the 0IRE DC levels (SB64χV) of the respective output signals of R output (48),G output(47), and B output(46).and next,set Sub.Bias 42,then measure the same as before. Calculate Vsbiassnsχ-(SB64χ-SB42χ)/22 R/G/B.BIAS:01010000 Sub.Bias: 1111111 R/G/B.BIAS:00110000 Sub.Bias: 1111111 Sub-bias control resolution Vsbiassns 48 47 46 L-50 Sub.Bias: 1000000/0101010 Contrast: 0111111 R/G/B.BIAS:11111111 Drive adjustment maximum output RGBout127 48 47 46 L-100 Measure the 100IRE amplitudes (DRVHχVp-p)of the respective output signals of R output (48),G output(47) and B output (46). (χ: R, G and B) Bright: 0000000 R/G/B DRIVE: 1111111 Contrast: 1000000 Output attenuation RGBout0 48 47 46 L-100 Measure the 100IRE amplitudes (DRVLχVp-p) of the respective Bright: 0000000 output signals of R output (48), G output (47), and B output (46). R/G/B DRIVE: 0000000 (χ: R, G and B) Contrast: 1000000 Calculate RGBout0χ=20log(DRVHχ/DRVLχ) No.A1877-17/42 LV766116C Parameter [VIDEO SW [Block] Video signal input 1DC voltage Video signal input 1 AC voltage Video signal input 2DC voltage Video signal input 2 AC voltage Video signal input 3DC voltage Video signal input 3AC voltage Video signal input 4DC voltage Video signal input 4AC voltage SVO terminal DC voltage SVO terminal AC voltage SVO terminal Ycmix AC Voltage SVOYC SVOAC SVODC VIN4AC VIN4DC VIN3AC VIN3DC VIN2AC VIN2DC VIN1AC VIN1DC Symbol Test point Input signal Test method Bus conditions 5 5 3 3 10 10 7 7 61 L-100 Input signals to pin 5 and measure the voltage of the pedestal. Video SW:01 Pin 5 recommended input level Video SW:01 L-100 Input signals to pin 3 and measure the voltage of the pedestal. Video SW:00 Pin 3 recommended input level Video SW:00 Input signals to pin 10 and measure the voltage of the pedestal. Video SW:10 Pin 10 recommended input level Video SW:10 Input signals to pin 7 and measure the voltage of the pedestal. Video SW:11 Pin 7 recommended input level L-100 Video SW:11 Input signals to pin 5 and measure the voltage of the pedestal at Video SW:01 pin 61. SVO SW:1 YCMIX:0 61 61 L-100 The signal is input to 5PIN, and the amplitude of the signal of VIDE0 SW:01 61PIN is measured. SVO SW:1 YCMIX:0 L-0 L-CW Y signal is input to 7PIN, and C signal of 8PIN is input, and the VIDE0 SW:11 amplitude of 61PIN (SVO) is measured. SVO SW:1 YCMIX:1 No.A1877-18/42 LV766116C •Chroma Block Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. VIF, SIF blocks: No signal 2. Deflection Block: Horizontal/vertical composite sync signals are input and the deflection block must be locked into the sync signals (Refer to the Deflection Block Input Signals and the Test Conditions). 3. Bus control conditions: Set the following conditions unless otherwise specified. Y Input is 7 Pin (YC-Y), C Input is 8 Pin (YC-C) (Video SW=3, C. Ext=1) Other DAC except the above-mentioned conditions is all initial conditions. 4. Y Input condition: No signal unless otherwise specified. (Sync is necessary to obtain synchronization). 5. How to calculate the demodulation ratio and angle: B-Y axis angle=tan-1(B ( 0) / B (270))+270° R-Y axis angle=tan-1(R (180) / R ( 90))+90° G-Y axis angle=tan-1(G (270) / G (180))+180° B-Y axis amplitude Vb=SQRT(B(0)*B(0)+B(270)*B(270)) R-Y axis amplitude Vr=SQRT(R(180)*R(180)+R(90)*R(90)) G-Y axis amplitude Vg=SQRT(G(180)*G(180)+G(270)*G(270)) R-Y axis 90° R(90) R(180) 180° G(180) G(270) B(270) B(0) 0° B-Y axis G-Y axis 270° No.A1877-19/42 LV766116C 6. Chroma input signal As for the PAL signal, the burst swings such as 135° and 225° every horizontal period. Chroma describes the phase caused when the burst occurs at 135°. As for the NTSC signal, the burst occurs constantly at 180°. The figures below are based on the phase of NTSC. When a PAL signal is generated, adjust the phase and then enter signals. The item common to both PAL and NTSC is the PAL signal. For those other than this, the measurement must be performed for each individual signals. The condition of fsc: Set the following conditions unless otherwise specified. PAL =4.433619MHz NTSC =3.579545MHz C-1 40IRE Burst 0 º 90 º 180 º 270 º X IRE signal (L-X) C-2 fsc 40IRE 40IRE Burst C-3 fsc 346 deg 40IRE fsc CW (Note: fsc±N*fh when the frequency is specified. Ｎ should be a natural number and the nearest value should be used.) Burst C-4 Burst B-Y only C-5 Burst R-Y only C-6 0.35V 0.35V *There is no signal for H, V blanking period. No.A1877-20/42 LV766116C Parameter Symbol Test point Input signal Test method Bus conditions [Chroma block]: PAL/NTSC common B-Y/Y amplitude ratio CLRBY 46 Color control Characteristics 1 CLRMN 46 46 46 46 47 48 Color control Characteristics 2 Color control sensitivity Residual higher harmonic level B Residual higher harmonic level G Residual higher harmonic level R [Chroma block]: PAL ACC amplitude characteristics 1 CLRMM YIN:L77 Measure the Y system’s output level. V1 CIN: No signal Input a signal to the CIN (only sync Signal to the YIN) and C-2 measure the output level to calculate as follows: CLRBY=100×(V2/V1) Measure the output amplitude V1 at color Control MAX mode and C-1 output amplitude V2 at color control CEN mode and, Calculate as follows: CLRMN=V1/V2 Measure the output amplitude V3 at color Control MIN mode to C-1 calculate as follows: CLRMM=20log (V1/V3) C-1 Measure the output amplitude V4 at color Control 90 mode and output amplitude V5 at color control 38 mode to calculate as follows: CLRSE=100×(V4− V5)/(V2×52) Measure the 8.86MHz component output amplitude at pin 46. Measure the 8.86MHz component output amplitude at pin 47. Measure the 8.86MHz component output amplitude at pin 48. Color:1000000 Color:1111111 Color:1000000 Color:0000000 CLRSE Color:1011010 Color:0100110 E_CAR_B E_CAR_G E_CAR_R C-1 Burst only C-1 Burst only Burst only ACCM1_P 46 46 46 48 C-1 0dB +6dB C-1 -20dB C-1 ACC amplitude characteristics 2 Demodulation output ratio R-Y/B-Y:PAL ACCM2_P RB_P Measure the output amplitude when 0dB is applied to the chroma Color:1000000 inputand when +6dB is applied to the chroma input. And calculate the ratio between them. ACCM1_P=20log(+6dBdata/0dBdata) Measure the output amplitude when –20dB is applied to the Color:1000000 chroma input and calculate the ratio between them. ACCM2_P=20log(-20dBdata/0dBdata) Refer to 5. and measure Bout output amplitude Vb and ROUT output Color:1000000 amplitude Vr. And calculate RB_P=Vr/Vb. Demodulation output ratio G-Y/B-Y:PAL GB_P 46 47 C-4 Measure Bout output amplitude Vbp and GOUT output amplitude Vgbp. And calculate GB_P=Vgbp/Vbp. Color:1000000 Demodulation output ratio G-Y/R-Y:PAL GR_P 47 48 C-5 Measure ROUT output amplitude Vrp and GOUT output amplitude Vgbp. And calculate GR_P=Vgrp/Vrp. Color:1000000 Demodulation angle R-Y/B-Y:PAL ANGRB_P 46 48 C-1 Refer to 5. and measure the B-Y and R-Y demodulation angle and calculate. Color:1000000 Killer operating point 0 (PAL) Killer operating point 3 (PAL) Difference between two Killer operating points (PAL) APC pull-in range(+) KILLP0 KILLP3 DKILLP PULIN+_P 46 46 C-1 C-1 Reduce the input signal until the output Level becomes 75mVp-p Color Killer or less. Measure the input level at that moment. Ope.:00 Reduce the input signal until the output Level becomes 75mVp-p Color Killer or less. Measure the input level at that moment. Ope.:11 Calculate as follows, DKILLP=KILLP0-KILLP3 46 46 C-1 Decrease the chroma fsc frequency from 4.433619MHz+1000Hz and measure the frequency at which the VCO locks. Increase the chroma fsc frequency from 4.433619MHz-1000Hz and measure the frequency at which the VCO locks. APC pull-in range(-) PULIN-_P C-1 No.A1877-21/42 LV766116C Parameter [Chroma block]: NTSC ACC amplitude characteristics 1 ACCM1_N Symbol Test point Input signal C-1 0dB +6dB C-1 -20dB C-1 Test method Bus conditions 46 ACC amplitude characteristics 2 ACCM2_N 46 46 48 Demodulation output ratio R-Y/B-Y:NTSC Demodulation output ratio G-Y/B-Y:NTSC Demodulation angle B-Y/R-Y: NTSC RB_N Measure the output amplitude when 0dB is applied to the chroma input and when +6dB is applied to the chroma input. And calculate the ratio between them. ACCM1_N=20log(+6dBdata/0dBdata) Measure the output amplitude when 20dB is applied to the chroma input and calculate the ratio between them. ACCM2_N=20log(-20dBdata/0dBdata) Refer to 5. And measure Bout output amplitude Vb and ROUT output amplitude Vr. And calculate RB_N=Vr/Vb. Color:1000000 GB_N ANGBR_N 47 46 48 C-1 C-1 Refer to 5. and measure GOUT output amplitude Vg. And calculate GB_N=Vg/Vb. Refer to 5. and measure the B-Y and R-Y demodulation angle and calculate. Reference: B-Y angle Color:1000000 Color:1000000 Demodulation angle G-Y/B-Y: NTSC ANGGB_N 46 47 C-1 Refer to 5. and measure the B-Y and G-Y demodulation angle and calculate. Reference: B-Y angle Color:1000000 Killer operating point 0 (NTSC) Killer operating point 3 (NTSC) Difference between two Killer operating points (NTSC) APC pull-in range(+) KILLN0 KILLN3 DKILLN PULIN+_N 46 46 C-1 C-1 46 46 46 46 46 48 46 C-1 Reduce the input signal until the output Level becomes 75mVp-p or less. Measure the input level at that moment. Reduce the input signal until the output Level becomes 75mVp-p or less. Measure the input level at that moment. Calculate as follows, DKILLN=KILLN0-KILLN3 Decrease the chroma fsc frequency from 3.579545MHz+1000Hz and measure the frequency at which the VCO locks. Increase the chroma fsc frequency from 3.579545MHz-1000Hz and measure the frequency at which the VCO locks. Measure each part of the output level and calculate the B-Y axis angle. Measure each part of the output level and calculate the B-Y axis angle. TINT+ =B-Y axis angle –TINCEN Measure each part of the output level and calculate the B-Y axis angle. TINT- =B-Y axis angle –TINCEN Measure the output amplitude. (B-Y IN:no signal) Measure the output amplitude. (R-Y IN:no signal) Color Killer Ope.:00 Color Killer Ope.:11 APC pull-in range(-) PULIN-_N C-1 Tint center Tint variable range (+) Tint variable range (-) Cr output Amplitude Cb output Amplitude TINCEN TINT+ TINTCBCR-R CBCR-B C-1 C-1 C-1 R-Y IN:C-6 B-Y IN:C-6 TINT:1000000 TINT:1111111 TINT:0000000 CbCr IN: 1 Color Sys:101 Cross B/W: 01 CbCr IN: 1 Color Sys: 101 Cross B/W: 01 [Filter Block]:Chroma BPF Characteristic C-BPF1A Peaker amplitude characteristic 3.93MHz C-BPF1B Peaker amplitude characteristic 4.73/4.13MHz C-BPF1C Peaker amplitude characteristic 4.93/3.93MHz C-BPF2A BandPass amplitude characteristic 3.93MHz C-BPF2B BandPass amplitude characteristic 4.73/4.13MHz C-BPF2C BandPass amplitude characteristic 4.93/3.93MHz CBPF1A 46 C-3 PAL signal Set the chroma frequency (CW) to 4.433619MHz-100kHz and measure C.Filter.Sys:10 V0 output amplitude. And then, set the chroma frequency (CW) to C.BYPASS:0 3.93MHz and measure V1 output amplitude to calculate as follows: CBPF1A=20log(V1/V0) Measure V2 output amplitude when the chroma frequency (CW) is 4.13MHz and V3 output amplitude when it (CW) is 4.73MHz to calculate as follows: CBPF1B =20log(V3/V2) Set the chroma frequency (CW) to 4.93MHz and measure V4 output amplitude to calculate as follows: CBPF1C =20log(V4/V1) Set the chroma frequency (CW) to 4.433619MHz-100MHz and measure V00 output amplitude. And then, set the chroma frequency (CW) to 3.93MHz and measure V10 output amplitude to calculate as follows: CBPF2A=20log(V10/V00) Measure V20 output amplitude when the chroma frequency (CW) is 4.13MHz and V30 output amplitude when it (CW) is 4.73MHz to calculate as follows: CBPF2B =20log(V30/V20) Set the chroma frequency (CW) to 4.93MHz and measure V40 output amplitude to calculate as follows: CBPF2C =20log(V40/V10) C.Filter.Sys:10 C.BYPASS:0 C.Filter.Sys:10 C.BYPASS:0 C.Filter.Sys:11 C.BYPASS:0 CBPF1B 46 C-3 PAL signal C-3 PAL signal C-3 PAL signal CBPF1C 46 CBPF2A 46 CBPF2B 46 C-3 PAL signal C-3 PAL signal C.Filter.Sys:11 C.BYPASS:0 C.Filter.Sys:11 C.BYPASS:0 CBPF2C 46 No.A1877-22/42 LV766116C •Deflection Block Input Signals and Test Conditions Unless otherwise specified，the following conditions apply when each measurement is made. 1. VIF, SIF blocks: No signal 2. C input: No. signal 3. Sync input: A horizontal/vertical composite sync signal PAL: 43IRE, horizontal sync signal (15.625kHz) and vertical sync signal (50kHz) NTSC: 40IRE, horizontal sync signal (15.734264kHz) and vertical sync signal (59.94kHz) Note: No burst signal, chroma signal shall exist below the pedestal level. Signal unsuitable for Y input Signal suitable for Y input Chroma signal Burst signal 4. Bus control conditions: Initial conditions unless otherwise specified． 5. The delay time from the rise of the horizontal output (pin 22 output) to the fall of the FBP IN (pin 23 input) is 7μs. 6. Pin 15 (vertical size correction circuit input terminal) is connected to VCC (5.0V). Parameter [Deflection block] Horizontal free-running frequency Horizontal pull-in range fH Symbol Test point Input signal Test method Bus conditions 22 22 5 YIN: No signal YIN: Horizontal /vertical sync signal PAL YIN: Horizontal /vertical sync signal PAL YIN: Horizontal /vertical sync signal PAL YIN: No signal Connect a frequency counter to the output of pin 22 (H out) and measure the horizontal free-running frequency. Using an oscilloscope, monitor the horizontal sync signal which is input to the Y IN (pin 5) and the pin 22 output (H out) and vary the horizontal signal frequency to measure the pull-in range. Measure the voltage for the pin 22 horizontal output pulse’s low-level period. Measure the voltage for the pin 22 horizontal output pulse’s low-level period. Measure the vertical output period T at pin 17. T × 15.625kHz (PAL) T × 15.734kHz (NTSC) CDMODE:001 (PAL) CDMODE:010 (NTSC) fH PULL Horizontal output pulse length Horizontal output pulse saturation voltage Vertical free-running period 50(PAL) Vertical free-running period 60(NTSC) Hduty 22 V Hsat 22 VFR50 VFR60 17 Vertical ramp output 2.5V T Horizontal output pulse (PAL)(NTSC) HPHCEN (PAL) (NTSC) 22 5 Y IN: Horizontal /vertical sync signal PAL NTSC Measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal. Measuring HPHCEN 20IRE 2.5V Horizontal output No.A1877-23/42 LV766116C Parameter Horizontal position adjustment range Symbol HPHrange Test point Input signal Y IN: Horizontal /vertical sync signal PAL Test method Bus conditions 22 5 With H.PHASE: 0 and 31, measure the delay time from the H.PHASE:00000 rise of the pin 22 horizontal output pulse to the fall of the Y to IN horizontal sync H.PHASE:11111 signal and calculate the difference from H PHCEN. Measuring HPHCEN 20IRE 2.5V Horizontal output Horizontal position adjustment maximum variable width HPHstep 22 5 Y IN: Horizontal /vertical sync signal PAL With H.PHASE: 0 to 31 varied, measure the delay time H.PHASE:00000 from to the rise of the pin 22 horizontal output pulse to the to fall of the Y IN horizontal sync signal and calculate the H.PHASE:11111 variation at each step. Retrieve data for maximum variation. Measuring HPHCEN 20IRE 2.5V Horizontal position adjustment maximum variable width HPHstep 22 5 Y IN: Horizontal /vertical sync signal PAL Horizontal output With H.PHASE: 0 to 31 varied, measure the delay time H.PHASE:00000 from to the rise of the pin 22 horizontal output pulse to the to fall of the Y IN horizontal sync signal and calculate the H.PHASE:11111 variation at each step. Retrieve data for maximum variation. Measuring HPH CEN 20IRE Horizontal blanking left variable range@0 BLKL0 46 5 Y IN: Horizontal /vertical sync signal PAL Horizontal output Measure the time T from the left end of Hsync at pin 5 Y IN to the right end of blanking period at pin 46 BlueOUT with H.BLK.L = 000. H.BLK.L:000 Y IN Hsync T Blue Horizontal blanking left variable range@7 BLKL7 46 5 Y IN: Horizontal /vertical sync signal PAL Measure the time T from the left end of Hsync at pin 5 Y IN H.BLK.L:111 to the right end of blanking period at pin 46 BlueOUT with H.BLK.L = 111. Y IN Hsync T Blue No.A1877-24/42 LV766116C Parameter Horizontal blanking right variable range@0 Symbol BLKR0 Test point Input signal Y IN: Horizontal /vertical sync signal PAL Test method Measure the time T from the left end of Hsync at pin 5 Y IN to the left end of blanking period at pin 46 BlueOUT with H.BLK.R = 000. Bus conditions H.BLK.R:000 46 5 Y IN T Hsync Blue Horizontal blanking right variable range@7 BLKR7 46 5 Y IN: Horizontal /vertical sync signal PAL Measure the time T from the left end of Hsync at pin 5 Y IN to the left end of blanking period at pin 46 BlueOUT with H.BLK.R = 111. H.BLK.R:111 Y IN T Hsync Blue Horizontal output stop voltage Hstop 20 22 Y IN: Horizontal /vertical sync signal Y IN: Horizontal /vertical sync signal Decrease the current from a source connected to pin 20 and measure the pin 20 voltage at which HOUT(PIN22) stops. H Phase BOW@16 HBOW16 22 5 Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW16=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output H Phase BOW@0 HBOW0 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW0=T2-T1 H Phase Bow: 00000 T 20IRE 2.5V Horizontal Out Horizontal output H Phase BOW@31 HBOW31 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW31=T2-T1 H Phase Bow: 11111 T 20IRE 2.5V Horizontal Out Horizontal output No.A1877-25/42 LV766116C Parameter H Phase ANGLE@16 Symbol HANG16 Test point Input signal Y IN: Horizontal /vertical sync signal Test method Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142).Caluculat as follow with each value of T is as T1 and T2. HANG16=T2-T1 Bus conditions 22 5 T 20IRE 2.5V Horizontal Out Horizontal output H Phase ANGLE@0 HANG0 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse to H Phase Angle: the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 00000 167(NTSC:142).Caluculat as follow with each value of T is as T1 and T2. HANG0=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output H Phase ANGLE@31 HANG31 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse to H Phase Angle: the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 11111 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HANG31=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output vertical ramp output amplitude Vsize64 @64 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at line 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows:Vsize64=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 vertical ramp output amplitude @0 Vsize0 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at line VSIZE: 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows: 0000000 Vsize0=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 vertical ramp output amplitude Vsize127 @127 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at line VSIZE: 24 (22: NTSC) and line 310 (262:NTSC). Calculate as follows: 1111111 Vsize127=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 No.A1877-26/42 LV766116C Parameter Symbol Test point Input signal Test method Bus conditions Vertical size correction @0 Vsizecomp 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VCOMP:000 voltage at the line 24 and line 310 with VCOMP = 000. FSCorEHT=1 Calculate as follows: Va=Vline310-Vline24 Apply 4.0V to pin 15 and measure the voltage at the line 24 and line 310 again. Calculate as follows: Va=Vline310-Vline24 Calculate as follows: Vsizecomp=Vb/Va Positive vertical ramp output Line 310 Line 24 Vertical ramp DC voltage @32 Vdc32 Y IN: Monitor the pin 17 vertical ramp output and measure the Horizontal /vertical voltage at line 167(142: NTSC). sync signal PAL Positive vertical ramp output NTSC 17 Line 167 Vertical ramp DC voltage @0 Vdc0 17 Y IN: Monitor the pin 17 vertical ramp output and measure the Horizontal /vertical voltage at line 167(142: NTSC). sync signal Positive vertical ramp output PAL NTSC VDC:000000 Line 167 Vertical ramp DC voltage @63 Vdc63 Y IN: Monitor the pin 17 vertical ramp output and measure the Horizontal /vertical voltage at line 167(142: NTSC). sync signal Positive vertical ramp output PAL NTSC VDC:111111 17 Line 167 Verticalposition @8 Vshift8 17 5 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:1000 Horizontal /vertical IN to the fall of the pin 17. sync signal the beginning of Vsync T V.out(+):17pin Vertical position @0 Vshift0 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:0000 Horizontal /vertical IN to the fall of the pin 17. sync signal 17 5 the beginning of Vsync T V.out(+):17pin Vertical position @15 Vshift15 17 5 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:1111 Horizontal /vertical IN to the Rise of the pin 17. sync signal the beginning of Vsync T V.out(+):17pin No.A1877-27/42 LV766116C Parameter Vertical linearity@16 Symbol Vlin16 Test point Input signal Y IN: Horizontal /vertical sync signal PAL Test method Monitor the pin 17 vertical ramp output and measure the voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin16=(Vb-Va)/(Vc-Vb) Bus conditions 17 Positive vertical ramp output Line 310 Line 167 Line 24 Vertical linearity@0 Vlin0 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VLIN:00000 voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin0=(Vb-Va)/(Vc-Vb) Positive vertical ramp output Line 310 Line 167 Line 24 Vertical linearity@31 Vlin31 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VLIN:11111 voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin31=(Vb-Va)/(Vc-Vb) 17 Positive vertical ramp output Line 310 Line 167 Line 24 Vertical S-shaped correction @16 Vscor16 Y IN: Horizontal /vertical sync signal PA L Monitor the pin 17 vertical ramp output and measure the voltage at line 26, line 70, line 145, line 189, line 264 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor16=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) 17 Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 Vertical S-shaped correction @0 Vscor0 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VSC:10000 voltage at line 26, line 70, line 145, line 189, line 264 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor0=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 Vertical S-shaped correction @31 Vscor31 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VSC:11111 voltage at line 26, line 70, line 145, line 189, line 284 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor31=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 No.A1877-28/42 LV766116C Parameter East/Wst DC oltage @64 EWdc64 Symbol Test point Input signal Horizontal, vertical sync signal Test method Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. Bus conditions 16 East/West output Line 167 East/West DC voltage @0 EWdc0 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. EWDC:000000 East/West output Line 167 East/West DC voltage @127 EWdc127 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. EWDC:111111 East/West output Line 167 Horizontal size compensation @0 Hsizecomp 16 Horizontal, vertical sync signal Monitor the West/East output of pin 16 and measure the voltage (Va) at line 167. Apply 4.0 V to pin 16 and measure again the voltage (Vb) at line 167. Calculate as follows: Hsizecomp=Va-Vb Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp64=Vb-Va HCOMP:000 FSCorEHT=1 East/West parabolic amplitude @64 EWamp64 16 Horizontal, vertical sync signal EWDC :1111111 East/West output Line 167 Line 24 East/West parabolic amplitude @0 EWamp0 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp0=Vb-Va EWAMP:000000 EWDC : 1111111 East/West output Line 167 Line 24 East/West parabolic amplitude @127 EWamp127 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp127=Vb-Va EWAMP:1111111 EWDC : 1111111 East/West output Line 167 Line 24 East/West parabolic tilt @64 EWtilt64 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as follows: Ewtilt64=Va-Vb EWDC : 1111111 EWCORSW: 1 16 East/West output Line 310 Line 24 East/West parabolic tilt @0 EWtilt0 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as follows: Ewtilt0=Va-Vb EWTILT:0000000 EWDC : 1111111 EWCORSW : 1 East/West output Line 310 Line 24 No.A1877-29/42 LV766116C Parameter Symbol East/West parabolic tilt @127 EWtilt127 Test point Input signal Test method Horizontal, Monitor the East/West output (parabolic wave output) of pin 16 and vertical sync measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as signal follows: Ewtilt127=Va-Vb Bus conditions EWTILT:1111111 EWDC : 1111111 EWCORSW : 1 16 East/West output Line 310 Line 24 East/West parabolic corner TOP EWcortop 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 under conditions of CORTOP:11111 (Va) and CORTOP:00000 (Vb). Calculate as follows: Ewcortop=Va-Vb CORTOP: 11111-00000 EWDC : 1111111 EWCORSW : 1 East/West output Line 24 East/West parabolic corner BOTTOM EWcorbot Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 310 under conditions of CORBOT:11111 (Va) and CORBOT:00000 (Vb). Calculate as follows: Ewcorbot=Va-Vb CORBOTTOM: 11111-00000 EWDC:1111111 EWCORSW : 1 16 East/West output Line 310 No.A1877-30/42 LV766116C μ-Controller Chip (LC873664A) Internal 64K-byte ROM (ROM/CGROM), 640-byte RAM And 352x9-bit CRT Display RAM 8-bit Single-chip Microcontroller. 1. Features ■Flash ROM 64K bytes ● 48K-byte program ROM ● 16K-byte character generator ROM ■Internal RAM ● General-purpose RAM: 640 bytes ● CRT display RAM: 352 × 9 bits ● ROM correction RAM: 128 bytes ■Minimum bus cycle time ● 77 ns (13.0 MHz) Note: The bus cycle time here refers to the ROM read speed. ■Minimum instruction cycle time ● 231 ns (13.0MHz) ■OSD ● Screen display: 36 characters × 8 lines ● Display RAM : 352 words (1 word=9 bits) Display area: 36 words × 8 lines Control area: 8 words × 8 lines ● Font types: 16×32 font, 256 types (including 5 fixed fonts) An arbitrary number of characters can be generated as 16×17 or 8×9 font characters. ● Display colors: 512 colors (Analog output) Character text, background, borders, and full background can be displayed. A maximum 16 colors displayable on a line. ● Display mode specifiable on a line basis. OSD mode1, OSD mode 2(Quarter size), OSD mode 3(Simplified graphic), caption/text mode ● Vertical display start line and horizontal display start position specifiable on a line basis. ● Shutter function (specifying the display start or stop line) and scroll functions specifiable on a line basis. ● Horizontal character spacing (9 to 16 dots) (*6) and vertical character spacing (1 to 32 dots) specifiable on a line basis. ● Character size selectable from 10 character sizes on a line basis. (*6) (Horizontal×Vertical) = (1×1), (1×2), (2×2), (2×4), (1.5×1), (1.5×2), (3×2), (3×4), (0.5×0.5), (0.75×0.5) ● Simplified graphic display (One character (16×16 font) can be painted in 4 or 8 colors.) ● The half tone control of the TV picture in the background of the character is possible. ● Built-in the oscillation circuit for display (*6)The supported range varies depending on the active display mode. Refer to the user's guide for details. ■Data slicer function(closed caption format) ● Extracts closed caption data and XDS data. ● NTSC/PAL selectable and line specifiable. ■Ports ● Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 10 (P1n, P3n) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n) *If X’tal oscillator is to be used for time-of-day clock, the number of available Port 0 is 6. Note: Threee of the available ports are internally connected to the companion signal processing IC. ■Timers ● Timer 0: 16-bit timer/counter with a capture register. ● Timer 1: 16-bit timer/counter that supports PWM/toggle outputs ● Base timer ■SIO ● SIO0: 8-bit synchronous serial interface ● SIO1: 8-bit asynchronous/synchronous serial interface (bus mode 1 system) Input and output is possible from the terminal of two systems in bus mode. The two data lines and clock lines can be connected. ■AD converter: 6 bits ×5 channels Note: One channel is connected internally to the signal processing IC. ■PWM: 14-bit PWM×1 channel No.A1877-31/42 LV766116C ■Digital AFT ● It supports 38MHz , 38.9MHz , 39.5MHz and 45.75MHz as the IF frequencies. ■Remote controller receiver circuit (sharing with P03 and INT3 pins) ● Noise rejection function (noise filter time constant selectable from 1 Tcyc,32 Tcyc,and 128Tcyc) ■Watchdog timer ● External RC watchdog timer ● Interrupt and reset signals selectable ■High-speed multiplication/division instructions ● 16 bits×8 bits (Execution time: 5 Tcyc) ● 24 bits×16 bits (Execution time: 12 Tcyc) ● 16 bits÷8 bits (Execution time: 8 Tcyc) ● 24 bits÷16 bits (Execution time: 12 Tcyc) ■Interrupts ● 15 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt Source INT0 INT1 INT2/T0L INT3/base timer T0H T1L/T1H SIO0 SIO1/data slicer vertical sync (VS#)/scan line Port 0 ● Priority levels X > H > L ● If interrupts of the same level, the one with the smallest vector address takes precedence. ■Subroutine stack levels: 320 levels maximum (the stack is allocated in RAM.) ■Oscillation circuits ● RC oscillation circuit (internal): For system clock ● VCO oscillation circuit (internal): For system clock generation and CRT display ● Crystal oscillation circuit: For base timer Note:When the base timer count of clock accuracy is necessary , use the port terminal (two ports) as the crystal oscillation. (See the [12 μ-Controller Chip Crystal Oscillation Circuit and Sample Characteristics] for details.) ■Standby function ● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting HALT mode. (1) Setting the reset pin to lower level. (2) Generation of reset with the watchdog timer. (3) Setting at least one of the INT0 and INT1 pins to the specified level. ● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The VCO and RC oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Generation of reset with the watchdog timer. (3) Setting at least one of the INT0 and INT1 pins to the specified level. (4) Having an interrupt source established at port 0. ■ROM correction function ● Executes the correction program on detection of a match with the program counter value. ● Correction program area size: 128 bytes (4 vector addresses) ■Development tools ● Emulater: TCB87 (Type B or Typ C) (onchip debugger interface board) + ECB873600A (evaluation chip board + LC873600EVA) + POD36-JCT (connecter between evaluation chip board and POD) + POD76600 (POD + LV766xxEVA) No.A1877-32/42 LV766116C 2. μ-Controller Chip System Block Diagram Interrupt control IR PLA Standby control ROM correct Flash ROM RC VCO Reference Clock PLL Clock generator PC SIO0 Bus interface SIO1 Port 0 ACC Port 1 B register Timer 0 C register Timer 1 Port 3 ALU D-AFT Xtal PSW DDS Base timer ADC PWM INT0-INT3 noise filter RAM RAR Data slicer OSD Contro l Circuit Stack pointer CGROM Control VRAM Watchdog timer No.A1877-33/42 LV766116C 3. μ-Controller Chip Pin Function Chart Pin Name CpuGND CpuVDD CpuVDD2 Port 0 P00 to P07 I/O I/O Description - power supply pin ＋ power supply pin ＋ power supply pin ・8-bit I/O port ・I/O specifiable in 4 bit units ・Pull-up resistors can be turned on and off in 4 bit units. ・HOLD reset input ・Port 0 interrupt input ・Pin functions P00: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/ SIO0 data output P01: INT1 input/HOLD reset input/timer 0H capture input/SIO0 data input/bus I/O P02: SIO0 clock I/O P03: INT3 input (with noise filter input)/timer 0 event input/ timer 0H capture input P04: AD conversion input terminal (AN4) P05: AD conversion input terminal (AN5) P06: AD conversion input terminal (AN6)/Output terminal for 32.768kHz crystal oscillation (XT2) P07: AD conversion input terminal (AN7)/Input terminal for 32.768kHz crystal oscillation (XT1) Interrupt acknowledge type Option No No No P00-P03: No P04-P07: Yes Port 1 P11 to P17 I/O Port 3 P30 to P32 I/O Rising & H Level Falling INT0 ○ ○ × ○ INT1 ○ ○ × ○ INT3 ○ ○ ○ × The two terminal of P00, P01, P04 and P05 can be used as LED driver. ・7-bit I/O port ・I/O specifiable in 1 bit units ・Pull-up resistors can be turned on and off in 1 bit units. ・Pin functions P13: TVPWMD output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: SIO1 data input / bus I/O / data output P17: SIO1 clock I/O /T1PWML output ・3-bit I/O port (Internal connected terminal) ・I/O specifiable in 1 bit units ・ Pin functions P30,P31: Internal communication interface terminal: P32 : INT2 input / timer 0 event input/ timer 0L capture input Interrupt acknowledge type Rising Falling Rising & Falling ○ H Level Rising Falling L Level ○ ○ × Yes No L Level INT2 RES# FILT VDDi1 VDDi2 RESi# XTIN CVIN PEOUT VS# HS# R G B BL1 BL2 DDSOUT DDSYS DDSIN DAFTIN Input Output Input Input Input Output Input Input Output Output Output Output Output Output Input Input Input ○ ○ × × No No No No No No No No No No No No No No No No No No No Reset pin Internal PLL filter pin for system clock ＋ power supply pin (Internal connected terminal) ＋ power supply pin (Internal connected terminal) Reset pin (Internal connected terminal) Reference clock input (Internal connected terminal) Video input pin (Internal connected terminal) Pedestal level output (Internal connected terminal) Vertical sync input pin (Internal connected terminal) Horizontal sync input pin (Internal connected terminal) Red (R) RGB video output pin (Internal connected terminal) Green (G) RGB video output pin (Internal connected terminal) Blue (B) RGB video output pin (Internal connected terminal) Fast blanking 1 control output pin (Internal connected terminal) Fast blanking 2 control output pin (Internal connected terminal) DDS color sub-carrier output pin (Internal connected terminal) DDS color system selection pin (Internal connected terminal) DDS clock input pin (Internal connected terminal) IF carrier input pin (Internal connected terminal) No.A1877-34/42 LV766116C 4. μ-Controller Chip Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port name P00 to P03 P04 to P07 P11 to P17 P30 to P31 P32 Option selected in units of 1 bit 1 bit Option type No 1 2 1 2 No No Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain Nch-open drain Output type No Programmable (*8) No Programmable Programmable Yes No Pull-up resistor (*8) Programmable pull-up resistors for port 0 are controlled in 4 bit units (P04 to P07). *Connect the IC as shown below to minimize the noise input to the CpuVDD pin. LSI CpuVDD Power supply CpuVDD2 1μF CpuGND 5. μ-Controller Chip Electrical characteristics／Ta=-10deg to +65deg, VSS=0V Parameter High level input current Symbol IIH(1) Pins Ports0,1 Conditions ･Output disable ･Pull-up MOS Tr.OFF ･VIN=VDD (including the off-leak current of the output Tr.) VIN=VDD ･Output disable ･Pull-up MOS Tr.OFF ･VIN=VSS (including the off-leak current of the output Tr.) VIN=VSS IOH=-1.0mA IOL=10mA IOL=1.6mA IOL=8.0mA VOH=0.9VDD VDD[V] 4.5~5.5 min typ Limits max 1 unit µA IIH(2) Low level input current IIL(1) RES# Ports0,1 4.5~5.5 4.5~5.5 -1 1 IIL(2) High level output voltage Low level output voltage VOH VOL(1) VOL(2) Pull-up MOS Tr. Resistance Rpu Bus terminal short circuit resistance RBS for internal communication Hysteresis voltage VHIS RES# Ports04-07, Ports1 Ports02,03 Ports06,07 Ports1 Ports00,01, Ports04,05 Ports04-07,1 ･P14-P30 ･P15-P31 ･P14-P16 ･P15-P17 Ports00-03,1 ･RES# 4.5~5.5 4.5~5.5 4.5~5.5 4.5~5.5 4.5~5.5 4.5~5.5 4.5~5.5 -1 VDD-1 1.5 0.4 0.4 15 40 130 70 300 kΩ Ω V 4.5~5.5 0.35 V . No.A1877-35/42 LV766116C 6. μ-Controller Chip SIO0 Characteristics(*9) ／Ta=-10deg to +65deg, VSS=0V Parameter Cycle Low level pulse-width High level Pulse-width Input Clock Serial Clock Serial Input Serial Outpu Serial Clock Serial Input Serial Output Output Clock Input Clock Output Clock Parameter Cycle Low level pulse-width High level pulse-width Cycle Output Clock Low level pulse-width High level pulse-width Input Clock Symbol tSCK(3) tSCKL(3) tSCKH(3) Pins SCK1(P15) Conditions See the figure 4. VDD[V] 4.5-5.5 min 2 1 1 typ tSCK(4) tSCKL(4) tSCKH(4) SCK1(P15) ･At the CMOS output selection ･See the figure 4. 4.5~5.5 2 1/2 1/2 tSCK Data setup time tsDI(2) SI1(P14) SB1(P14) ･Define for rising of SIOCLK. ･See the figure 4. 4.5~5.5 0.03 thDI(2) Data hold time 0.03 Output delay time tdDO(4) SO1(P16) SB1(P14) ･Define for falling of SIOCLK. ･Define as time until output change start in open drain output. ･See the figure 4. 4.5~5.5 Symbol tSCK(1) tSCKL(1) tSCKH(1) tSCKHA(1a) ･Continuous data transmitting and receiving mode ･See the figure 4. (*10) ･At the CMOS output selection ･See the figure 4. ･At the CMOS output ･Continuous data transmitting and receiving mode ･See the figure 4. ･Define for rising of SIOCLK. ･See the figure 4. Pins SCK0(P02) Conditions See the figure 4. Limits VDD[V] 4.5~5.5 min 2 1 1 4 typ max unit tCYC Cycle Low level pulse-width Low level pulse-width tSCK(2) tSCKL(2) tSCKH(2) tSCKHA(2a) SCK0(P02) 4.5~5.5 4/3 1/2 1/2 tSCKH(2) + 2tCYC tSCKH(2)+ (10/3)tCYC tCYC tSCK tsDI(1) Data setup time thDI(1) Data hold time Output delay time tdDO(1) SI0(P01) SB0(P01) 4.5~5.5 0.03 μs 0.03 SO0(P00) SB0(P01) tdDO(2) ･Continuous data transmitting and receiving mode (*11) ･Synchronous 8-bit mode (*11) (*11） 4.5~5.5 (1/3)tCYC +0.05 1tCYC +0.05 (1/3)tCYC +0.05 tdDO(3) (*9) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation. (*10) When using the serial clock input with continuous data transmitting and receiving mode, lengthen time from the set of the cereal clock of SI0RUN in the state of "H" to the falling of the first cereal clock when it begins to send and receive continuous data more than tSCKHA. (*11) This is defined for falling of SIOCLK and it is defined as time until output change start in open drain output. (See the figure 4) 7. μ-Controller Chip SIO1 Characteristics (*11) / Ta=-10deg to +65deg, VSS=0V Limits max unit tCYC μs (1/3)tCYC +0.05 (*12) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation. No.A1877-36/42 LV766116C 8. μ-Controller Chip Pulse input conditions / Ta=-10deg to +65deg, VSS=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pins INT0,INT1,INT2 Conditions ･Interrupt acceptable ･Timer0, 1 event input enabled ･Interrupt acceptable ･Timer0, 1 event input enabled ･Interrupt acceptable ･Timer0, 1 event input enabled ･Interrupt acceptable ･Timer0, 1 event input enabled Reset acceptable VDD[V] 4.5~5.5 min 1 typ Limits max unit tCYC INT3/P03 (1/1 is selected for noise rejection clock.) INT3/P03 (1/32 is selected for noise rejection clock.) INT3/P03 (1/128 is selected for noise rejection clock.) RES# 4.5~5.5 2 4.5~5.5 64 4.5~5.5 256 4.5~5.5 200 µs 9. μ-Controller Chip AD converter characteristics / Ta=-10deg to +65deg, VSS=0V Parameter Resolution Absolute precision Conversion time Symbol N ET tCAD Pins AN3, AN4~AN7 (P04-P07) Conditions (*13) Until result of conversion is ensured after Vref selection 1 bit conversion time = 3 × Tcyc VSS VAIN=VDD VAIN=VSS -1 VDD[V] 4.5~5.5 min typ 6 Limits max ±1 0.636 unit bit LSB µs Analog input voltage range Analog port input current VAIN IAINH IAINL VDD 1 V µA (*13) Absolute precision does not include quantizing error (1/2LSB). No.A1877-37/42 LV766116C 10. μ-Controller Chip Sample current dissipation characteristics / Ta=-10deg to +65deg, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored Parameter Current dissipation during basic operation (*14) (*15) Symbol IDDOP(1) Pins CpuVDD Conditions ·Reference clock=4.43MHz crystal oscillation （Operating mode: BipChip） System clock: VCO (13.0MHz) ·VCO for OSD operating ·Built-in RC oscillation stops ·At the 1/1 frequency dividing ·OSD, DSL enabled ·Reference clock=4.43MHz crystal oscillation （Stanby mode: BipChip） ·System clock: reference clock frequency dividing (32kHz) ·VCO for the main clock and for OSD stops ·Built-in RC oscillation stops ·At the 1/2 frequency dividing VDD[V] 4.5~5.5 min Limits typ max 31 42 unit mA IDDOP(2) CpuVDD 4.5~5.5 2 2.7 mA Current dissipation in HALT mode (*14) (*15) IDDHALT(1) CpuVDD IDDHALT(2) CpuVDD IDDHALT(3) CpuVDD Current dissipation in HOLD mode (*15) IDDHOLD CpuVDD ·HALT mode ·Reference clock=4.43MHz crystal oscillation （Stanby mode: BipChip） ·System clock: VCO (13.0MHz) ·VCO for OSD stops ·Built-in RC oscillation stops ·OSD, DSL enabled ·HALT mode ·Reference clock=4.43MHz crystal oscillation （Stanby mode: BipChip） ·System clock: Built-in RC oscillation ·VCO for the main clock and for OSD stops ·At the 1/1 frequency dividing ·HALT mode ·Reference clock=4.43MHz crystal oscillation （Stanby mode: BipChip） ·System clock: reference clock frequency dividing (32kHz) ·VCO for the main clock and for OSD stops ·Built-in RC oscillation stops ·At the 1/2 frequency dividing ·HOLD mode ·All oscillation stop ·Reference clock=4.43MHz crystal oscillation （Stanby mode:BipChip） 4.5~5.5 5 8 mA 4.5~5.5 1.7 3.2 mA 4.5~5.5 1.3 2 mA 4.5~5.5 1.2 1.9 mA (*14) The currents of the output transistors and the internal pull-up MOS transistors are ignored. (*15) 4.43MHz crystal oscillation current is contained. No.A1877-38/42 LV766116C 11. μ-Controller Chip Ｃcrystal Oscillation Circuit and Sample Characteristics／Ta=-10deg to +65deg, VSS=0V When the base timer count of clock accuracy is necessary , LC873664A can use the port terminal (P06,P07) as the crystal oscillation (See the Figure 1). The sample oscillation circuit characteristics and recommended oscillation circuit when port terminal (P06, P07) is used as XTAL oscillation terminal are shown below. The sample oscillation circuit characteristics in the table below is based on the following conditions: • Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. • Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended circuit parameters C1 32.768kHz Epson TOYOCOM MC-306 18pF C2 18pF Rf OPEN Rd 390kΩ 4.5~5.5V Operating supply voltage range TmsXtal (*16) Oscillation stabilizing time Typ 1.0S max 1.5S Applicable CL value = 12.5pF SMD-type Frequency Manufacturer Oscillator Notes (*16) The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see the Figure 3). The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. ・Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. ・The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10deg to +65deg. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer ・When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ･ The distance between the clock I/O terminal (P07/XT1 terminal P06/XT2 terminal) and external parts should be as short as possible. ･ The capacitors’ VSS should be allocated close to the microcontroller’s CpuGND terminal and be away from other GND. ･ The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 (P07) Rf XT2 (P06) Rd C1 X’tal C2 Figure 1 Recommended oscillation circuit. 0.5VDD Figure 2 The Point of AC timing measure. No.A1877-39/42 LV766116C CpuVDD Power supply Reset time TPIL(5) RES# 0V Built-in RC oscillation tmsVCO VCO1 tmsXtal XT1,XT2 XTAL Oscillation enable signal Indifinite Reset Instruction execution Reset time and oscillation stable time Invalid the HOLD release signal Valid the HOLD release signal Built-in RC oscillation tmsVCO VCO1 tmsXtal XT1,XT2 XTAL oscillation enable signal Status HOLD HALT Ｈ(Enable state) HOLD release signal and oscillation stable time Figure 3 Oscillation stable time. No.A1877-40/42 LV766116C SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission time (SIO0 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Data RAM transmission time ( ) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 4 Serial I/O wave. tPIL tPIH Figure 5 Pulse input timing wave. 100Ω FILT + - 1MΩ 2.2μF 33000pF Figure 6 FILT recommended circuit. (Note) Place FILT parts on board as close to the microcontroller as possible. No.A1877-41/42 LV766116C CpuVDD2 + 1μF Figure 7 CpuVDD2 recommended circuit. (Note) Place CpuVDD2 parts on board as close to the microcontroller as possible. * Refer to the user’s manual of LC873600 series,when you know the details about μ-Controller. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice. PS No.A1877-42/42