LV8112V

Ordering number : ENA1645 Bi-CMOS IC LV8112V Overview For Polygon Mirror Motor 3-phase Brushless Motor Driver The LV8112V is a 3-phase brushless motor driver for polygon mirror motor driving of LBP. A circuit needed to drive of polygon mirror motor can be composed of a single-chip. Also, the output transistor is made DMOS by using BiDC process, and by adopting the synchronous rectification method, the lower power consumption (Heat generation) is achieved. Features • 3-phase bipolar drive • Direct PWM drive + synchronous rectification • IO max1 = 2.5A • IO max1 = 3.0A (t ≤ 0.1ms) • Output current control circuit • PLL speed control circuit • Phase lock detection output (with mask function) • Compatible with Hall FG • Provides a 5V regulator output Specifications Parameter Supply voltage • Full complement of on-chip protection circuits, including lock protection, current limiter, under-voltage protection, and thermal shutdown protection circuits • Circuit to switch slowing down method while stopped (Free run or Short-circuit brake) • Constraint protection detection signal switching circuit (FG or LD) • Forward / Reverse switching circuit • Hall bias pin (Bias current cut in a stopped state) • SDCC (Speed Detection Current Control) function Maximum Ratings at Ta = 25°C Symbol VCC max VG max Output current IO max1 IO max2 Allowable Power dissipation Operation temperature Storage temperature Junction temperature Pd max Topr Tstg Tj max VCC pin VG pin *1 t ≤ 0.1ms *1 Mounted on a specified board *2 Conditions Ratings 37 42 2.5 3.0 1.7 -25 to +80 -55 to +150 150 Unit V V A A W °C °C °C *1. Tj max = 150°C must not be exceeded. *2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 11310 SY 20091224-S00004 No.A1645-1/13 LV8112V Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage range 5V constant voltage output current LD pin applied voltage LD pin output current FG pin applied voltage FG pin output current HB pin applied voltage HB pin output current Symbol VCC IREG VLD ILD VFG IFG VHB IHB Conditions Ratings 10 to 35 0 to -30 0 to 5 0 to 15 0 to 5 0 to 15 0 to 5 0 to -30 Unit V mA V mA V mA V mA Electrical Characteristics at Ta = 25°C, VCC = 24V Parameter Current drain Symbol ICC1 ICC2 5V Constant Voltage Output Output voltage Line regulation Load regulation Temperature coefficient Output Block Output ON resistance Output leakage current Lower side Diode forward voltage Upper side Diode forward voltage Charge Pump Output (VG pin) Output voltage CP1 pin Output ON resistance (High level) Output ON resistance (Low level) Hall Amplifier Block Input bias current Common mode input voltage range Hall input sensitivity Hysteresis Input voltage L → H Input voltage H → L Hall Bias (HB pin) P-channel Output Output voltage ON resistance Output leakage current FG Amplifier Schmitt Block (IN1) Input amplifier gain Input hysteresis (H → L) Input hysteresis (L → H) hysteresis FGFIL pin High level output voltage Low level output voltage External capacitor charge current External capacitor discharge current Amplitude VOH(FGFIL) VOL(FGFIL) ICHG1 ICHG2 V(FGFIL) VCHG1 = 1.5V VCHG2 = 1.5V 2.7 0.75 -5 3 1.95 3.0 0.85 -4 4 2.15 3.3 0.95 -3 5 2.35 V V μA μA Vp-p GFG VSHL(FGS) VSLH(FGS) VFGL Design target value * Input referred, Design target value * Input referred, Design target value * Input referred, Design target value * 5 0 10 10 times mV mV mV VOL(HB) IL(HB) IHB = -20mA VO = 0V 20 30 10 Ω μA ΔVIN(HA) VSLH VSHL IHB(HA) VICM -2 0.5 80 15 24 12 -12 42 -0.5 VREG-2.0 μA V mVp-p mV mV mV VOH(CP1) VOL(CP1) ICP1 = -2mA ICP1 = 2mA 500 300 700 400 Ω Ω VGOUT VCC+4.9 V RON IOleak VD1 VD2 IO = 1A , Sum of the lower and upper side outputs Design target value * ID = -1A ID = 1A 1.0 1.0 10 1.35 1.35 μA V V 1.5 1.9 Ω VREG ΔVREG1 ΔVREG2 ΔVREG3 VCC = 10 to 35V IO = -5 to -20mA Design target value * 4.65 5.0 20 25 0 5.35 100 60 V mV mV mV/°C In a stop state Conditions min Ratings typ 5.5 1.0 max 6.5 1.5 mA mA Unit * Design target value, Do not measurement. Continued on next page. No.A1645-2/13 LV8112V Continued from preceding page. Parameter FG Output Output ON resistance Output leakage current PWM Oscillator High level output voltage Low level output voltage External capacitor charge current Oscillation frequency Amplitude Recommended operation frequency range CSD Oscillation Circuit High level output voltage Low level output voltage Amplitude External capacitor charge current External Capacitor Discharge Current Oscillation frequency Phase comparing output Output ON resistance (high level) Output ON resistance (low level) Phase Lock Detection Output Output ON resistance Output leakage current Error Amplifier Block Input offset voltage Input bias current High level output voltage Low level output voltage DC bias level Current Control Circuit Drive gain GDF While phase locked 0.5 0.55 0.6 times VIO(ER) IB(ER) VOH(ER) VOL(ER) VB(ER) IOH = -100μA IOL = 100μA Design target value * -10 -1 EI+0.7 EI-1.75 -5% EI+0.85 EI-1.6 VREG/2 +10 +1 EI+1.0 EI-1.45 5% mV μA V V V VOL(LD) IL(LD) ILD = 10mA VO = 5V 20 30 10 Ω μA VPDH VPDL IOH = -100μA IOL = 100μA 500 500 700 700 Ω Ω VOH(CSD) VOL(CSD) V(CSD) ICHG1(CSD) VCHG1 = 2.0V ICHG2(CSD) VCHG2 = 2.0V f(CSD) C = 0.068μF, Design target value * 2.7 0.8 1.75 -14 8 30 3.0 1.0 2.0 -10 11 40 3.3 1.2 2.25 -6 14 50 V V Vp-p μA μA Hz VOH(PWM) VOL(PWM) ICHG(PWM) f(PWM) V(PWM) fOPR VPWM = 2V C = 150pF 2.95 1.3 -90 180 1.5 15 3.2 1.5 -70 225 1.7 3.45 1.7 -50 270 1.9 300 V V μA kHz Vp-p kHz VOL(FG) IL(FG) IFG = 7mA VO = 5V 20 30 10 Ω μA Symbol Conditions min Ratings typ max Unit Current Limiter Circuit (pins RF and RFS) Limiter voltage Under-voltage Protection Operation voltage Hyteresis CLD Circuit External capacitor charge current Operation voltage Thermal Shutdown Operation Thermal shutdown operation temperature Hysteresis CLK pin External input frequency High level input voltage Low level input voltage Input open voltage Hysteresis High level input current Low level input current fI(CLK) VIH(CLK) VIL(CLK) VIO(CLK) VIS(CLK) IIH(CLK) IIL(CLK) VCLK = VREG VCLK = 0V 0.1 2.0 0 VREG-0.5 0.2 -10 -110 0.3 0 -85 10 VREG 1.0 VREG 0.4 +10 -60 kHz V V V V μA μA ΔTSD Design target value (Junction temperature) 30 °C TSD Design target value (Junction temperature) 150 175 °C. ICLD VH(CLD) VCLD = 0V -4.5 3.25 -3.0 3.5 -1.5 3.75 μA V VSD ΔVSD 8.3 0.2 8.7 0.35 9.1 0.5 V V VRF 0.465 0.515 0.565 V * Design target value, Do not measurement. Continued on next page. No.A1645-3/13 LV8112V Continued from preceding page. Parameter CSDSEL pin High level input voltage Low level input voltage Input open voltage High level input current Low level input current S/S pin High level input voltage Low level input voltage Input open voltage Hysteresis High level input current Low level input current BRSEL pin High level input voltage Low level input voltge Input open voltage High level input current Low level input current F/R pin High level input voltage Low level input voltage Input open voltage High level input current Low level input current VIH(FR) VIL(FR) VIO(FR) IIH(FR) IIL(FR) VF/R = VREG VF/R = 0V 2.0 0 VREG-0.5 -10 -110 0 -85 VREG 1.0 VREG +10 -60 V V V μA μA VIH(BRSEL) VIL(BRSEL) VIO(BRSEL) IIH(BRSEL) IIL(BRSEL) VBRSEL = VREG VBRSEL = 0V 2.0 0 VREG-0.5 -10 -110 0 -85 VREG 1.0 VREG +10 -60 V V V μA μA VIH(SS) VIL(SS) VIO(SS) VIS(SS) IIH(SS) IIL(SS) VS/S = VREG VS/S =0V 2.0 0 VREG-0.5 0.2 -10 -110 0.3 0 -85 VREG 1.0 VREG 0.4 +10 -60 V V V V μA μA VIH(CSD) VIL(CSD) VIO(CSD) IIH(CSD) IIL(CSD) VCSD = VREG VCSD = 0V 2.0 0 VREG-0.5 -10 -110 0 -85 VREG 1.0 VREG +10 -60 V V V μA μA Symbol Conditions min Ratings typ max Unit No.A1645-4/13 LV8112V Package Dimensions unit : mm (typ) 3333 TOP VIEW 15.0 44 23 SIDE VIEW BOTTOM VIEW (4.7) 5.6 7.6 (3.5) 1 (0.68) 0.65 0.22 22 0.2 1.7MAX SIDE VIEW 0.1 (1.5) 0.5 SANYO : SSOP44K(275mil) 2.0 Pd max -- Ta Allowable power dissipation, Pd max -- W 1.7 1.5 1.0 0.95 0.5 0 -25 0 25 50 75 80 100 Ambient temperature, Ta -- C Pin Assignment GND2 VCC1 VCC2 OUT1 OUT2 OUT3 IN3+ IN2+ IN1+ 24 23 21 22 Top view 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SUB RFS CP2 CP1 VG RF 28 27 26 25 LV8112V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BRSEL CSDSEL FGFIL FC PH PD PWM GND EI EO VREG CSD TOC S/S CLK F/R CLD HB FG LD No.A1645-5/13 LV8112V Block Diagram and Application Circuit Example PWM CSDSEL CSDSEL PD CSD CSD OSC COUNT LOGIC PWM OSC VREG EI BRSEL BRSEL LOGIC EO S/S TOC S/S CONT AMP COMP F/R F/R TSD LD output LD LD CLD LD MASK PLL FC PEAK HOLD PH VREG VREG LVDS VCC VCC1 VCC2 CLK input FG output CLK FG CLK FG CNTROL CIRCUIT CHARGE PUMP VG CP1 CP2 FGFIL FILTER OUT1 DRIVER OUT2 HALL HYS AMP HB CURR LIM OUT3 SUB IN1+ IN1− IN2+ IN2− IN3+ IN3− HB RFS RF GND GND2 No.A1645-6/13 LV8112V Pin Function Pin No. 1 Pin name CLK Function Clock input pin (10kHz maximum) Equivalent circuit VREG 55kΩ 5kΩ 10kΩ 1 2 LD Phase lock detection output pin. Goes ON during PLL-phase lock. Open drain output. VREG 2 3 S/S Start/Stop input pin. START with a low-level input. STOP with a high-level input or open input 5kΩ 55kΩ 10kΩ VREG 3 4 VREG 5V regulator output pin. (the control circuit power supply) Connect a capacitor between this pin and GND for stabilization. VCC 50Ω 4 5 BRSEL Brake selection pin. By low level, short-circuit braking when the S/S pin is in a stopped state. (Brake for the inspection process) VREG 55kΩ 5kΩ 5 6 CSDSEL Motor constraint protection detection signal selection pin. Select FG with low, and LD with high or in an open state. VREG 55kΩ 5kΩ 6 Continued on next page. No.A1645-7/13 LV8112V Continued from preceding page. Pin No. 7 Pin name F/R Function Pin to select Forward / Reverse. (Pin to select SDCC function) VREG Equivalent circuit 55kΩ 5kΩ 7 8 CLD Pin to set phase lock signal mask time. Connect a capacitor between this pin and GND. If there is no need for masking, this pin must be left open. VREG 500Ω 2kΩ 8 9 CSD Pin for both the constraint protection circuit operation time and the initial reset pulse setting. Connect a capacitor between this pin and GND. If the motor constraint protection circuit is not used, a capacitor and a resistor must be connected in parallel between the CSD pin and GND. VREG 500Ω 9 10 FG FG Schmitt output pin. Open drain output. VREG 10 12 PWM Pin to set the oscillation frequency of PWM. Connect a capacitor between this pin and GND. VREG 200Ω 2kΩ 12 14 FC Frequency characteristics correction pin of the current limiter circuit. Connect a capacitor between this pin and GND. VREG 500Ω 14 110kΩ Continued on next page. No.A1645-8/13 LV8112V Continued from preceding page. Pin No. 15 Pin name FGFIL FG filter pin. When the noise of the FG signal is a problem, connect a capacitor between this pin and GND for stabilization. Function VREG Equivalent circuit 15 16 PH Pin to stabilize the RF waveform. Connect a capacitor between this pin and GND. VREG 500Ω 16 10kΩ 17 PD Phase comparison output pin. The phase error is output by the duty changing of the pulse. VREG 500Ω 17 18 EI Error amplifier input pin. VREG 500Ω 18 19 EO Error amplifier output pin. VREG 19 100kΩ 20 TOC Torque command voltage input pin. Normally, this pin must be connected with the EO pin. VREG 20 21 GND Ground pin of the control circuit block. Continued on next page. No.A1645-9/13 LV8112V Continued from preceding page. Pin No. 22 Pin name HB Function Hall element bias current pin. Goes ON when the S/S pin is in a start state. Goes OFF when the S/S pin is in an stopped state. VREG Equivalent circuit 22 23 24 25 26 27 28 IN1+ IN1− IN2+ IN2− IN3+ IN3− Hall amplifier input pin. A high level state of logic is recognized when IN+ > IN−. In reverse case is a low-level state. The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. VREG 24 26 28 500Ω 500Ω 23 25 27 29 30 32 34 36 SUB GND2 OUT3 OUT2 OUT1 Frame ground pin. This pin is connected with the GND2 pin. Ground pin of the output circuit block. Output pin. As for PWM, Duty control is executed on the upper- side FET. VCC 32 34 36 38 RF Source pin of output MOSFET (lower-side). Connect a low resistance (Rf) between this pin and GND. 38 VREG 39 RFS Output current detection pin. Connect to RF pin. 39 5kΩ 40 VCC2 Power supply pin. Connect a capacitor between this pin and GND for stabilization. 41 42 VCC1 VG Power supply pin for control. Charge pump output pin (Power supply for the upper side FET gate). Connect a capacitor between this pin and VCC. 500Ω 100Ω VCC 44 43 44 CP1 CP2 Pin to connect a capacitor for charge pump. Connect a capacitor between CP1 and CP2. 42 43 No.A1645-10/13 LV8112V 3-phase Logic Truth Table F/R = H IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H (IN = “H” indicates the state where in IN+ > IN−) F/R = L IN2 H H L L L H IN3 L H H H L L OUT1 L L M H H M Output OUT2 H M L L M H OUT3 M H H M L L S/S Pin Input state High or Open Low Mode Stop Start BRSEL Pin Input state High or Open Low While stopped Free run Short-circuit brake CSDSEL Pin Input state High or Open Low Mode LD standard FG standard SDCC Select Input state F/R = High or Open F/R = Low Mode Function ON Function OFF LV8112V Description 1. Speed Control Circuit This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method. This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency. fFG (Servo) = fCLK 2. Output Drive Circuit This IC adopts the direct PWM drive method to reduce power loss in the output. The output transistor is always saturated while the transistor is on and adjusts the driving force of the motor by changing the duty that the output transistor is on. The PWM switching of the output is performed by the upper-side output transistor. Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off. But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification. 3. Current Limiter Circuit This IC limits the (peak) current at the value I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister)). The current limitation operation consists of reducing the PWM output on duty to suppress the current. To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this delay. It is necessary to set the current increases by the delay. 4. Power Saving Circuit This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state. 5. Reference Clock Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis. But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs. If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of motor if the motor constrained protection circuit does operate. (Clock disconnection protection) No.A1645-11/13 LV8112V 6. PWM Frequency The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin. fPWM ≈ 1 / (29500 × C ) … 150pF or more fPWM ≈ 1 / (32000 × C ) … 100pF or more, less than 150pF The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected. The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce influence of the output. 7. Hall Effect Sensor Input Signals The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs. Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise. If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting capacitors across the inputs. 8. FG Signals The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be excluded by inserting a capacitor between the FGFIL pin and GND. Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of noise occurs easily when the position of GND of a capacitor is incorrect. 9. Constraint Protection Circuit This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin. The set time (in seconds) is 102 × C (μF) When a capacitor of 0.068μF is attached, the protection time becomes about 7.0 seconds. The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be controlled. Therefore, if the motor constraint protection circuit is not used, a resistor of about 220kΩ and a capacitor of about 4700pF must be connected in parallel between the CSD pin and GND. 10. Phase Lock Signals (1) Phase lock range This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the characteristics of the IC. ( because the accelerations of the change in FG frequency influences.) When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock. (2) Phase lock signal mask functions When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the capacitance of the capacitor attached between the CLD pin and GND. The mask time (seconds) is 1.8 × C (μF) When a capacitor of 0.1μF is attached, the mask time becomes about 180ms. If the signals should be masked completely, the mask time must be set well in advance. When there is no need for masking, the CLD pin must be left open. No.A1645-12/13 LV8112V 11. Power Supply Stabilization Since this IC is used in applications that draw large output currents and adopts the drive method by switching, the power-Supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between the VCC pin and GND. The ground-side a capacitor must be connected as close to the GND2 pin of power GND as possible. If it is impossible to connect a capacitor (electrolytic capacitor) near the pin, the ceramic capacitor of about 0.1μF must be connected as close to the pin as possible. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection, Since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required. 12. VREG Stabilization To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1μF or more. GND of the capacitor must be attached as close to the control block GND (GND1 pin) of the IC as possible. 13. Error Amplifier External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of noise. Also, these components must be placed as separate from the motor as possible. 14. IC Reverse Metal To improve heat radiation, the metal part on the reverse of IC is stuck fast to the substrate by using highly-conduction solder. 15. SDCC (Speed Detection Current Control) function The SDCC circuit controls the speed detection current. It limits the current to 87.5% of the specified current to reduce acceleration of the motor when the rotation of the motor exceeds 95% of its target speed. This enables stabilized phase lock pull-in and minimizes the variation in startup time. The SDCC function is disabled by setting F/R low. It is enabled by setting F/R high or open. Notes: If the selected state of SDCC does not match the rotational direction of the motor, it is necessary to solve the problem by changing the HALL bias. SANYO SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This This catalog provides information as of February, 2010. Specifications and information herein are subject information as of January, 2009. Specifications and information t o change without notice. PS No.A1645-13/13