LV8138V

Ordering number : ENA2013 Bi-CMOS IC LV8138V Overview For Brushless Motor Drive Sine wave PWM Drive, Pre driver IC The LV8138V is a PWM system pre driver IC designed for three-phase brushless motors. This IC reduces motor driving noise by using a high-efficiency, sine wave PWM drive type. It incorporates a full complement of protection circuits and, by combining it with a hybrid IC in the STK611 or STK5C4 series, the number of components used can be reduced and a high level of reliability can be achieved. Furthermore, its power-saving mode enables the power consumption in the standby mode to be reduced to zero. This IC is optimally suited for driving various large-size motors such as those used in air conditioners and hot-water heaters. Features • Three-phase bipolar drive • Sine wave PWM drive • Drive phase setting function (Set 0-58 degrees 32 steps: There is an adjustment function corresponding to the CTL pin input) • Supports power saving mode(power saving mode at CTL pin voltage of 1.0V (typ) or less; ICC = 0mA, HB pin turned off) • Supports bootstrap • Automatic recovery type constraint protection circuit • Forward/reverse switching circuit, Hall bias pin • Current limiter circuit, low-voltage protection circuit, and thermal shutdown protection circuit • FG1 and FG3 output (360-degree electrical angle/1 pulse and 3 pulses) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. 22912 SY 20120119-S00004 No.A2013-1/19 LV8138V Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Allowable power dissipation Symbol VCC max IO max Pd max1 Pd max2 CTL pin applied voltage FG1,FG3 pin applied voltage Junction temperature Operating temperature Storage temperature VCTL max VFG1 max VFG3 max Tj max Topr Tstg Independent IC Mounted on a specified circuit board.* VCC pin Conditions Ratings 18 15 0.45 1.05 18 18 150 -40 to +105 -55 to +150 Unit V mA W W V V °C °C °C * Specified circuit board : 114.3mm × 76.1mm × 1.6mm, glass epoxy Note 1) Absolute maximum ratings represent the values that cannot be exceeded for any length of time. Note 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for further details. Allowable Operating range at Ta = 25°C Parameter Supply voltage range 5V constant voltage output current HB pin output current FG1,FG3 pin output current Symbol VCC IREG IHB IFG1, IFG3 Conditions Ratings 9.5 to 16.5 10 30 10 Unit V mA mA mA Electrical Characteristics at Ta = 25°C, VCC = 15V Ratings Parameter Supply current 1 Supply current 2 Output Block High level output voltage Low level output voltage Lower output ON resistance Upper output ON resistance Output leakage current Minimum output pulse width Output minimum dead time 5V Constant Voltage Output Output voltage Voltage fluctuation Load fluctuation Hall Amplifier Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis width Input voltage Low Input voltage High High Low IB (HA) VICM1 VICM2 VHIN ΔVIN (HA) VSLH VSHL When a Hall element is used Single-sided input bias mode (when a Hall IC is used) Sine wave, Hall element offset = 0V 9 5 -19 20 11 -11 40 19 -5 mV mV mV 80 mVp-p -2 0.3 0 0 VREG-1.7 VREG μA V V VREG ΔV (REG1) ΔV (REG2) IO = -5mA VCC = 9.5 to 16.5V, IO = -5mA IO = -5 to -10mA 4.7 5.0 5.3 100 100 V mV mV VHO VLO RONL RONH IOleak Tmin Tdt 2.0 2.0 IO = -10mA IO = 10mA IO = 10mA IO = -10mA VREG-0.35 VREG-0.15 0.15 15 15 0.3 30 35 10 4.0 4.0 V V Ω Ω μA μs μs Symbol ICC1 ICC2 At stop CTL ≤ 1.0V typ Conditions min typ 5.0 0 max 8.0 20 mA μA Unit Continued on next page. No.A2013-2/19 LV8138V Continued from preceding page. Ratings Parameter CSD Oscillator Circuit High level output voltage Low level output voltage Amplitude External capacitor charging current External capacitor discharging current Oscillation frequency PWM Oscillator (PWM pin) High level output voltage Low level output voltage Amplitude Oscillation frequency Current Limiter Operation Limiter voltage VRF 0.225 0.25 0.275 V VOH (PWM) VOL (PWM) V (PWM) f (PWM) C = 2200pF, R = 15kΩ (design target value) 3.3 1.3 1.78 3.5 1.5 2.0 17 3.7 1.7 2.22 V V Vp-p kHz f (CSD) C = 0.22μF (design target value) 113.6 Hz VOH (CSD) VOL (CSD) V (CSD) ICHG1 (CSD) ICHG2 (CSD) VCHG1 = 2.0V VCHG2 = 2.0V 2.7 0.8 1.75 -17 3 3.0 1.0 2.0 -10 10 3.3 1.2 2.25 -3 17 V V Vp-p μA μA Symbol Conditions min typ max Unit Thermal Shutdown Protection Operation Thermal shutdown protection operating temperature Hysteresis width TH pin Protection start voltage Hysteresis width HB pin Output ON resistance Output leakage current RON (HB) IL (HB) IHB = 10mA Power saving mode VCC = 15V 15 30 10 Ω μA VTH ΔVTH 0.25 0.2 0.6 0.4 1.05 0.6 V V ΔTSD TSD * Design target value (junction temperature) * Design target value (junction temperature) 35 °C 150 175 °C Low Voltage Protection Circuit (detecting VCC voltage) Operation voltage Hysteresis width FG1 FG3 Pin Output ON resistance Output leakage current CTL Amplifier (drive mode) Input voltage range High level input voltage Middle level input voltage CTL Amplifier (power saving mode) Low level input voltage Hysteresis width Input current F/R Pin High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) VF/R = VREG VF/R = 0V 0.21 10 -10 3.0 0 0 0.31 50 0 VREG 0.7 0.3 0.41 100 +10 V V V V μA μA VIL1 (CTL) ΔCTL IIH (CTLI) CTL = 3.5V Power saving mode 0.15 10 1.0 0.5 18 1.5 0.85 26 V V μA VIN (CTL) VIH (CTL) VIM (CTLI) PWM ON duty 100% PWM ON duty 0% 0 5.1 1.8 5.4 2.1 VCC 5.7 2.4 V V V RON (FG) IL (FG) IFG = 5mA VFG = 18V 40 60 10 Ω μA VSD ΔVSD 7.0 0.25 8.0 0.5 9.0 0.75 V V Continued on next page. No.A2013-3/19 LV8138V Continued from preceding page. Ratings Parameter FAULT Pin Drive stop voltage Drive start voltage Input open voltage High level input current Low level input current ADP1 Pin (drive phase adjustment) Minimum lead angle Maximum lead angle Current ratio with the ADP2 pin current ADP2 Pin (drive phase adjustment) High level output voltage Low level output voltage VADP2H VADP2L CTL = 5.4V CTL = 0V 1.95 0 2.5 3.05 0.51 V V Vadp01 Vadp16 ADP ADP1 pin = 0V ADP1 pin = VREG CTL = 3.75V, IADP1/IADP2 56 1.45 0 58 2 2.55 2 Deg Deg A/A VFOF VFON VIO (FLT) IIH (FLT) IIL (FLT) VFLT=VREG VFLT=0V -250 0 3.0 4.6 VREG 0 -160 10 -70 0.35 VREG V V V μA μA Symbol Conditions min typ max Unit DPL Pin (drive-phase-adjustment limit setting pin) Lead angle limit high level voltage Lead angle limit low level voltage VDPLH VDPLL 3.3 1.3 3.5 1.5 3.8 1.7 V V * These are design target values and no measurements are made. No.A2013-4/19 LV8138V Package Dimensions nit : mm (typ) 3191C 9.75 30 1.5 Pd max - Ta Specified circuit board : 114.3 × 76.1 × 1.6mm3 glass epoxy Mounted on a specified circuit board. Allowable power dissipation, Pd max -- W 1.05 1.0 5.6 7.6 1 0.65 (0.33) (1.3) 1.5 MAX 0.22 0.15 0.5 0.5 0.45 Independent IC 0.38 0.16 0 --40 0.1 --20 0 20 40 60 80 100 120 Ambient temperature, Ta -- C SANYO : SSOP30(275mil) Pin Assignment VREG5 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RPWM 16 LV8138V 1 IN1+ 2 IN1- 3 IN2+ 4 IN2- 5 IN3+ 6 IN3- 7 GND 8 VCC 9 CTL 10 DPL 11 FG3 12 FG1 13 ADP2 14 CSD 15 ADP1 Top view CPWM FAULT HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 HB TH RF TGND FR No.A2013-5/19 STK5C4-XXX VB1 VCC + IN1+ IN1- IN2+ IN2- IN3+ IN3VREG VCC VREG HALL HYS AMP LVSD ENABLE FAULT FAULT HIN1 MOSC HIN2 PRE DRIVER HIN3 LIN1 LIN2 LIN3 VREG CONTROL CIRCUIT HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 TH1 TH2 TH ITRIP CURR LIM RF Rf GND TGND U-,V-,WRCIN VS3,WOUT VS2,VOUT FAULT VREG HB HB VS2,VOUT VB3 VS1,UOUT VB2 VCC VM + CSD VREG CSD OSC VS3,WOUT VDD VSS VS1,UOUT DPL ADP2 Drive Phase Revise VREG M LV8138V Sample Application Circuit 1 (Hall element, HIC) ADP1 Drive Phase Setting VREG VREG Rotate Detect TSD RESET CTL AMP F/R PWM OSC PWM GENERATE FG1 FG1 Output FG3 FG FG3 Output CTL RPWM CPWM F/R CTL Input F/R Input No.A2013-6/19 Hall IC VREG Input1 VB1 VCC + VREG VCC VREG HALL HYS AMP LVSD ENABLE FAULT FAULT HIN1 MOSC HIN2 PRE DRIVER HIN3 LIN1 LIN2 LIN3 VREG CONTROL CIRCUIT HIN2 HIN3 LIN1 LIN2 LIN3 TH1 TH2 ITRIP CURR LIM RF U-,V-,WRCIN GND TGND VS3,WOUT HIN1 VS2,VOUT FAULT VREG HB HB VS2,VOUT VB3 VS1,UOUT VB2 VCC + VM Hall IC Input2 Hall IC Input3 STK5C4-XXX IN1+ IN1- IN2+ IN2- IN3+ IN3- CSD VREG CSD OSC VS3,WOUT VDD VSS VS1,UOUT DPL ADP2 Drive Phase Revise Sample Application Circuit 2 (Hall IC, HIC) VREG M LV8138V ADP1 Drive Phase Setting VREG VREG Rotate Detect TSD TH RESET CTL AMP F/R PWM OSC PWM GENERATE FG1 FG1 Output FG3 FG FG3 Output CTL RPWM CPWM F/R Note : The Hall IC to be used must be of open collector or open drain type (no internal pull-up resistor connected to the output). CTL Input F/R Input No.A2013-7/19 VCC + VREG VCC MURA260T3 IN1+ IN1- IN2+ IN2- IN3+ IN3VREG HB VREG HB TND525/NCP5106 ATP613 VM + CSD LVSD FAULT FAULT HIN1 MURA260T3 VREG CSD OSC 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 HALL HYS AMP DPL UOUT ATP613 ADP2 MOSC HIN2 PRE DRIVER HIN3 LIN1 LIN2 LIN3 VREG 1 2 3 4 VCC VB HIN HO LIN VS COM LO Drive Phase Revise TND525/NCP5106 8 7 6 5 VREG CONTROL CIRCUIT ATP613 LV8138V ADP1 Drive Phase Setting Sample Application Circuit 3 (Hall erement, FET) ATP613 MURA260T3 ATP613 TND525/NCP5106 M VOUT VREG VREG Rotate Detect TSD TH RESET CTL AMP PWM OSC F/R RF CURR LIM PWM GENERATE FG1 FG1 Output FG3 FG FG3 Output 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 ATP613 WOUT CTL RPWM CPWM F/R GND TGND CTL Input F/R Input No.A2013-8/19 Hall IC VREG Input1 VCC + VREG VCC MURA260T3 Hall IC Input2 Hall IC Input3 IN1+ IN1- IN2+ IN2- IN3+ IN3VREG HB VREG HB TND525/NCP5106 ATP613 VM + CSD LVSD FAULT FAULT HIN1 MURA260T3 VREG CSD OSC 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 HALL HYS AMP DPL UOUT ATP613 ADP2 MOSC HIN2 PRE DRIVER HIN3 LIN1 LIN2 LIN3 VREG 1 2 3 4 Drive Phase Revise TND525/NCP5106 VCC VB HIN HO LIN VS COM LO 8 7 6 5 Sample Application Circuit 4 (Hall IC, FET) VREG CONTROL CIRCUIT ATP613 LV8138V ADP1 Drive Phase Setting ATP613 MURA260T3 ATP613 TND525/NCP5106 M VOUT VREG VREG Rotate Detect TSD TH RESET PWM OSC F/R RF CURR LIM FG1 FG1 Output PWM GENERATE FG3 FG FG3 Output CTL AMP 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 ATP613 WOUT CTL RPWM CPWM F/R GND TGND Note: The Hall IC to be used must be of open collector or open drain type (no internal pull-up resistor connected to the output). CTL Input F/R Input No.A2013-9/19 LV8138V Pin Functions Pin No. 1 2 3 4 5 6 Pin Name IN1+ IN1IN2+ IN2IN3+ IN3Pin function Hall signal input pins. The high state is when IN+ is greater than IN-, and the low state is the reverse. An amplitude of at least 100mVp-p (differential) is desirable for the Hall signal inputs. If noise on the Hall signals is a problem, insert capacitors between IN+ and IN- pins. If input is provided from a Hall IC, the common-mode input range can be expanded by biasing either + or -. Equivalent Circuit VREG 1 3 5 500Ω 500Ω 2 4 6 7 8 GND VCC Ground pin of the control circuit block. Power supply pin for control. Insert a capacitor between this pin and ground to prevent the influence of noise, etc. 9 CTL Control input pin. When CTL pin voltage rises, the IC changes the output signal PWM duty to increase the torque output. VREG VCC 65kΩ 9 125kΩ 10 DPL Setting pin for drive phase adjustment limit. This pin is used to limit the lead angle of the drive phase. The lead angle is limited to zero degrees when the voltage is 1.5V or lower and the limit is released when the voltage is 3.5V or higher. VREG 500Ω 10 11 12 FG3 FG1 FG3 : 3-Hall FG signal output pin. 8-pole motor outputs 12 FG pulses per one rotation. In power saving mode, high-level is output. FG1 :1-Hall FG signal output pin. 8-pole motor outputs 4 pulses per one rotation. In power saving mode, high-level is output. VREG 11 12 25Ω Continued on next page. No.A2013-10/19 LV8138V Continued from preceding page. Pin No. 13 Pin Name ADP2 Pin function Setting pin for phase drive correction. This pin sets the amount of correction made to the lead angle according to the CTL input. Insert a resistor between this pin and ground to adjust the amount of correction. Equivalent Circuit VCC VREG VREG 500Ω 500Ω 13 14 CSD Pin to set the operating time of the motor constraint protection circuit. Insert a capacitor between this pin and ground. This pin must be connected to ground if the constraint protection circuit is not used. VREG 500Ω 500Ω 14 15 ADP1 Drive phase adjustment pin. The drive phase can be advanced from 0 to 58 degrees during 180-degree current carrying drive. The lead angle becomes 0 degrees when 0V is input and 58 degrees when 5V is input. VCC VREG AD 500Ω 15 500Ω 16 CPWM Triangle wave oscillation pin for PWM generation. Insert a capacitor between this pin and ground and a resistor between this pin and RPWM for triangle wave oscillation. VREG 200Ω 16 17 RPWM Oscillation pin for PWM generation. Insert a resistor between this pin and CPWM. VREG 17 Continued on next page. No.A2013-11/19 LV8138V Continued from preceding page. Pin No. 18 20 Pin Name FR TGND FR Forward/reverse rotation setting pin. A low-level specifies forward rotation and a high-level specifies reverse rotation. This pin is held low when open. Pin function Equivalent Circuit VREG 2kΩ TGND Test pin. Connect this pin to ground. 18 20 100kΩ 19 VREG5 5V regulator output pin (control circuit power supply). Insert a capacitor between this pin and ground for power stabilization. 0.1μF or so is desirable. VCC 50Ω 19 21 RF Output current detection pin. This pin is used to detect the voltage across the current detection resistor (Rf). The maximum output current is determined by the equation IOUT = 0.25V/Rf. VREG 21 22 TH Thermistor connection pin. The thermistor detects heat generated from HIC and turns off the drive output when an overheat condition occurs. If the pin voltage is 0.6V or lower, the drive output is turned off. VREG 500Ω 22 Continued on next page. No.A2013-12/19 LV8138V Continued from preceding page. Pin No. 23 Pin Name FAULT Pin function HIC protection signal input pin. This pin accepts an error mode detection signal generated by the HIC side. A low-level indicates that an error mode is detected and turns off the drive output. Equivalent Circuit VREG 30kΩ 500Ω 23 24 25 26 27 28 29 LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 LIN1, LIN2, and LIN3 : L-side output pins. Generate 0 to VREG5 push-pull outputs. HIN1, HIN2, and HIN3 : H-side output pins. Generate 0 to VREG5 push-pull outputs. VREG 25 27 29 500Ω 24 26 28 30 HB Hall bias HIC power supply pin. Insert a capacitor between this pin and ground. This pin is set to high-impedance state in power saving mode. By supplying Hall bias and HIC power using this pin, the power consumption by Hall bias and HIC in power saving mode can be reduced to zero. VCC 30 No.A2013-13/19 LV8138V Timing Chart (IN = “H”indicates the state in which IN+ is greater than IN-.) (1) F/R pin = L Normal hall input LA=0 IN1+ IN1IN2+ IN2IN3+ IN3- IN1 IN2 IN3 H L H H L L H H L L H L L H H L L H H L H H L L H H L L H L L H H L L H F/R="L"120° energization HIN1 ON UOUT OFF LIN1 ON HIN2 ON PWM PWM VOUT OFF LIN2 ON HIN3 ON PWM PWM PWM WOUT OFF LIN3 ON PWM PWM F/R="L"sin wave drive method Max Duty UOUT 0% Max Duty VOUT 0% Max Duty WOUT 0% F/R="H"120° energization in reverse rotate HIN1 ON UOUT OFF LIN1 ON HIN2 ON PWM PWM VOUT OFF LIN2 ON HIN3 ON PWM PWM WOUT OFF LIN3 ON PWM PWM 3 HALL FG 1 HALL FG The energization is switched to 120° when 3 Hall FG frequency is 6.1Hz (TYP) or lower A direction of rotation is detected from Hall signal according to F/R pin input If the motor rotates in reverse against F/R pin input, 120° energization is maintained forcibly. No.A2013-14/19 LV8138V (2) F/R pin = H Reverse hall input LA=0 IN1+ IN1IN2+ IN2IN3+ IN3- IN1 IN2 IN3 L L H L H H L H L H H L H L L H L H L L H L H H L H L H H L H L L H L H F/R="H"120° energization HIN1 ON UOUT OFF LIN1 ON HIN2 ON PWM PWM VOUT OFF LIN2 ON HIN3 ON PWM PWM WOUT OFF LIN3 ON PWM PWM F/R="H" sin wave drive method Max Duty UOUT 0% Max Duty VOUT 0% Max Duty WOUT 0% F/R="L"120° energization in reverse rotate HIN1 ON UOUT OFF LIN1 ON HIN2 ON PWM PWM VOUT OFF LIN2 ON HIN3 ON PWM PWM PWM WOUT OFF LIN3 ON PWM PWM 3 HALL FG 1 HALL FG The energization is switched to 120° when 3 Hall FG frequency is 6.1Hz (TYP) or lower A direction of rotation is detected from Hall signal according to F/R pin input If the motor rotates in reverse against F/R pin input, 120° energization is maintained forcibly. No.A2013-15/19 LV8138V Functional Description • Basic operation of 120-degree ⇔ 180-degree current-carrying switching At startup, this IC starts at 120-degree current-carrying. The current-carrying is switched to 180 degrees when the 3-Hall FG frequency is 6.1Hz (typ) or above and the rising edge of the IN2 signal has been detected twice in succession. signal input sequence ° Concerning the Hall motor rotation direction commands and Hall signal input sequence in order to set the lead angle. If This IC controls the the motor rotation direction commands and Hall signal input sequence do not conform to what is shown on the timing chart, the motor is driven by 120-degree current-carrying. Example 1 : When the Hall signal has been input with the following logic IN1 IN2 IN3 H L H H L L H H L L H L L H H L L H → → → → → When F/R pin input is high → 120-degree current-carrying When F/R pin input is low → 180-degree current-carrying Example 2 : When the Hall signal has been input with the following logic IN1 IN2 IN3 H L H L L H L H H L H L H H L H L L → → → → → When F/R pin input is high → 180-degree current-carrying When F/R pin input is low → 120-degree current-carrying • CTL pin input a) Power-saving mode VCTL < VIL (1.0V : typ) When the CTL pin voltage is lower than VIL (1.0V : typ), the IC enters the power-saving mode, and the following are set : • LIN1 to LIN3 and HIN1 to HIN3 outputs all set to low • ICC = 0, HB pin = OFF The power consumption of the IC can now be set to 0, and the power consumption of the Hall element connected to the HB pin and the output block can also be set to 0. b) Standby mode VIL < VCTL < VIM (2.1V : typ) When the CTL pin voltage is VIL < VCTL < VIM, the IC enters the standby mode. Low is output for the UIN1 to UIN3 outputs and bootstrap charge pulses (2μs pulse width: design target) are output to the LIN1 to LIN3 outputs to prepare for drive start. c) Drive mode VIM < VCTL < VIH (5.4V : typ) When the CTL pin voltage is VIM < VCTL < VIH, the IC enters the drive mode, and the motor is driven at the PWM duty ratio corresponding to VCTL. When VCTL is increased, the PWM duty ratio increases, and the maximum duty ratio is reached at VIH. d) Test mode 8V < VCTL < VCTL max (design target) When the CTL pin voltage is 8V or higher, the IC enters the test mode, and the motor is driven at the 120-degree current-carrying and maximum duty* ratio. * When the PWM oscillation frequency setting is 17kHz (*90% : typ). • The CTL pin is pulled down by 190kΩ : typ inside the IC. Caution is required when the control input voltage input is subjected to resistance division, for example. • Bootstrap capacitor initial charging mode When the mode is switched from the power-saving mode to the standby mode and then to the drive mode, the IC enters the bootstrap capacitor charging mode (UH, VH, WH pins = L UL, VL, WL pins = H 3.84ms typ) in order to charge the bootstrap capacitor. No.A2013-16/19 LV8138V • Drive phase adjustment During 180-degree current-carrying drive, any lead angle from 0 to 58 degrees can be set using the ADP1 pin voltage (lead angle control). This setting can be adjusted in 32 steps (in 1.875-degree increments) from 0 to 58 degrees using the ADP1 pin voltage, and it is updated every Hall signal cycle (it is sampled at the rising edge of the IN3 input and updated at its falling edge). A number of lead angle adjustments proportionate to the CTL pin voltage can be undertaken by adjusting the resistance levels of resistors connected to the ADP1 pin, ADP2 pin and DPL pin. When these pins are not going to be used, reference must be made to section 4.5, and the pins must not be used in the open status. Furthermore, a resistance of 47kΩ or more must be used for the resistor (RADP2) that is connected to the ADP2 pin. 1. The slopes of VCTL and VADP1 can be adjusted by setting the resistance level of the resistor (RADP1) connected to ADP1 (pin 15). VADP1,VADP2[V] ADP2 VREG RDPL1 Lead Angle[∞ ] 32 steps IADP2 IADP1 RADP2 RADP1 2.5V 2.34V ADP2 VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=IADP1×RADP1 0∞ 0V VCTL[V] 2. The ADP2 pin rise can be halted (a limit on the lead angle adjustment can be set by means of the CTL voltage) by setting DPL (pin 10). VADP1,VADP2[V] ADP2 VREG RDPL1 Lead Angle[°] 32 steps IADP2 RDPL2 IADP1 RADP2 RADP1 2.5V 1.25V 1.17V 0° 0V ADP2 2.1V 3.75V 5.4V VCTL[V] VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=IADP1×RADP1 DPLLIM=VDPL×1.5 3. The offset and slope can be adjusted as desired by setting RADP1 and RADP12 of ADP1 (pin 15). (It is also possible to set a limit on the lead angle adjustment by means of the CTL voltage by setting DPL.) VADP1,VADP2[V] 58° 5V VREG ADP2 ADP1 IADP1 4.25V DPL ADP1 VREG RDPL12 RADP1 Lead Angle[°] 32 steps RDPL1 2.5V ADP2 DPL 58° 5V IADP2 RADP2 0.88V 0° 0V 2.1V 5.4V VCTL[V] VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=((RADP1×RADP12)/(RADP1+RADP12))×IADP1 +(RADP1/(RADP1+RADP12))×VREG 4. When the lead angle is not adjusted ADP1 pin: shorted to ground; ADP2 pin and DPL pin: pulled down to ground using the resistors 5. When the lead angle is not adjusted by means of the CTL pin voltage (for use with a fixed lead angle) ADP1 pin: lead angle setting by resistance division from VREG; ADP2 pin and DPL pin: pulled down to ground by the resistors ADP1 No.A2013-17/19 DPL 58∞ 5V LV8138V Description of LV8138V 1. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VRF/Rf (where VRF = 0.25V typ, Rf is the value of the current detection resistor). The current limiter operates by reducing the output on duty to suppress the current. The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the current limiting function does not malfunction, its operation has a delay of approx. 1μs. If the motor coils have a low resistance or a low inductance, current fluctuation at startup (when there is no back electromotive force in the motor) will be rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. Application must take this increase in the current due to the delay into account when the current limiter value is set. 2. Power Saving Circuit (CTL pin) This IC goes into the power saving mode that stops operation of all the circuits to reduce the power consumption. If the HB pin is used for the Hall element bias and the output block, the current consumption in the power-saving mode is zero. 3. Hall Input Signal Signals with an amplitude in excess of the hysteresis is required for the Hall inputs. However, considering the influence of noise and phase displacement, an amplitude of over 100mV is desirable. If noise disrupts the output waveform (at phase change), this must be prevented by inserting capacitors or other devices across the Hall inputs. The constraint protection circuit uses the Hall inputs to discriminate the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise, care is required. If all three phases of the Hall input signal go to the same input state (HHH or LLL), the outputs are all set to the off state. If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or –side) at a voltage within the common-mode input voltage range (0.3V to VREG-1.7V) allows the other input side to be used as an input over the 0V to VREG range. 4. Constraint Protection Circuit This IC goes into the power saving mode that stops operation of all the circuits to reduce the power consumption. If the HB pin is used for the Hall element bias and the output block, the current consumption in the power-saving mode is zero. This IC provides an on-chip constraint protection circuit to protect the IC itself and the motor when the motor is constrained. If the Hall input signals do not change for over a fixed period when the motor is in operation, this circuit operates. Also, the upper-side output transistor is turned off while the constraint protection circuit is operating. This time is determined by the capacitance of the capacitor connected to the CSD pin. Set time (in seconds) ≈ 90 × C (μF) If a 0.022μF capacitor is used, the protection time will be about 2.0 seconds. The set time must be selected to have an adequate margin with respect to the motor startup time Conditions to clear the constraint protection state : CTL pin when a low-level voltage is input → Release protection and reset count When TSD protection is detected → Stop count 5. Power Supply Stabilization Since this IC adopts a switching drive technique, the power-supply line level can be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the VCC pins and ground. If the electrolytic capacitors cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1μF must be connected near these pins. If diodes are inserted in the power-supply line to prevent destruction of the device when the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. No.A2013-18/19 LV8138V 6. VREG Stabilization A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply. The ground lead of that capacitor must be located as close as possible to the control system ground (SGND) of the IC. 7. Forward/Reverse Switching (F/R pin) Switching between forward rotation and reverse rotation must not be undertaken while the motor is running. 8. TH Pin The TH pin must normally be pulled up to the 5V regulator for use. When it has been set to low, the outputs are low. 9. FAULT Pin The FAULT pin must normally be pulled up to the 5V regulator for use. When it has been set to low, the outputs are low. In addition, the FG output does OFF, too 10. PWM Frequency Setting fCPWM ≈ 1/ (1.78CR) Components with good temperature characteristics must be used. An oscillation frequency of about 17kHz is obtained when a 2200pF capacitor and 15kΩ resistor are used. If the PWM frequency is too low, switching noise will be heard from the motor; conversely, if it is too high, the output power loss will increase. For this reason, a frequency between 15kHz and 30kHz or so is desirable. The capacitor ground must be connected as close as possible to the control system ground (SGND pin) of the IC to minimize the effects of the outputs. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2012. Specifications and information herein are subject to change without notice. PS No.A2013-19/19