LV8827LF

Ordering number : ENA1865 Bi-CMOS IC LV8827LF Overview For Brushless Motor Drive PWM Driver IC The LV8827LF is a PWM-type driver IC designed for 3-phase brushless motors. The rotational speed can be controlled by inputting the PWM pulse from the outside, and changing Duty. The IC incorporates a latch-type constraint protection circuit. Features • IO max = 1.5A (built-in output Tr) • Speed control and synchronous rectification using direct PWM input (supports 3.3V inputs) • 1-Hall FG output • Latch type constraint protection circuit (the latch is released by S/S and F/R.) • Forward/reverse switching circuit, Hall bias pin • Power save circuit (Power save in stop mode) • Current limiter circuit, Low-voltage protection circuit, Overheat protection circuit • Charge pump circuit, 5V regulator output. • Start/stop circuit (short brake when motor is to be stopped) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. N0410 SY 20101015-S00002 No.A1865-1/13 LV8827LF Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol VCC max VG max Output current Allowable power dissipation IO max Pd max1 Pd max2 Junction temperature Operating temperature Storage temperature Tj max Topr Tstg VCC pin VG pin t ≤ 500ms *1 Independent IC Mounted on a circuit board.*2 Conditions Ratings 36 42 1.5 0.2 1.35 150 -40 to +80 -55 to +150 Unit V V A W W °C °C °C *1 : Tj cannot exceed Tj max = 150°C *2 : Specified circuit board : 40mm × 50mm × 0.8mm, glass epoxy (four-layer board) Allowable Operating range at Ta = 25°C Parameter Supply voltage range 5V constant voltage output current HB pin output current FG pin applied voltage FG pin output current Symbol VCC IREG IHB VFG IFG Conditions Ratings 8.0 to 35 0 to -10 0 to -200 0 to 6 0 to 10 Unit V mA μA V mA Electrical Characteristics at Ta = 25°C, VCC = 24V Parameter Supply current 1 Supply current 2 Output block Low-side output ON resistance High-side output ON resistance Low-side output leak current High-side output leak current Low-side diode forward voltage High-side diode forward voltage 5V Constant-voltage Output Output voltage Line regulation Load regulation Hall Amplifier Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis width Input voltage Low → High Input voltage High → Low CSD oscillator circuit High level output voltage Low level output voltage Amplitude External capacitor charge current External capacitor discharge current Oscillation frequency Charge pump output (VG pin) Output voltage VGOUT VCC+4.5 V VOH (CSD) VOL (CSD) V (CSD) ICHG1 (CSD) VCHG1 = 2.0V ICHG2 (CSD) VCHG2 = 2.0V f (CSD) C = 0.022μF (Design target value) 2.7 0.9 1.6 -14 9.5 3.0 1.1 1.9 -11.5 12 130 3.3 1.3 2.2 -9 14.5 V V Vp-p μA μA Hz IB (HA) VICM1 VICM2 VHIN ΔVIN (HA) VSLH VSHL When using Hall elements At one-side input bias (Hall IC application) SIN wave -2 0.3 0 80 9 3 -19 20 9 -11 35 16 -5 VREG-1.7 VREG μA V V mVp-p mV mV mV VREG ΔV (REG1) ΔV (REG2) IO = -5mA VCC = 8.0 to 35V, IO = -5mA IO = -5m to -10mA 4.8 5.1 5.4 50 100 V mV mV RON (L1) RON (H1) IL (L) IL (H) VD (L1) VD (H1) ID = -1.0A ID = 1.0A -50 1.0 1.1 1.2 1.3 IO = 1.0A IO = -1.0A 0.47 0.67 0.65 0.9 50 Ω Ω μA μA V V Symbol ICC1 ICC2 At stop Conditions min Ratings typ 3.3 0.7 max 4.0 0.8 mA mA Unit Continued on next page. No.A1865-2/13 LV8827LF Continued from preceding page. Parameter CP1 pin Output ON resistance (High level) Output ON resistance (Low level) Charge pump frequency Internal PWM frequency Oscillation frequency Current limiter operation Limiter voltage Thermal shutdown operation Thermal shutdown operation temperature Hysteresis width HB pin Output voltage VHB IHB = -100μA 3.4 3.6 3.8 V ΔTSD *Design target value (junction temperature) 30 °C TSD *Design target value (junction temperature) 150 165 180 °C VRF 0.19 0.21 0.23 V f (PWM) 41 51.5 62 kHz VOH (CP1) VOL (CP1) f (CP) ICP1 = -2mA ICP1 = 2mA 82 500 350 103 700 500 124 Ω Ω kHz Symbol Conditions min Ratings typ max Unit Low-voltage protection (5V constant-voltage output detection) Operation voltage Hysteresis width FG pin (3FG pin) Output ON resistance Output leak current S/S pin High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current PWMIN pin Recommended input frequency High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current F/R pin High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) *Design target value VF/R = VREG VF/R = 0V *Design target value *Design target value 2.0 0 VREG-2.2 0.25 45 -115 VREG-2.0 0.33 60 -90 VREG 1.0 VREG-1.8 0.4 75 -65 V V V V μA μA F (PWIN) VIH (PWIN) VIL (PWIN) VIO (PWIN) VIS (PWIN) IIH (PWIN) IIL (PWIN) VPWIN = VREG VPWIN = 0V 0.5 2.0 0 VREG-2.2 0.25 45 -115 VREG-2.0 0.33 60 -90 60 VREG 1.0 VREG-1.8 0.4 75 -65 kHz V V V V μA μA VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VSS = VREG VSS = 0V 2.0 0 VREG-2.2 0.25 45 -115 VREG-2.0 0.33 60 -90 VREG 1.0 VREG-1.8 0.4 75 -65 V V V V μA μA VOL (FG) IL (FG) IFG = 5mA VO = 5V 40 60 10 Ω μA VSD ΔVSD 3.95 0.2 4.15 0.3 4.35 0.4 V V * : Design target value and no measurement is made. No.A1865-3/13 LV8827LF Package Dimensions unit : mm (typ) 3400 2 Pd max – Ta Specified board : 40 × 50 × 0.8mm3 glass epoxy (four-layer board) TOP VIEW 4.0 SIDE VIEW BOTTOM VIEW Allowable power dissipation, Pd max -- W 1.5 1.35 4.0 (2.4) (2.4) 1 0.756 0.45 12 0.25 0.5 21 (0.75) 24 0.5 (0.8) SIDE VIEW 0.85 MAX 0.2 0.112 0 --40 --20 0 20 40 60 80 100 0.0 NOM Ambient temperature, Ta -- °C SANYO : VQFN24K(4.0X4.0) Pin Assignment PWMIN CSD 24 23 22 21 20 19 IN3- 1 S/S F/R HB FG 18 PGND IN3+ 2 17 RF IN2- 3 16 OUT2 IN2+ 4 15 OUT3 IN1IN1+ 5 14 OUT1 6 13 VG 7 SGND 8 VREG 9 CP2 10 CP1 11 VCC1 12 VCC2 No.A1865-4/13 LV8827LF Three-phase logic truth table (IN = “High” indicates the state where IN+ > IN-.) ("H" = SOURCE, "L" = SINK, and "M" = output OFF are shown with OUT1 to 3.) F/R = ⎡H⎦ IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = ⎡L⎦ IN2 H H L L L H IN3 L H H H L L OUT1 L L M H H M Output OUT2 H M L L M H OUT3 M H H M L L F/R IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H Output FG L L L H H H S/S pin, PWMIN pin Input state High or Open Low S/S pin Stop (short brake) Start PWMIN pin Output OFF Output ON CSD function When the S/S pin is in a STOP state When the F/R pin is switched When 0% duty is detected at the PWMIN pin input When low-voltage condition is detected When TSD condition is detected → → → → → Protection released and count reset (Initial reset) Protection released and count reset Protection released and count reset Protection released and count reset (Initial reset) Stop counting No.A1865-5/13 LV8827LF Internal Equivalent Circuit and Sample External Component Circuit F/R input PWMIN input S/S input F/R PWMIN S/S F/R PWMIN S/S VREG VREG CSD CSD OSC MOSC LDA 3FG CONTROL CIRCUIT VCC LVSD VCC1 VCC2 TSD CHARGE PUMP VG CP1 CP2 OUT1 DRIVER HALL HYS AMP CURR LIM OUT2 + FG output FG FG OUT3 HB IN1+ IN1- IN2+ IN2- IN3+ IN3- HB VCC RF SGND PGND No.A1865-6/13 LV8827LF Pin Functions Pin No. 1 2 3 4 5 6 Pin Name IN3IN3+ IN2IN2+ IN1IN1+ Hall input pin. •High when IN+ > IN-. Low in reverse relationship. The input amplitude of over 100mVp-p (differential) is desirable in the Hall inputs. Insert a capacitor between the IN+ and IN- pins if the noise on the Hall signal is a problem. Pin function Equivalent Circuit VREG 1 3 5 500Ω 500Ω 2 4 6 7 8 SGND VREG Control circuit block ground pin. 5V regulator output pin (control circuit power supply). Insert a capacitor between this pin and ground for stabilization. About 0.1μF is necessary. VCC 50Ω 8 9 10 11 CP2 CP1 VCC1 Charge pump capacitor connection pin. Insert capacitor between CP1 and CP2. Control power pin. Insert a capacitor between this pin and ground to prevent the influence of noise, etc. 12 VCC2 Output power pin. Insert a capacitor between this pin and ground to prevent the influence of noise, etc. 13 VG Charge pump output pin. (Upper-side FET gate power supply) Insert a capacitor between this pin and VCC. VCC 300Ω 200Ω 10 CP CG 13 9 Continued on next page. No.A1865-7/13 LV8827LF Continued from preceding page. Pin No. 14 15 16 Pin Name OUT1 OUT3 OUT2 Output pin. PWM is controlled by the upper-side FET. Pin function Equivalent Circuit VCC 14 15 16 17 17 RF Output current detection pin. Insert a low resistance resistor (Rf) between this pin and ground. VREG 17 5kΩ 18 19 PGND S/S Out circuit block ground pin. Pin to select the start/stop type. Stop = High or open Start = Low VREG 50kΩ 5kΩ 19 75kΩ 20 FG FG signal output pin. 1-Hall FG (IN1). Open drain output. VREG 20 Continued on next page. No.A1865-8/13 LV8827LF Continued from preceding page. Pin No. 21 Pin Name F/R Pin function Pin to select the forward/reverse type. This pin goes to the high level when open. Equivalent Circuit VREG 50kΩ 5kΩ 21 75kΩ 22 CSD Pin to set the constraint protection circuit operating time and initial reset pulse. Insert a capacitor between this pin and ground. Insert a resistor in parallel with the capacitor if the protection circuit is not to be used. VREG 500Ω 22 23 PWMIN External PWM input pin. Apply an external PWM input signal to this pin. (Input frequency range is from 0.5 to 60kHz.) PWM ON = Low PWM OFF = High or open VREG 50kΩ 5kΩ 23 75kΩ 24 HB HALL bias pin (3.6V output). Connect an NPN transistor. (See “5 Hall Input Signal.") VREG 300Ω 250Ω 24 No.A1865-9/13 LV8827LF Description of LV8827LF 1. Output Drive Circuit This IC adopts a direct PWM drive method to reduce power loss in the output. It regulates the drive force of the motor by changing the output on duty. The output PWM switching is performed by the upper-side output transistor. The current regeneration route during the normal PWMOFF passes through the parasitic diode of the output DMOS. This IC performs synchronous rectification, and is intended to reduce heat generation compared to diode regeneration. 2. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VRF/Rf (VRF = 0.21V (typical), Rf: current detection resistor). This circuit suppresses the output current by reducing the output on duty. The current limiter circuit has an operation delay (approx. 700ns) to detect reverse recovery current flowing in the diode due to the PWM operation, and prevent a malfunction of the current limiting operation. If the coil resistance of the motor is small, or the inductance is low, the current at startup (the state in which there is no back electromotive force generated in the motor) will change rapidly. As a result, the operation delay may sometimes cause the current limiting operation to take place at a value above the set current. In such a case, it is necessary to set the current limit value while taking into consideration the increase in current due to the delay. * Regarding the PWM frequency in the current limiter circuit The PWM frequency in the current limiter circuit is determined by the internal reference oscillator, and is approximately 50kHz. 3. Speed control method Pulses are input to the PWMIN pin, and the output can be controlled by varying the duty cycle of these pulses. When a low-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set to ON. When a high-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set to OFF. If it is necessary to input pulses using inverted logic, this can be done by adding an external transistor (NPN). It is judged Duty=0%, count reset and the HB pin output of the CSD circuit become "L" when the input of the PWMIN pin becomes "H" level during the fixed time, and it enters the state of a short brake. 4. Constraint Protection Circuit The LV8827LF includes a constraint protection circuit for protecting the IC and the motor in a motor constraint mode. This circuit operates when the motor is in an operation condition and the Hall signal does not switch over for a certain period. Note that while this constraint protection is operating, the upper-side output transistor will be OFF. Time setting is performed according to the capacitance of the capacitor connected to the CSD pin. Set time (s) ≈ 90 × C (μF) When a 0.022μF capacitor is connected, the protection time becomes approximately 2.0 seconds. The set time must be selected to a value that provides adequate margin with respect to the motor startup time. Conditions for releasing the constraint protection state: • When the S/S pin is in a STOP state → Protection released and count reset(Initial reset) • When the F/R pin is switched → Protection released and count reset • When 0% duty is detected at the PWMIN pin input → Protection released and count reset • When low-voltage condition is detected → Protection released and count reset (Initial reset) (• When TSD condition is detected → Stop counting) The CSD pin also functions as the initial reset pulse generation pin. If it is connected to ground, the logic circuit will go into a reset state, preventing speed control from taking place. Consequently, when not using constraint protection, connect a resistor of approximately 220kΩ and a capacitor of about 4700pF in parallel to ground. No.A1865-10/13 LV8827LF 5. Hall Input Signal A pulse input with the amplitude in excess of the hysteresis (35mV maximum) is required for the Hall inputs. It is desirable that the amplitude of the Hall input signal be 100mVp-p or more in consideration of the effect of noise and phase displacement. If disturbances to the output waveform (during phase switching) occur due to noise, connect a capacitor between the Hall input pins to prevent such disturbances. In the constraint protection circuit, the Hall input is utilized as a judgment signal. Although the circuit ignores a certain amount of noise, caution is necessary. If all three phases of the Hall input signal go to the same input state (HHH or LLL), the outputs are all set to the OFF state. If the Hall IC is used, fixing one side of the inputs (either the + or – side) at a voltage within the common-mode input voltage range (between 0.3V and VREG-1.7V) allows the other input side to be used as an input over the 0V to VREG range. ○ Method of connecting Hall elements Type (1) connection (three Hall elements connected in series) Advantages • Because the current flowing in Hall elements can be shared by connecting the Hall elements in series, the current consumption is less than that of a parallel-connected arrangement. • The use of a current limiting resistor can be eliminated. • Fluctuations of amplitude with temperature are reduced. Disadvantages • Because only 1V can be applied to one Hall device, there is a possibility that adequate amplitude cannot be obtained. • The current flowing in the Hall elements varies with temperature. Type (2) connection (three Hall elements connected in parallel) Advantages • The current flowing in the Hall elements can be determined by the current limiting resistor. • The voltage applied to the Hall elements can be varied, enabling adequate amplitude to be obtained. Disadvantages • Because it is necessary to supply current separately to each Hall element, the current consumption becomes large. • A current limiting resistor is necessary. • The amplitude varies with temperature. (1) VCC (2) VCC HB 3V Constant-voltage Output HB 3V Constant-voltage Output ○ HB pin The HB pin is used for cutting off the current flowing in the Hall elements during standby (for saving electricity). The output from the HB pin is set to OFF in the following cases. • When the S/S pin is in a STOP state • When 0% duty is detected at the PWMIN pin input No.A1865-11/13 LV8827LF 6. Power Saving Circuit (Start/Stop circuit) To save power when the LV8827LF is in the stop state, most of the circuit is stopped, aiming at reducing current consumption. If the Hall bias pin is used, the current consumption in the power-saving mode will be approximately 700μA. Even in the power-saving mode, a 5V regulator voltage is output. Also, in the power-saving mode, the IC is in a short break state. (lower-side shorted) 7. Power Supply Stabilization This IC generates a large output current, and employs a switching drive method, so the power supply line level can be disturbed easily. For this reason, it is necessary to connect a capacitor (electrolytic) of sufficient capacitance between the VCC pin and ground to ensure a stable voltage. Connect the ground side of the capacitor to the PGND pin, which is the power ground, as close as possible to the pin. If it is not possible to connect a capacitor of sufficiently large capacitance close to the pin, connect a ceramic capacitor of approximately 0.1μF to the vicinity of the pin. If diodes are inserted in the power supply line to prevent IC destruction resulting from reverse-connecting the power supply, the power supply lines are even more easily disrupted. And even larger capacitor is required. 8. VREG Stabilization To stabilize the VREG voltage, which is the power supply for the control circuit, connect a capacitor of 0.1μF or larger. Connect the ground of this capacitor as close as possible to the control block ground (SGND pin) of the IC. 9. Charge pump Circuit The voltage is stepped-up by the charge pump circuit, causing the gate voltage of the upper-side output FET to be generated. The voltage is stepped-up by capacitor CP connected between pins CP1 and CP2, causing charge to accumulate in capacitor CG connected between pins VG and VCC. The capacitance of CP and CG must always satisfy the following relationship. CG ≥ 4 × CP Charging and discharging of capacitor CP take place based on a frequency of 100kHz. When the capacitance of capacitor CP is large, the current supply capability of power supply VG will increase. However, if the capacitance is too large, the charging and discharging operations will be insufficient. The larger the capacitance of capacitor CG, the more stable voltage VG will become. However, if the capacitance is made too large, the period during which voltage VG is generated when the power is switched ON will become long, so caution is necessary. The capacitance settings of CP and CG should be the following. CP = 0.01μF CG = 0.1μF 10. Difference point of LV8827LF and LV8829LF This difference that IC is the more following compared with LV8829LF exists. LV8827LF When Duty=0% of PWM input is detected Short brake LV8829LF Synchronous rectification OFF (Free run) At the low frequency number of PWM input (About 7.5kHz under) At low ON Duty of the PWM input (ex. frequency: 20kHz, ON Duty: 3% under) Backflow current detecting function non It is. (At detection -> Synchronous rectification OFF) Like synchronous rectification ON Synchronous rectification OFF Like synchronous rectification ON Synchronous rectification OFF 11. Metal part at the rear of the IC The metal part at the rear of the IC (exposed die-pad) constitutes the sub ground of the IC, so connect it to the control ground (SGND pin) and power ground pin (PGND) at points close to the IC. No.A1865-12/13 LV8827LF SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2010. Specifications and information herein are subject to change without notice. PS No.A1865-13/13