STK672-070-E

Ordering number : EN7307B Thick-Film Hybrid IC STK672-070-E Overview Unipolar Constant-current Chopper (external excitation PWM) Circuit with Built-in Microstepping Controller Stepping Motor Driver (sine wave drive) Output Current 1.5A (no heat sink*) The STK672-070-E is a stepping motor driver hybrid IC that uses power MOSFETs in the output stage. It includes a builtin microstepping controller and is based on a unipolar constant-current PWM system. The STK672-070-E supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. It supports five excitation methods: 2 phase, 1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. It also allows the motor speed to be controlled with only a clock signal. The use of this hybrid IC allows designers to implement systems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive. This product is provided in a smaller package than SANYO's earlier STK672-040-E for easier mounting in end products. Applications • Facsimile stepping motor drive (send and receive) • Paper feed and optical system stepping motor drive in copiers • Laser printer drum drive • Printer carriage stepping motor drive • X-Y plotter pen drive • Other stepping motor applications Note*: Conditions: VCC1 = 24V, IOH = 1.5A, 2W1-2 excitation mode. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61108HKIM/D1803SI(OT) No.7307-1/18 STK672-070-E Features • Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator. • One of five drive types can be selected with the drive mode settings (M1, M2, and M3) 1) 2 phase excitation drive 2) 1-2 phase excitation drive 3) W1-2 phase excitation drive 4) 2W1-2 phase excitation drive 5) 4W1-2 phase excitation drive • Phase retention even if excitation is switched. • Provides the MOI phase origin monitor pin. • The CLK input counter block can be selected to be one of the following by the high/low setting of the M3 input pin. 1) Rising edge only 2) Both rising and falling edges • The CLK input pin includes built-in malfunction prevention circuits for external pulse noise. • ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20kΩ (typical) pull-up resistors. • No noise generation due to the difference between the A and B phase time constants during motor hold since external excitation is used. • Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any value between 0V and 1/2VCC2. • External excitation PWM drive allows a wide operating supply voltage range (VCC1 = 10 to 45V) to be used. • Current detection resistor (0.22Ω) built-in the hybrid IC itself. • Power MOSFETs adopted for low drive loss. • Provides a motor output drive current of IOH = 1.5A. (at Tc = 105°C) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Input voltage Output current Repeated avalanche capacity Allowable power dissipation Operating IC substrate temperature Junction temperature Storage temperature Symbol VCC1 max VCC2 max VIN max IOH max Ear max Pd max Tc max Tj max Tstg θc-a = 0 No signal No signal Logic input pins 0.5s, 1 pulse, with VCC1 applied Conditions Ratings 52 -0.3 to +7.0 -0.3 to +7.0 2.0 25 6.5 105 150 -40 to +125 Unit V V V A mJ W °C °C °C Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Input voltage Phase driver withstand voltage Output current 1 Output current 2 Symbol VCC1 VCC2 VIH VDSS IOH1 IOH2 Tr1, 2, 3, and 4 (the A, A, B, and B outputs) Tc = 105°C, CLK ≥ 200Hz Tc = 80°C, CLK ≥ 200Hz With signals applied With signals applied Conditions Ratings 10 to 45 5 ± 5% 0 to VCC2 100 (min) 1.5 1.7 Unit V V V V A A No.7307-2/18 STK672-070-E Electrical Characteristics at Tc = 25°C, VCC1 = 24V, VCC2 = 5V Parameters Control supply current Output saturation voltage Average output current FET diode forward voltage [Control Inputs] Input voltage VIH VIL IIH IIL Except for the Vref pin Except for the Vref pin Except for the Vref pin Except for the Vref pin 0 125 1 250 4 1 10 510 V V μA μA Symbols ICC Vsat Ioave Vdf Conditions min Pin 6, with ENABLE pin held low. RL = 12Ω Load: R = 3.5Ω / L = 3.8mH For each phase If = 1A 0.445 Rating typ 2.1 0.65 0.5 1 max 14 1.2 0.56 1.8 mA V A V unit Input current [Vref Input Pin] Input voltage Input current [Control Outputs] Output voltage [Current Distribution Ratio (A·B)] 2W1-2, W1-2, 1-2 2W1-2, W1-2 2W1-2 2W1-2, W1-2, 1-2 2W1-2 2W1-2, W1-2 2W1-2 2 PWM frequency VI II Pin 7 Pin 7, 2.5V input 0 330 415 2.5 545 V μA VOH VOL I = –3mA, pins MOI I = +3mA, pins MOI 2.4 0.4 V V Vref Vref Vref Vref Vref Vref Vref Vref fc θ = 1/8 θ = 2/8 θ = 3/8 θ = 4/8 θ = 5/8 θ = 6/8 θ = 7/8 100 92 83 71 55 40 21 100 37 47 57 % % % % % % % % kHz Note: A constant-voltage power supply must be used. The design target value is shown for the current distribution ratio. Package Dimensions unit:mm (typ) 4186 46.6 41.2 8.5 12.7 1 2.0 (6.6) 14 2.0=28 15 4.0 0.5 1.0 3.6 25.5 0.4 2.9 No.7307-3/18 VCC2 Vref 7 5 4 3 2 A AB B BB 6 M1 Current distribution ratio switching 8 Internal Block Diagram M2 9 Excitation mode control CWB 10 Phase advance counter CLOCK 11 Rise/fall detection and switching Pseudo-sine wave generator M3 12 RESET 13 Phase excitation drive signal generation MOI 14 – + STK672-070-E Excitation state monitor ENABLE 15 RC oscillator PWM control Reference clock generation – + 1 SUB PG A13256 No.7307-4/18 STK672-070-E Test Circuit Diagrams Vsat VCC2 6 Start 11 5 4 8 9 Vref=2.5V 7 V VCC2 13 1 A13257 A13258 Vdf VCC1 6 A AB B BB STK672-070-E V RL 5 4 3 2 A AB B BB 3 2 STK672-070-E + 1 A IIH, IIL VCC2 Ioave, ICC, fc VCC1 VCC2 A M1 M2 M3 6 8 9 12 11 STK672-070-E 10 13 14 15 7 1 + 13 1 fc A STK672-070-E Vref ENABLE 7 15 2 BB SW3 VCC1 8 9 3 4 AB B SW2 6 Start 11 5 A SW1 a ba b IIH A IIL CLK CWB RESET ENABLE A 2.5V Vref A13259 A13260 For Ioave measurement: Set switch SW1 to the b position, provide the Vref input and switch over switch SW2. For fc measurement: Set SW1 to the a position, set Vref to 0V, and switch over switch SW3. For ICC measurement: Set the ENABLE input to the low level. No.7307-5/18 STK672-070-E Power-on Reset The application must perform a power-on reset operation when VCC2 power is first applied to this hybrid IC. Application circuit that used 2W1-2 phase excitation (microstepping operation) mode. VCC2=5V VCC1=10V to 45V 5 14 8 14 9 VCC2=5V ENABLE VF 0.3V + CBW MOI Simple power on reset circuit (This circuit cannot be used for power supply voltage drop detection.) CLK RESET 12 14 15 11 13 10 14 STK672-070-E 1 4 3 2 A AB B BB + SG PG VCC2=5V We recommend a value of about 100Ω for Ro2 to minimize the influence of the Vref pin internal impedance, which is 6kΩ RoX: Input impedance: 6kΩ ±30% A13261 Ro1 7 RoX Vref Ro2 Setting the Motor Current The motor current IOH is set by the Vref voltage on the hybrid IC pin 7. The following formula gives the relationship between IOH and Vref. RoX = (Ro2 × 6kΩ) ÷ (Ro2 + 6kΩ) Vref = VCC2 × RoX ÷ (Ro1 + RoX) IOH = (1) (2) 1 × Vref (3) K Rs K: 5.16 (Voltage divider ratio), Rs: 0.22Ω (This is the hybrid IC's internal current detection resistor. It has a tolerance of ±3%.) Applications can use motor currents from the current (0.05 to 0.1A) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, IOH = 1.5A Ioave 0A Motor current waveform A13262 IOL Function Table M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 Phase switching clock edge timing 1 2W1-2 phase excitation 4W1-2 phase excitation Rising edge only Rising and falling edges Forward CWB 0 Reverse 1 ENABLE RESET Motor current is cut off when low Active low 100μF or higher 6 Two-phase stepping motor IOH No.7307-6/18 STK672-070-E Functional Description External Excitation Chopper Drive Block Description VCC1 IOFF ION Enable φA (control signal) Current divider Vref L2 L1 Divider CR oscillator 800kHz A=1 45kHz S D1 MOSFET AND Q Latch circuit R Noise filter – + Rs A13263 Driver Block Basic Circuit Structure Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required. When a high level is input to φA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be input, the Q output will go high, and the MOSFET will be turned on as its initial value. The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to the latch circuit set pin occurs. In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when the motor is locked. Input Pin Functions Pin No. 11 10 15 8, 9, 12 13 7 Symbol CLK CWB ENABLE M1, M2, M3 RESET Vref Function Phase switching clock Rotation direction setting (CW/CCW) Output cutoff Excitation mode setting System reset Current setting Pin circuit type Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Input impedance 6kΩ (typ.) ±30% No.7307-7/18 STK672-070-E Input Signal Functions and Timing • CLK (phase switching clock) 1) Input frequency range: DC to 50kHz 2) Minimum pulse width: 10μs 3) Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.) 4) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 5) Built-in multi-stage noise rejection circuit 6) Function: - When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge. - When M3 is low: The phase is advanced one step by both rising and falling edges, for a total of two steps per cycle. CLK Input Acquisition Timing (M3 = Low) CLK input System clock Phase excitation counter clock Excitation counter up/down Control output timing Control output switching timing A13264 • CWB (Method for setting the rotation direction) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When CWB is low: The motor turns in the clockwise direction. - When CWB is high: The motor turns in the counterclockwise direction. 3) Notes: When M3 is low, the CWB input must not be changed for about 6.25μs before or after a rising or falling edge on the CLK input. • ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold as the internal state of this hybrid IC.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When ENABLE is high or open: Normal operating state - When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the reset input have any effect on the hybrid IC state. No.7307-8/18 STK672-070-E • M1, M2, and M3 (Excitation mode and CLK input edge timing selection) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 Phase switching clock edge timing 1 2W1-2 phase excitation 4W1-2 phase excitation Rising edge only Rising and falling edges 3) Valid mode setting timing: Applications must not change the mode in the period 5μs before or after a CLK signal rising or falling edge. Mode Setting Acquisition Timing CLK input System clock Mode setting M1 to M3 Mode switching clock Mode switching timing Hybrid IC internal setting state Phase excitation clock Excitation counter up/down A13265 • RESET (Resets all parts of the system.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at least 10μs.) At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to about 71% after the reset is released. 3) Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must apply a power on reset when the VCC2 power supply is first applied. • Vref (Sets the current level used as the reference for constant-current detection.) 1) Pin circuit type: Analog input structure 2) Function: - Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage VCC2 minus 2.5V. - Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5V as the upper limit. Output Pin Functions Pin No. 14 Symbol MOI Function Phase excitation origin monitor Pin circuit type Standard CMOS structure Output Signal Functions and Timing • A, A, B, and B (Motor phase excitation outputs) 1) Function: - In the 4 phase and 2 phase excitation modes, a 3.75μs (typical) interval is set up between the A and A and B and B output signal transition times. No.7307-9/18 STK672-070-E Phase States During Excitation Switching • Excitation phases before and after excitation mode switching 2W1-2 phase → 2 phase A 0 1 28 27 25 B 24 20 8B 12 9 20 17 19 16 A 16 A W1-2 phase → 1-2 phase 30 4 28 B 24 20 22 20 18 16 A 1-2 phase → 2 phase A 0 28 28 20 20 16 A 2 phase → 1-2 phase A 0 4 B 12 12 18 A 2 phase → W1-2 phase A 30 6 B 24 28 20 4 12 8B 22 B 28 20 4 12 B 21 16 A A 14 13 17 A B 20 29 5 28 4 12 B 14 8B 22 4 26 0 28 20 4 6 B 12 16 B 10 21 13 17 A 2 phase → 2W1-2 phase A 25 28 0 4 24 8 20 12 16 B 9 14 8B 12 12 10 22 20 18 16 A 1-2 phase → W1-2 phase A 30 2 29 14 6 4 28 26 B 24 A 0 2 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 23 21 19 17 A 1-2 phase → 2W1-2 phase A 1 5 15 13 27 25 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 2W1-2 phase → 1-2 phase 31 A 3 28 0 4 8 24 20 16 12 4 5 8B 11 12 2W1-2 phase → W1-2 phase A 30 31 0 1 2 3 29 4 28 5 27 30 0 2 26 6 28 4 25 26 7 6 B 24 24 8 8B 22 10 23 20 9 1816 1412 22 10 11 21 12 20 13 19 18 17 161514 A W1-2 phase → 2W1-2 phase A 29 31 1 3 5 7 B 9 11 28 4 B 24 15 W1-2 phase → 2 phase 30 28 26 A 0 2 B 24 Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 and M2) Excitation phase immediately before setting the excitation mode A13266 No.7307-10/18 STK672-070-E • Excitation phases before and after excitation mode switching 2W1-2 phase → 2 phase 31 A 0 28 28 B 24 23 20 8B 12 21 20 16 A W1-2 phase → 2 phase 30 A 0 28 28 B 24 20 22 8B 12 22 20 16 A 1-2 phase → 2 phase A 0 28 28 20 20 16 A 2 phase →1-2 phase A 0 4 B 12 12 18 A 2 phase → W1-2 phase A 2 3 27 B 24 28 20 4 12 8B 26 B 28 20 4 12 B 10 19 A A A13267 2W1-2 phase → 1-2 phase A 01 4 5 28 0 4 8 24 20 16 12 13 12 8B 9 2W1-2 phase → W1-2 phase A 30 31 0 1 2 3 29 4 28 5 27 30 0 2 26 6 28 4 25 26 7 6 B 24 24 8 8B 22 10 23 20 9 1816 1412 22 10 11 21 20 12 13 19 18 17 161514 A W1-2 phase → 2W1-2 phase A 31 1 3 5 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 29 4 7 25 B 24 15 1716 A W1-2 phase → 1-2 phase 30 6 A 02 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 18 16 A 1-2 phase → W1-2 phase A 30 2 14 29 27 25 4 26 B 24 7 B 9 11 13 23 21 19 14 17 A 15 1-2 phase → 2W1-2 phase A 30 27 B B 3 4 26 8B 22 28 0 4 24 20 16 12 10 14 6 28 0 4 24 8 20 12 16 B 24 7 B 11 23 19 A 15 2 phase → 2W1-2 phase A B 28 20 4 12 11 B 16 A 18 No.7307-11/18 STK672-070-E Excitation Time and Timing Charts • CLK rising edge operation 2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 1 M3 0 1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 RESET CWB MOSFET Gate Signal MOSFET Gate Signal 1 1 RESET CWB MOSFET Gate Signal CLK A A B B CLK A A B B MOI 100% 71% Comparator Reterence Voltage Comparator Reterence Voltage MOI 100% 71% Vref A 100% 71% Vref A 100% 71% Vref B Vref B W1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 RESET CWB CLK A A B B MOI 100% 92% 71% Comparator Reterence Voltage Comparator Reterence Voltage MOSFET Gate Signal 2W1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 RESET CWB CLK A A B B MOI 100% 92% 83% 71% 55% 40% 20% 1 1 1 1 1 40% Vref A 100% 92% 71% 40% Vref A 100% 92% 83% 71% 55% 40% 20% Vref B Vref B A13268 No.7307-12/18 STK672-070-E • CLK rising and falling edge operation 1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB MOSFET Gate Signal W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB MOSFET Gate Signal MOSFET Gate Signal 1 CLK A A B B MOI 100% 71% CLK A A B B MOI 100% 92% 71% Comparator Reterence Voltage Comparator Reterence Voltage 40% Vref A 100% 71% Vref A 100% 92% 71% 40% Vref B Vref B 2W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB CLK A A B B MOI 100% 92% 83% 71% 55% 40% MOSFET Gate Signal 4W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB CLK A A B B MOI 100% 97% 92% 88% 77% 83% 71% 66% 55% 48% 40% 31% 14% 20% 1 1 1 Comparator Reterence Voltage Vref A 20% Comparator Reterence Voltage Vref A 100% 92% 83% 71% 55% 40% Vref B 20% 100% 97% 92% 88% 77% 83% 66% 71% 48% 55% 40% 31% 14% 20% Vref B A13269 No.7307-13/18 STK672-070-E Thermal Design The main elements internal to this hybrid IC with large average power losses are the current control devices, the regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2 phase excitation. The losses in the various excitation modes are as follows. 2 phase excitation ·fclock I Pd2EX = (Vsat+Vdf) · fclock · IOH · t2 + OH · (Vsat · t1+Vdf · t3) 2 2 Pd1-2EX = 0.64 · {(Vsat+Vdf) · 1-2 phase excitation ·fclock I fclock · IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 4 4 ·fclock I fclock ·IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 8 8 W1-2 phase excitation PdW1-2EX = 0.64 · {(Vsat+Vdf) · ·fclock I 2W1-2 phase excitation Pd2W1-2EX = 0.64 · {(Vsat+Vdf) · fclock ·IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 16 16 4W1-2 phase excitation Pd4W1-2EX = 0.64 · {(Vsat+Vdf) · I OH ·fclock fclock ·IOH · t2 + · (Vsat · t1+Vdf · t3)} 16 16 Here, t1 and t3 can be determined from the same formulas for all excitation methods. −L · n (1 – R + 0.35 · IOH) R + 0.35 VCC 1 t1 = VCC 1 + 0.35 t3 = − L · n ( ) R I OH ·R + VCC 1 + 0.35 However, the formula for t2 differs with the excitation method. 2 phase excitation t2 = 2 fclock – (t1+t3) 1-2 phase excitation t2 = 3 fclock – t1 W1-2 phase excitation t2 = 7 – t1 fclock 2W1-2 phase excitation 4W1-2 phase excitation t2 = 15 – t1 fclock IOH t3 t1 t2 A13270 Motor Phase Current Model Figure (2 Phase Excitation) fclock Vsat Vdf IOH t1 t2 t3 : CLK input frequency (Hz) : The voltage drop of the power MOSFET and the current detection resistor (V) : The voltage drop of the body diode and the current detection resistor (V) : Phase current peak value (A) : Phase current rise time (s) VCC1 : Supply voltage applied to the motor (V) : Constant-current operating time (s) L : Motor inductance (H) : Phase switching current regeneration time (s) R : Motor winding resistance (Ω) No.7307-14/18 STK672-070-E Determine θc-a for the heat sink from the average power loss determined in the previous item. Tc max: Hybrid IC substrate temperature (°C) Tc max - Ta [°C/W] θc-a = Ta: Application internal temperature (°C) Pd EX PdEX: Hybrid IC internal average loss (W) Determine θc-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below. The ambient temperature of the device will vary greatly according to the air flow conditions within the application. Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum plate side) will never exceed a Tc max of 105°C, whatever the operating conditions are. 20 θc-a - Pd Heat sink thermal resistance, θc-a - °C/W Heat sink thermal resistance, θc-a - °C/W θc-a= Tc max -- Ta (°C/W) Pd Tc max=105°C bie am ed nte ure ara rat Gu mpe te 2 θc-a - S 2m mA l pl at e (fla t bl ack 16 10 7 5 (no Vertical standing type Natural convection air cooling sur f ace fin ish ) ) 12 sur fac 8 60 °C 4 40° C 3 e fi nis h 50°C nt 2 0 0 No. Fin 25.5 (°C/W) 2 4 6 8 10 12 14 16 1.0 No. Fin 25.5 (°C/W) 10 2 3 5 7 100 2 3 5 IC internal average power loss, Pd - W Heat sink surface area, S - cm2 Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss from the thermal resistance of the hybrid IC substrate, namely 25.5°C/W. For a Tc max of 105°C at an ambient temperature of 50°C PdEX = 100 - 50 = 2.15W 25.5 PdEX = 100 - 40 = 2.54W 25.5 For a Tc max of 105°C at an ambient temperature of 40°C This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (See ΔTc – Pd curve in the graph on page 17.) The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal resistance θj-c. Tj = Tc + θj-c × Pds (°C) Here, we determine Pds, the loss for each transistor, by determining PdEX in each excitation mode. Pds = PdEX/4 The steady-state thermal resistance θj-c of a power MOSFET is 19.2°C/W. No.7307-15/18 STK672-070-E 55 53 51 fc - VCC2 55 53 51 fc - Tc PWM frequency, fc - kHz 49 47 45 43 41 39 37 35 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 PWM frequency, fc - kHz 49 47 45 43 41 39 37 35 0 20 40 60 80 100 120 ITF02184 Supply voltage, VCC2 - V 2.5 ITF02183 1.8 Substrate temperature, Tc - °C Vsat - IOH Vdf - IOH Internal diode forward voltage, Vdf - V Output saturation voltage, Vsat - V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.0 1.5 C 25° Tc= °C 105 1.0 C 5° 10 = °C Tc 25 0.5 0 0 0.5 1.0 1.5 2.0 2.5 ITF02185 0 0.5 1.0 1.5 2.0 2.5 ITF02186 Motor current, IOH - A 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 IOH - VCC1 Motor current, IOH - A 1.4 IOH - Tc Test motor: PK244-01B Test motor: PK244-01B 1.2 Motor current, IOH - A Motor current, IOH - A 15 20 25 30 35 40 45 50 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 ITF02188 Motor supply voltage, VCC1 - V ITF02187 450 Substrate temperature, Tc - °C IVref - Vref 450 IVref - Tc Reference voltage input current, IVref - μA Reference voltage input current, IVref - μA 400 350 300 250 200 150 100 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ITF02189 400 350 Vref=2.0V 300 250 200 Vref=1.5V Vref=1.0V 150 100 50 0 0 20 40 60 80 100 120 ITF02190 Vref=0.5V Reference voltage, Vref - V Substrate temperature, Tc - °C No.7307-16/18 STK672-070-E 2.0 1.8 Vref - IOH Substrate temperature increase, ΔTc - °C Test motor: PK244-01B VCC1=24V 90 80 70 60 50 40 30 20 10 0 ΔTc - Pd Reference voltage, Vref - V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 15 20 25 30 35 40 45 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 Substrate Temperature Rise Test Test motor: PK264-01B VCC1=24V, VCC2=5V IOH=1A (with no heat sink) Motor current, IOH - V ITF02191 2.5 Hybrid IC internal average power dissipation, Pd - W ITF02192 Motor Current IOH Derating vs. Operating Substrate Temperature Tc. Substrate temprature increase, ΔTc - °C 35 2.0 2ex 25 20 15 Motor current, IOH - A 57 100000 30 1.5 1.0 4W 10 5 0 100 ex 1-2 0.5 0 2 3 5 7 1000 2 3 5 7 10000 2 3 0 20 40 60 80 100 120 ITF02194 CLK frequency, PPS - Hz ITF02193 Substrate temprature, Tc - °C Notes • The current ranges shown above apply when the output voltage is not in the avalanche range. • The operating substrate temperature Tc values shown above are measured during motor operation. Since Tc varies with the ambient temperature Ta, the value of IOH, and whether IOH is continuous or intermittent, it must be measured in an actual operating system. No.7307-17/18 STK672-070-E SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2008. Specifications and information herein are subject to change without notice. PS No.7307-18/18