STK672-440A-E_11

Ordering number : ENA1128B STK672-440A-E Overview Thick-Film Hybrid IC 2-phase Stepping Motor Driver The STK672-440A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control. Applications • Office photocopiers, printers, etc. Features • Built-in overcurrent detection function (output current OFF). • Built-in overheat detection function (output current OFF). • If either over-current or overheat detection function is activated, the FAULT1 signal (active low) is output. The FAULT2 signal is used to output the result of activation of protection circuit detection at 2 levels. • Built-in power on reset function. • A micro-step sine wave-driven driver can be activated merely by inputting an external clock. • External pins can be used to select 2, 1-2 (including pseudo-micro), W1-2, 2 W1-2, or 4W1-2 excitation. • The switch timing of the 4-phase distributor can be switched by setting an external pin (MODE3) to detect either the rise and fall, or rise only, of CLOCK input. • Phase is maintained even when the excitation mode is switched. Rotational direction switching function. • Supports schmitt input for 2.5V high level input. • Incorporating a current detection resistor (0.122Ω: resistor tolerance ±2%), motor current can be set using two external resistors. • The ENABLE pin can be used to cut output current while maintaining the excitation mode. • With a wide current setting range, power consumption can be reduced during standby. • No motor sound is generated during hold mode due to external excitation current control. • A external excitation system is used for PWM operations. Fixed current control for shifting the phase of Ach/Bch is used for the PWM phase. 62911HKPC 018-08-0074/N2509HKIM/71608HKIM No.A1128-1/21 STK672-440A-E Specifications Absolute Maximum Ratings at Tc = 25°C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Input voltage Output current 1 Output current 2 Allowable power dissipation 1 Allowable power dissipation 2 Operating substrate temperature Junction temperature Storage temperature Symbol VCC max VDD max VIN max IOP max IOH max PdMF max PdPK max Tc max Tj max Tstg No signal No signal Logic input pins 10µs, 1 pulse (resistance load) VDD=5V, CLOCK≥200Hz With an arbitrarily large heat sink. Per MOSFET No heat sink Conditions Ratings 52 -0.3 to +6.0 -0.3 to +6.0 20 3.5 8.3 3.1 105 150 -40 to +125 unit V V V A A W W °C °C °C Allowable Operating Ranges at Ta=25°C Parameter Operating supply voltage 1 Operating supply voltage 2 Input high voltage Input low voltage Output current CLOCK frequency Phase driver withstand voltage Recommended operating substrate temperature Recommended Vref range Vref Tc=105°C Symbol VCC VDD VIH VIL IOH fCL VDSS Tc With signals applied With signals applied Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17 Tc=105°C, CLOCK≥200Hz Minimum pulse width: at least 10µs ID=1mA (Tc=25°C) No condensation Conditions Ratings 10 to 42 5±5% 2.5 to VDD 0 to 0.8 3.0 0 to 50 100min 0 to 105 0.2 to 1.8 unit V V V V A kHz V °C V Electrical Characteristics at Tc=25°C, VCC=24V, VDD=5.0V *1 Parameter VDD supply current Output average current *2 FET diode forward voltage Output saturation voltage Control input pin 5V level input current GND level input current Vref input bias current FAULT1 pin Output low voltage 5V level leakage current FAULT2 pin Overcurrent detection output voltage Overheat detection output voltage Overheat detection temperature PWM frequency TSD fc Design guarantee 41 144 48 55 °C kHz VOF3 3.1 3.3 3.5 VOF2 Input voltage Symbol ICCO Ioave Vdf Vsat VIH VIL IILH IILL IIB VOLF IILF Conditions VDD=5.0V, ENABLE=Low R/L=1Ω/0.62mH in each phase If=1A (RL=23Ω) RL=23Ω Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17=5V Pins 10, 11, 12, 13, 14, 15, 17=GND Pin 19 =1.0V Pin 16 (IO=5mA) Pin 16 =5V Pin 8 (when all protection functions have been activated) 2.4 2.5 2.6 V 10 0.25 2.5 -0.3 50 0.27 min typ 5.7 0.32 1 0.25 max 7.0 0.37 1.6 0.38 VDD 0.8 75 10 15 0.5 10 unit mA A V V V V µA µA µA V µA Notes *1: A fixed-voltage power supply must be used. *2: The value for Ioave assumes that the lead frame of the product is soldered to the mounting circuit board. Continued on next page. No.A1128-2/21 STK672-440A-E Continued from preceding page. Parameter 4W1-2 4W1-2 4W1-2 4W1-2 A€ B Chopper Current Ratio 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 2 2W1-2 2W1-2 W1-2 2W1-2 2W1-2 W1-2 1-2 Vref *3 2W1-2 2W1-2 W1-2 2W1-2 2W1-2 W1-2 1-2 Symbol =15/16, 16/16 =14/16 =13/16 =12/16 =11/16 =10/16 =9/16 =8/16 =7/16 =6/16 =5/16 =4/16 =3/16 =2/16 =1/16 Conditions min typ 100 97 95 93 87 83 77 71 64 55 47 40 30 20 11 100 % max unit Notes *3: The values given for Vref are design targets, no measurement is performed. Package Dimensions unit:mm (typ) 29.2 25.6 (20.47) 2.0 4.5 (12.9) (5.0) (5.0) (R1.7) 11.0 14.5 14.4 7.2 1 19 (3.5) 1.0 (5.6) 18 1.0=18.0 0.52 4.2 0.4 8.2 (20.4) 14.5 No.A1128-3/21 STK672-440A-E Derating Curve of Motor Current, IOH, vs. STK672-440A-E Operating Substrate Temperature, Tc 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 90 100 110 ITF02574 IOH - Tc 200Hz 2 phase excitation Hold mode Motor current, IOH - A Operating Substrate Temperature, Tc- °C Notes • The current range given above represents conditions when output voltage is not in the avalanche state. • If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-4** series hybrid ICs given in a separate document. • The operating substrate temperature, Tc, given above is measured while the motor is operating. Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent operation of IOH, always verify this value using an actual set. No.A1128-4/21 R02 ENABLE FAULT2 FAULT1 S.G P STK672-440A-E Block Diagram VDD 9 MOI FAULT2 Vref 7 19 8 A 4 AB 5 B 3 BB 1 MODE1 10 MODE2 11 CWB 13 Excitation mode selection Rising edge / falling edge detection CLOCK 12 Phase advance counter Current divider ratio switching - + Pseudo sine wave generator MODE3 17 RESETB 14 Power-on reset Phase excitation signal generator Overcurrent detection ENABLE 15 Latch Overheating detection Oscillator Reference clock generator - PWM control + + FAULT1 16 2 P.G1 6 P.G2 S.G 18 SUB Sample Application Circuit No.A1128-5/21 STK672-440A-E Precautions [GND wiring] • To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as possible to Pin 2 and Pin 6 of the hybrid IC. In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2. [Input pins] • When VDD is being input, for each input pin, measures must be taken so that a negative voltage less than -0.3V is not applied to Pin 18. Measures must also be taken so that a voltage equal to or greater than VDD is not input. • High voltage input other than VDD, MOI, FAULT1, and FAULT2 is 2.5V. • Pull-up resistors are not connected to input pins. Pull-down resistors are attached. When controlling the input to the hybrid IC with the open collector type, be sure to connect a pull-up resistor (1 to 20kΩ). Be sure to use a device (0.8V or less, low level, when IOL=5mA) for the open collector driver at this time that has an output voltage specification such that voltage is pulled to less than 0.8V at low level. • When using the power on reset function built into the hybrid IC, be sure to directly connect Pin 14 to VDD. • We recommend attaching a 1,000pF capacitor to each input to prevent malfunction during high-impedance input. Be sure to connect the capacitor near the hybrid IC, between Pin 18 (S, G). When input is fixed low, directly connect to Pin 18. When input is fixed high, directly connect to VDD. [Current setting Vref] • We recommend a resistance of 1kΩ or less for RO2 to reduce the effect of input bias current to the Vref pin. • If the motor current is temporarily reduced, the circuit given below is recommended. The variable voltage range of Vref input is 0.2 to 1.8V. [Setting the motor current] The motor current, IOH, is set using the Pin 19 voltage, Vref, of the hybrid IC. Equations related to IOH and Vref are given below. Vref ≈ (RO2 ÷ (RO2+RO1))×VDD(5V) ························································· (1) IOH ≈ (Vref ÷ 4.9) ÷ Rs ·················································································· (2) The value of 4.9 in Equation (2) above represents the Vref voltage as divided by a circuit inside the control IC. Rs: 0.122Ω (Current detection resistor inside the hybrid IC) No.A1128-6/21 STK672-440A-E • Motor current peak value IOH setting IOH 0 [Smoke Emission Precuations] If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at VCCON (24V ON), causing the STK672-440A-E to emit smoke because 5V circuits cannot be controlled. In addition, as long as one of the output Pins, 1, 3, 4, or 5, is open, inductance energy stored in the motor results in electrical stress on the driver, possibly resulting in the emission of smoke. Function Table M2 M1 M3 1 0 0 2-phase excitation selection 1-2 phase excitation (IOH=100%, 71%) 0 1 1-2-phase excitation (IOH=100%) W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 1 2W1-2 phase excitation 4W1-2 phase excitation CLOCK Edge Timing for Phase Switching CLOCK rising edge 0 CLOCK both edges IOH=100% results in the Vref voltage setting, IOH. During 1-2 phase excitation, the hybrid IC operates at a current setting of IOH=100% when the CLOCK signal rises. Conversely, pseudo micro current control is performed to control current at IOH=100% or 71% at both edges of the CLOCK signal. CWB pin Forward/CW Reverse/CCW 0 1 ENABLE • RESETB pin ENABLE RESETB Motor current cut: Low Active Low No.A1128-7/21 STK672-440A-E Timing Charts 2-phase excitation timing charts (M3=1) M1 M2 M3 RESET 0 0 1 0 1-2-phase excitation timing charts (M3=1) C 1 0 %100%71% 1 B VrefVref CWB MOSFET Gate Signal Comparator Reference Voltage CLK A A B B MOI 100% 71% A phase Vref 100% 71% Vref W1-2-phase excitation timing charts (M3=1) M1 M2 M3 RESET CWB CLK A A B 2W1-2-phase excitation timing charts (M3=1) 0 1 0 1 0 Comparator Reference Voltage 100% 92% 71% 40% Vref 100% 92% 71% 40% Vref No.A1128-8/21 1 STK672-440A-E 1-2-phase excitation timing charts (M3=0) M1 M2 M3 RESET CWB MOSFET Gate Signal 0 0 0 W1-2-phase excitation timing charts (M3=0) CLK A A B B MOI 100% Comparator Reference Voltage 71% A phase Vref 100% 71% A phase B phase Vref B phase 2W1-2-phase excitation timing charts (M3=0) 4W1-2-phase excitation timing charts (M3=0) A phase A phase B phase B phase No.A1128-9/21 Comparator 1 M I C B omparator Reference Voltage T1 1 FM 0 02 0 2M % 53 8 5 MOSFET Gate Signal STK672-440A-E Usage Notes 1. I/O Pins and Functions of the Control Block [Pin description] HIC pin 7 Pin Name MOI Function No.A1128-10/21 STK672-440A-E [Vref (Voltage setting to be used for the current setting reference)] • Pin type: Analog input configuration, input pull-down resistor 100kΩ Input voltage is in the voltage range of 0.2V to 1.8V. [Input timing] The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate voltage is 5V±5%, conduction of current to output at the time of power on reset adds electromotive stress to the MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD, which is outside the operating supply voltage, is less than 4.75V. In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10µs until CLOCK input. 4Vtyp Control IC power (VDD) rising edge Control IC power on reset 3.8Vtyp RESETB signal input No time specification ENABLE signal input CLOCK signal input At least 10µs At least 10µs ENABLE, CLOCK, and RESETB Signals Input Timing [Configuration of control block I/O pins] The input pins of this driver all use Schmitt input. Typical specifications at Tc=25°C are given below. Hysteresis voltage is 0.3V (VIHa-VILa). RESETB No.A1128-11/21 STK672-440A-E Input voltage specifications are as follows. VIH=2.5Vmin VIL=0.8Vmax 5V Vref/4.9 + Amplifier 100kΩ VSS VSS Input pin Pin 19 Thermal shutdown VSS (The buffer has an open drain configuration.) Output pin Pin 16 Overcurrent FAULT1 Output FAULT1 is an open drain output. Low is output if either overcurrent or overheating is detected. FAULT2 output Output is resistance divided (2 levels) and the type of abnormality detected is converted to the corresponding output voltage. • Overcurrent: 2.5V(typ) • Overheat: 3.3V(typ) Abnormality detection can be released by a RESETB operation or turning VDD voltage on/off. [MOI output] The output frequency of this excitation monitor pin varies depending on the excitation mode. For output operations, see the timing chart. No.A1128-12/21 STK672-440A-E 2. Overcurrent Detection and Overheat Detection Functions of the STK672-430A-E and 440A-E Each detection function operates using a latch system and turns output off. Because a RESET signal is required to restore output operations, once the power supply, VDD, is turned off, you must either again apply power on reset with VDDON or apply a RESETB=High→Low→High signal. [Overcurrent detection] This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there is a short between the motor terminals. Overcurrent detection occurs at 3.4A typ with the STK672-430A-E and at 5.0A typ for the STK672-440A-E. Overcurrent detection begins after an interval of no detection (a dead time of 1.25µs typ) during the initial ringing part No.A1128-13/21 STK672-440A-E 3. STK672-440A-E Allowable Avalanche Energy Value (1) Allowable Range in Avalanche Mode When driving a 2-phase stepping motor with constant current chopping using an STK672-4** Series hybrid IC, the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-4** Series when Driving a 2Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-4** Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (3-1). EAVL1=VDSS×IAVL×0.5×tAVL ------------------------------------------- (3-1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (3-1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-4** Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (3-2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (3-1). PAVL=VDSS×IAVL×0.5×tAVL×fc ------------------------------------------- (3-2) fc: Hz units (fc is set to the PWM frequency of 50kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-4** Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=1A, tAVL=0.2µs when using a STK672-440A-E driver, the result is: PAVL=110×1×0.5×0.2×10-6×50×103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (3-2) falls within the allowable range for avalanche operations. No.A1128-14/21 STK672-440A-E 4. Calculating STK672-440A-E HIC Internal Power Loss The average internal power loss in each excitation mode of the STK672-440A-E can be calculated from the following formulas. *1 [Each excitation mode] 2-phase excitation mode 2PdAVex= (Vsat+Vdf) ×0.5×CLOCK×IOH×t2+0.5×CLOCK×IOH× (Vsat×t1+Vdf×t3) --------------------------- (4-1) 1-2 Phase excitation mode 1-2PdAVex= (Vsat+Vdf) ×0.25×CLOCK×IOH×t2+0.25×CLOCK×IOH× (Vsat×t1+Vdf×t3) ---------------------- (4-2) W1-2 Phase excitation mode W1-2PdAVex=0.64[(Vsat+Vdf) ×0.125×CLOCK×IOH×t2+0.125×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ---------- (4-3) 2W1-2 Phase excitation mode 2W1-2PdAVex=0.64[(Vsat+Vdf) ×0.0625×CLOCK×IOH×t2+0.0625×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ------ (4-4) 4W1-2 Phase excitation mode 4W1-2PdAVex=0.64[(Vsat+Vdf) ×0.0625×CLOCK×IOH×t2+0.0625×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ------ (4-5) Motor hold mode HoldPdAVex= (Vsat+Vdf) ×IOH---------------------------------------------------------------------------------------------- (4-6) Note: 2-phase 100% conductance is assumed in Equation (4-6). Vsat: Combined voltage of Ron voltage drop + current detection resistance Vdf: Combined voltage of the FET body diode + current detection resistance *1 CLOCK: Input CLOCK (HIC: input frequency at Pin 12) *1 Although a synchronous rectification system is used, substitute using the value of Vdf, while taking design margins into account. t1, t2, and t3 represent the waveforms shown in the figure below. t1: Time required for the winding current to reach the set current (IOH) t2: Time in the constant current control (PWM) region t3: Time from end of phase input signal until inverse current regeneration is complete IOH 0A Motor COM Current Waveform Model t1= (-L/(R+0.25)) In (1-(((R+0.25)/VCC) ×IOH)) --------------------------------------------------------------- (4-7) t3= (-L/R) In ((VCC+1)/(IOH×R+VCC+1)) --------------------------------------------------------------------- (4-8) VCC: Motor supply voltage (V) L: Motor inductance (H) R: Motor winding resistance (Ω) IOH: Motor set output current crest value (A) No.A1128-16/21 STK672-440A-E Fixed current control time, t2, for each excitation mode (1) 2-phase excitation (2) 1-2 phase excitation (3) W1-2 phase excitation (4) 2W1-2 phase excitation (and 4W1-2 phase excitation) t2 = (2÷CLOCK) - (t1 + t3)·······························(4-9) t2 = (3÷CLOCK) - t1·········································(4-10) t2 = (7÷CLOCK) - t1·········································(4-11) t2 = (15÷CLOCK) - t1·······································(4-12) For the values of Vsat and Vdf, be sure to substitute from Vsat vs IOH and Vdf vs IOH at the setting current value IOH. (See pages to follow) Then, determine if a heat sink is necessary by comparing with the ∆Tc vs Pd graph (see next page) based on the calculated average output loss, HIC. For heat sink design, be sure to see STK672-440A-E. The HIC average power, PdAVex described above, represents loss when not in avalanche mode. To add the loss in avalanche mode, be sure to add PAVL (4-13, 14) using the formula (3-2) for average power loss , PAVL, for STK6724** avalanche mode, described below to PdAVex described above. When using this IC without a fin, always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of convection around the HIC. [Calculating the average power loss, PAVL, during avalanche mode] The allowable avalanche energy, EAVL, during fixed current chopping operation is represented by Equation (3-2) used to find the average power loss, PAVL, during avalanche mode that is calculated by multiplying Equation (3-1) by the chopping frequency. PAVL=VDSS×IAVL×0.5×tAVL×fc······································································································(3-2) fc: Hz units (input MAX PWM frequency when using the STK672-4** series.) Be sure to actually operate an STK672-4** series and substitute values found when observing operations on an oscilloscope for VDSS, IAVL, and tAVL. The sum of PAVL values for each excitation mode is multiplied by the constants given below and added to the average internal HIC loss equation, except in the case of 2-phase excitation. 1-2 excitation mode and higher: PAVL(1)=0.7×PAVL ···································································· (4-13) During 2-phase excitation and motor hold: PAVL(1)=1×PAVL······················································· (4-14) No.A1128-17/21 STK672-440A-E STK672-440A-E Output saturation voltage, Vsat - Output current, IOH 1.2 Vsat - IOH Output saturation voltage, Vsat - V 1.0 0.8 0.6 C 5° 10 = Tc °C 25 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ITF02576 Output current, IOH - A STK672-440A-E Forward voltage, Vdf -Output current, IOH 1.6 1.4 Vdf- IOH Forward voltage, Vdf - V 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 C 25° T c= °C 105 2.0 2.5 3.0 3.5 4.0 4.5 ITF02577 Output current, IOH - A Substrate temperature rise, ∆Tc (no heat sink) - Internal average power dissipation, PdAV ∆Tc - PdAV 80 70 60 50 40 30 20 10 0 0 0.5 1.0 Substrate temperature rise, ∆Tc - °C 1.5 2.0 2.5 3.0 3.5 ITF02578 Hybrid IC internal average power dissipation, PdAV - W No.A1128-18/21 STK672-440A-E 5. Thermal design [Operating range in which a heat sink is not used] Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the quality of the HIC. The size of heae No.A1128-19/21 STK672-440A-E Figure 2 Substrate temperature rise, ∆Tc - Internal average power dissipation, PdAV 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ITF02578 ∆Tc - PdAV Substrate temperature rise, ∆Tc - °C Hybrid IC internal average power dissipation, PdAV - W Figure 3 Heat sink area (Board thickness: 2mm) - θc-a 100 θc-a - S Heat sink thermal resistance, θc-a - °C/W 7 5 3 2 10 7 5 3 2 Wi t hn Wit o su ha flat rfac e fi blac k su nish rfac e f i ni sh 1.0 10 2 3 5 7 100 2 3 5 7 1000 ITF02554 Heat sink area, S - cm2 No.A1128-20/21 STK672-440A-E 6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink. The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta. Power loss of up to 3.1W is allowable at Ta=25°C, and of up to 1.75W at Ta=60°C. Allowable power dissipation, PdPK (no pe woewi No.A1128-21/21