Ordering number : ENA0143
ENA1951
LC87F5DC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
http://onsemi.com
Overview
The LC87F5DC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3 ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard rewritable),
4K-byte RAM, onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports
(with automatic block transmission/reception capabilities),an asynchronous/synchronous SIO port, two UART ports
(full duplex), four 12-bit PWM channels, an 8-bit 15-channel AD converter, a high-speed clock counter, a system
clock frequency divider, and a 29-source 10-vector interrupt feature.
Features
Flash ROM
• Single 5V power supply, on-board writeable
• Block erase in 128 byte units
• 131072 × 8 bits (LC87F5DC8A)
RAM
• 4096 × 9 bits (LC87F5DC8A)
Bus Cycle Time
• 83.3ns (12MHz)
Note: Bus cycle time indicates the speed to read ROM.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.04
N0712HKIM 20060117-S00009 No.A0143-1/28
LC87F5DC8A
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
62 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
8 (VSS1 to VSS4, VDD1 to VDD4)
Timers
• Timer 0: 16-bit timer/counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2-channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with 2 16-bit capture registers)
• Timer 1: 16-bit timer/counter that support PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
• Can generate output real-time.
Serial interface
• SIO0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits)
• SIO1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 Tcyc)
3) Automatic continuous data transmission (1 to 32 bytes)
No.A0143-2/28
LC87F5DC8A
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bits in continuous transmission mode)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 15 channels
PWM: Multifrequency 12-bit PWM × 4 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
• The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector
Selectable Level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO1/SIO2/UART1 transmit/UART2
transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels maximum (the stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
• Multifrequency RC oscillation circuit (internal):
For system clock
For system clock, with internal Rf
For low-speed system clock
For system clock
No.A0143-3/28
LC87F5DC8A
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(3) Having an interrupt source established at port 0.
(4) Having an interrupt source established in the base timer circuit.
On-chip debugging function
• Permits software debugging with the test device installed on the target board.
Shipping Form
• QIP80E (14×20): Lead-free type
• TQFP80J (12×12): Lead-free type
Development Tools
• Evaluation (EVA) chip:
• Emulator:
• Flash ROM writer adapter:
LC87EV690
EVA62S + ECB876600D + SUB875D00 + POD80QFP or POD80SQFP
ICE-B877300 + SUB875D00 + POD80QFP or POD80SQFP
W87F54256Q(QIP80E), W87F54256SQ(TQFP80)
No.A0143-4/28
LC87F5DC8A
Package Dimensions
unit : mm (typ)
3174A
64
0.8
23.2
20.0
41
65
80
17.2
14.0
40
25
24
1
0.15
0.35
0.8
(2.7)
0.1
3.0max
(0.8)
SANYO : QIP80E(14X20)
Package Dimensions
unit : mm (typ)
3290
14.0
41
40
80
21
12.0
61
1
20
0.5
0.2
14.0
60
0.5
12.0
0.125
0.1
1.2max
(1.0)
(1.25)
SANYO : TQFP80J(12X12)
No.A0143-5/28
PB4
PB3
PB2
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
PA0
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PA1
PA2
PA3/AN12
PA4/AN13
PA5/AN14
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
PB5
PB6
PB7
P27/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P25/INT5/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1
P23/INT4/T1IN/T0LCP/T0HCP/URX2
P22/INT4/T1IN/T0LCP/T0HCP/UTX2
P21/INT4/T1IN/T0LCP/T0HCP
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1
P07/T7O
P06/T6O
P05/CKO
P04
P03
P02
P01
P00
VSS2
VDD2
PWM0
PWM1
SI2P3/SCK20
LC87F5DC8A
Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LC87F5DC8A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SI2P2/SCK2
SI2P1/SI2/SB2
SI2P0/DO2
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P34
P33/URX1
P32/UTX1
P31/PWM5
P30/PWM4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Top view
QIP80E (14×20) “Lead-free Type”
No.A0143-6/28
PB7
P27/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P25/INT5/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1
P23/INT4/T1IN/T0LCP/T0HCP/URX2
P22/INT4/T1IN/T0LCP/T0HCP/UTX2
P21/INT4/T1IN/T0LCP/T0HCP
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1
P07/T7O
P06/T6O
P05/CKO
P04
P03
P02
P01
P00
VSS2
VDD2
PWM0
LC87F5DC8A
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
LC87F5DC8A
PWM1
SI2P3/SCK20
SI2P2/SCK2
SI2P1/SI2/SB2
SI2P0/SO2
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P34
P33/URX1
P32/UTX1
P31/PWM5
P30/PWM4
P87/AN7
P86/AN6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PA3/AN12
PA4/AN13
PA5/AN14
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
Top view
TQFP80J (12×12) “Lead-free Type”
No.A0143-7/28
LC87F5DC8A
QIP
NAME
TQFP
QIP
NAME
TQFP
1
PA1
79
41
SI2P3/SCK20
2
PA2
80
42
PWM1
40
3
PA3/AN12
1
43
PWM0
41
4
PA4/AN13
2
44
VDD2
42
5
PA5/AN14
3
45
VSS2
43
6
P70/INT0/T0LCP/AN8
4
46
P00
44
7
P71/INT1/T0HCP/AN9
5
47
P01
45
8
P72/INT2/T0IN/T0LCP
6
48
P02
46
9
P73/INT3/T0IN/T0HCP
7
49
P03
47
10
RES
8
50
P04
48
11
XT1/AN10
9
51
P05/CKO
49
12
XT2/AN11
10
52
P06/T6O
50
13
VSS1
11
53
P07/T7O
51
14
CF1
12
54
15
CF2
13
55
P20/INT4/T1IN/T0LCP/T0HCP/
INT6/T0LCP1
P21/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP/
39
52
53
16
VDD1
14
56
17
P80/AN0
15
57
18
P81/AN1
16
58
19
P82/AN2
17
59
P25/INT5/T1IN/T0LCP/T0HCP
57
20
P83/AN3
18
60
P26/INT5/T1IN/T0LCP/T0HCP
58
21
P84/AN4
19
61
P27/INT5/T1IN/T0LCP/T0HCP
59
22
P85/AN5
20
62
PB7
60
23
P86/AN6
21
63
PB6
61
24
P87/AN7
22
64
PB5
62
25
P30/PWM4
23
65
PB4
63
26
P31/PWM5
24
66
PB3
64
27
P32/UTX1
25
67
PB2
65
28
P33/URX1
26
68
PB1
66
29
P34
27
69
PB0
67
30
P10/SO0
28
70
VSS3
68
31
P11/SI0/SB0
29
71
VDD3
69
32
P12/SCK0
30
72
PC7/DBGP2
70
33
P13/SO1
31
73
PC6/DBGP1
71
34
P14/SI1/SB1
32
74
PC5/DBGP0
72
35
P15/SCK1
33
75
PC4
73
36
P16/T1PWML
34
76
PC3
74
37
P17/T1PWMH/BUZ
35
77
PC2
75
38
SI2P0/SO2
36
78
PC1
76
39
SI2P1/SI2/SB2
37
79
PC0
77
40
SI2P2/SCK2
38
80
PA0
78
UTX2
P23/INT4/T1IN/T0LCP/T0HCP/
URX2
P24/INT5/T1IN/T0LCP/T0HCP/
INT7/T0HCP1
54
55
56
No.A0143-8/28
LC87F5DC8A
System Block Diagram
Interrupt Control
IR
Standby Control
PLA
Flash ROM
RC
X’tal
Clock
Generator
CF
PC
MRC
SIO0
Bus Interface
ACC
SIO1
Port 0
B Register
SIO2
Port 1
C Register
Timer 0
Port 3
ALU
Timer 1
Port 7
Timer 4
Port 8
PSW
Timer 5
ADC
RAR
PWM0
INT0-3
Noise Rejection Filter
RAM
PWM1
Port 2 INT4, 5, 6, 7
Stack Pointer
Base Timer
Port A
Watch Dog Timer
Timer 6
Port B
Timer 7
Port C
UART1
UART2
PWM5
PWM4
On-chip Debugger
No.A0143-9/28
LC87F5DC8A
Pin Description
Name
VSS1
VSS2
VSS3
VDD1
I/O
Function description
Option
-
Power supply pin (-)
No
-
Power supply pin (+)
No
• 8-bit I/O port
Yes
VDD2
VDD3
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05 :System clock output
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input, bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input, bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1PWML output
P17 : Timer 1PWMH output, beeper output
Port 2
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units
• Other functions
P20 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/timer 0H capture input
P22 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/UART2 transmit
P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/UART2 receive
P24 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture inputINT7 input/timer 0H capture 1 input
P25 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer0L capture input/timer 0H
capture input Interrupt acknowledge type
Interrupt acknowledge type
Port 3
P30 to P34
I/O
Rising
Falling
INT4
Y
Y
INT5
Y
Y
INT6
Y
INT7
Y
Rising &
H level
L level
Y
N
N
Y
N
N
Y
Y
N
N
Y
Y
N
N
Falling
• 5-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
Continued on next page.
No.A0143-10/28
LC87F5DC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Function description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units
• Other functions
P70 : INT0 input/HOLD release input/timer 0L capture input/Output for watchdog timer
P71 : INT1 input/HOLD release input/timer 0H capture input
P72 : INT2 input/HOLD release input/timer 0 event input/timer 0L capture input
P73 : INT3 input with noise filter/timer 0 event input/timer 0H capture input
Interrupt acknowledge type
Rising
Falling
INT0
Y
Y
INT1
Y
Y
INT2
Y
INT3
Y
Rising &
H level
L level
N
Y
Y
N
Y
Y
Y
Y
N
N
Y
Y
N
N
Falling
• AD converter input port : AN8 (P70), AN9 (P71)
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P87
• Other functions
P80 to P87: AD converter input port
Port A
I/O
• 6-bit I/O port
Yes
• I/O specifiable in 1-bit units
PA0 to PA5
• Pull-up resistor can be turned on and off in 1-bit units
Port B
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistor can be turned on and off in 1-bit units
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC5 to PC7 : On-chip Debugger
SIO2 Port
I/O
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
SI2P0 to SI2P3
• Shared functions:
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0
O
• PWM0 output port
No
• General-purpose I/O available
PWM1
O
• PWM1 output port
No
• General-purpose I/O available
RES
I
Reset pin
No
XT1
I
• Input terminal for 32.768kHz X'tal oscillation
No
• Shared functions:
AN10: AD converter input port
General-purpose input port
Must be connected to VDD1 if not to be used
XT2
I/O
• Output terminal for 32.768kHz X'tal oscillation
No
• Shared functions:
AN11: AD converter input port
General-purpose I/O port
Must be set for oscillation and kept open if not to be used
CF1
I
Ceramic resonator input pin
No
CF2
O
Ceramic resonator output pin
No
No.A0143-11/28
LC87F5DC8A
Port Output Configuration
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
P00 to P07
1 bit
P10 to P17
P20 to P27
1 bit
Option Type
Output Type
Pull-Up Resistor
1
CMOS
Programmable (Note 1)
2
N-channel open drain
No
1
CMOS
Programmable
2
N-channel open drain
1
CMOS
2
N-channel open drain
P30 to P34
PA0 to PA5
PB0 to PB7
1 bit
PC0 to PC7
Programmable
Programmable
Programmable
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
-
No
N-channel open drain
No
No
CMOS
P80 to P87
SI2P0, SI2PS
SI2P3
-
No
PWM0, PWM1
SI2P1
No
-
CMOS (When selected as ordinary port)
N-channel open drain
No
(When SIO2 data is selected)
XT1
-
No
XT2
Input only
No
Output for 32.768kHz quartz oscillator
-
No
N-channel open drain
No
(when in general-purpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
Example 1: When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup
capacitors.
LSI
VDD1
Power
supply
For backup
VDD2
VDD3
VSS1 VSS2 VSS3
No.A0143-12/28
LC87F5DC8A
Example 2: The high-level output at the ports is unstable when the HOLD mode backup is in effect.
LSI
VDD1
Power
supply
For backup
VDD2
VDD3
VSS1 VSS2 VSS3
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Maximum Supply
Symbol
Pins/Remarks
VDDMAX
VDD1, VDD2,
VDD3
Input voltage
VI(1)
XT1, CF1
Input/Output
VIO(1)
Ports 0, 1, 2
voltage
Voltage
Conditions
VDD1=VDD2=VDD3
VDD[V]
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 3, 7, 8
Ports A, B, C
-0.3
SI2P0 to SI2P3
VDD+0.3
PWM0, PWM1,
XT2
Peak output
IOPH(1)
Ports 0, 1, 2, 3
CMOS output select per 1
Ports A, B, C
application pin
-10
PWM0, PWM1
Per 1 application pin
-20
IOPH(3)
P71 to P73
Per 1 application pin
-5
IOM(1)
Ports 0, 1, 2, 3
CMOS output select per 1
current
Ports A, B, C
application pin
-7.5
(Note1-1)
SI2P0 to SI2P3
-15
current
SI2P0 to SI2P3
IOPH(2)
High level output current
Average output
IOM(2)
PWM0, PWM1
Per 1 application pin
IOM(3)
P71 to P73
Per 1 application pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
Ports 1, 3
Total of all applicable pins
PWM0, PWM1
-3
-10
mA
-25
SI2P0 to SI2P3
ΣIOAH(3)
Ports 0
Total of all applicable pins
ΣIOAH(4)
Port 0, 1, 3
Total of all applicable pins
-25
-45
PWM0, PWM1
SI2P0 to SI2P3
ΣIOAH(5)
Ports 2, B
Total of all applicable pins
-25
ΣIOAH(6)
Ports A, C
Total of all applicable pins
-25
ΣIOAH(7)
Ports 2, A, B, C
Total of all applicable pins
-45
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A0143-13/28
LC87F5DC8A
Continued from preceding page.
Specification
Parameter
Peak output
Symbol
IOPL(1)
current
Pins/Remarks
P02-P07
Conditions
VDD[V]
min
typ
max
unit
Per 1 application pin
Ports 1, 2, 3
20
Ports A, B, C
SI2P0 to SI2P3
PWM0, PWM1
Average output
IOPL(2)
P00, P01
Per 1 application pin
30
IOPL(3)
Ports 7, 8, XT2
Per 1 application pin
10
IOML(1)
P02-P07
Per 1 application pin
current
Ports 1, 2, 3
(Note1-1)
Ports A, B, C
15
Low level output current
SI2P0 to SI2P3
PWM0, PWM1
IOML(2)
P00, P01
Per 1 application pin
20
IOML(3)
Ports 7, 8, XT2
Per 1 application pin
7.5
Total output
ΣIOAL(1)
Port 7, XT2
Total of all applicable pins
15
current
ΣIOAL(2)
Port 8
Total of all applicable pins
15
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
20
ΣIOAL(4)
Port 1, 3
Total of all applicable pins
PWM0, PWM1
mA
45
SI2P0 to SI2P3
ΣIOAL(5)
Port 0
Total of all applicable pins
ΣIOAL(6)
Port 0, 1, 3
Total of all applicable pins
45
80
PWM0, PWM1
SI2P0 to SI2P3
Maximum power
ΣIOAL(7)
Ports 2, B
Total of all applicable pins
45
ΣIOAL(8)
Ports A, C
Total of all applicable pins
45
ΣIOAL(9)
Ports 2, A, B, C
Total of all applicable pins
Pdmax
QIP80E
368
TQFP80J
325
Consumption
Operating
Topr
temperature range
Storage temperature
Tstg
range
80
mW
-20
70
-55
125
°C
Note 1-1: Average output current is average of current in 100ms interval.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A0143-14/28
LC87F5DC8A
Recommended Operating Range at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD [V]
min
typ
max
unit
0.245µs ≤ tCYC ≤ 200µs
2.8
5.5
supply voltage
0.367µs ≤ tCYC ≤ 200µs
2.5
5.5
(Note2-1)
1.47µs ≤ tCYC ≤ 200µs
2.2
5.5
2.0
5.5
Operating
Memory
VDD(1)
VHD
VDD1=VDD2=VDD3
VDD1=VDD2=VDD3
sustaining
RAM and register contents in
HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
2.2 to 5.5
P70 port input/
0.3VDD
VDD
+0.7
interrupt side
VIH(2)
Ports 0, 8
Ports A, B, C
2.2 to 5.5
PWM0,PWM1
VIH(3)
P70 Watchdog timer
side
VIH(4)
Low level input
VIL(1)
voltage
XT1, XT2, CF1,
RES
Ports 1, 2, 3
SI2P0 to SI2P3
VIL(2)
0.3VDD
VDD
+0.7
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
VDD
2.2 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
V
0.1VDD
+0.4
P71 to P73
P70 port input/
0.2VDD
interrupt
VIL(3)
Ports 0, 8
Ports A, B, C
VIL(4)
PWM0,PWM1
VIL(5)
Port 70 Watchdog
Timer
VIL(6)
XT1, XT2, CF1,
RES
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
Instruction cycle
tCYC
2.8 to 5.5
0.245
200
time
(Note2-2)
2.5 to 5.5
0.367
200
2.2 to 5.5
1.470
200
• CF2 pin open
2.8 to 5.5
0.1
12
• System clock frequency
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
2
External system
FEXCF(1)
CF1
clock frequency
μs
division rate = 1/1
• External system clock duty =
MHz
50±5%
• CF2 pin open
2.8 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
4
division rate = 1/2
Oscillation
FmCF(1)
CF1, CF2
frequency
Range
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note2-3)
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
Internal RC oscillation
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation.
See Fig. 2.
2.8 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
2.2 to 5.5
16
2.2 to 5.5
32.768
MHz
2.0
kHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0143-15/28
LC87F5DC8A
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
High level input
IIH(1)
current
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C
VIN=VDD
(including the off-leak current of
SI2P0 to SI2P3
RES
min
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
the output Tr.)
PWM0, PWM1
IIH(2)
Low level input
XT1, XT2
Using as an input port
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C
VIN=VSS
(including the off-leak current of
current
SI2P0 to SI2P3
RES
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-15
μA
the output Tr.)
PWM0, PWM1
IIL(2)
XT1, XT2
Using as an input port
IIL(3)
CF1
VIN=VSS
VIN=VSS
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1.0mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports A, B, C
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VDD-0.4
VOH(3)
VOH(4)
SI2P0 to SI2P
Ports 71, 72, 73
VOH(5)
IOH=-0.2mA
2.2 to 5.5
VOH(6)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
P30,P31(PWM4,5
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
IOH=-1.0mA
2.2 to 5.5
VDD-0.4
VOH(8)
output mode)
Low level output
VOL(1)
Ports 0, 1, 2, 3
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports A, B, C
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1.0mA
2.2 to 5.5
0.4
VOL(3)
VOL(4)
SI2P0 to SI2P3
PWM0, PWM1
P00, P01
VOL(5)
VOL(6)
VOL(7)
Ports 7, 8,XT2
VOL(8)
Pull-up resistation
Rpu
Ports 0, 1, 2, 3
IOL=30mA
4.5 to 5.5
1.5
IOL=5.0mA
3.0 to 5.5
0.4
IOL=2.5mA
2.2 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1.0mA
2.2 to 5.5
0.4
V
VOH=0.9VDD
Port 7
2.2 to 5.5
15
40
70
kΩ
Ports A, B, C
Hysteresis
VHIS
Voltage
RES
Ports 1, 2, 7
2.2 to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
SI2P0 to SI2P3
Pin capacitance
CP
All pins
• For pins other than that under
test : VIN=VSS
• f=1MHz
• Ta=25°C
No.A0143-16/28
LC87F5DC8A
Serial I/O Characteristics at Ta=-20 to +70°C, VSS1=VSS2=VSS3=0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pins/
Remarks
SCK0(P12)
Specification
Conditions
VDD[V]
• See Fig. 6.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
• Continuous data
Input clock
tSCKHA(1a)
transmission/reception mode
• SIO2 is not in use
2.2 to 5.5
simultaneous.
4
tCYC
• See Fig. 6.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
6
Serial clock
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected.
4/3
• See Fig. 6.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
Output clock
tSCKHA(2a)
• Continuous data
transmission/reception mode
• SIO2 is not in use
2.2 to 5.5
simultaneous.
tSCKH(2)
+2tCYC
• CMOS output selected.
tSCKH(2)
+
(10/3)tCYC
• See Fig. 6.
tSCKHA(2b)
tCYC
• Continuous data
transmission/reception mode
tSCKH(2)
• SIO2 is in use simultaneous.
+2tCYC
• CMOS output selected.
tSCKH(2)
+
(16/3)tCYC
• See Fig. 6.
Serial input
Data setup time
SI0(P11),
SB0(P11)
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
Data hold
thDI(1)
0.03
2.2 to 5.5
Time
Input clock
Output delay
0.03
tdD0(1)
time
SO0(P10),
SB0(P11),
• Continuous data
(1/3)tCYC
transmission/reception mode
+0.05
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode.
tdD0(3)
μs
1tCYC
• (Note 4-1-3)
2.2 to 5.5
Output clock
Serial output
tsDI(1)
+0.05
• (Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0143-17/28
LC87F5DC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
Tsck(3)
Low level
tSCKL(3)
Specification
Pins/
Conditions
Remarks
SCK1(P15)
VDD[V]
• See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected.
tSCKL(4)
1
2
1/2
2.2 to 5.5
pulse width
High level
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
Data hold
thDI(2)
0.03
2.2 to 5.5
time
Output delay time
Serial output
tsDI(2)
unit
1
• See Fig. 6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.2 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
Parameter
0.03
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK
• Must be specified as the time
to the beginning of output state
2.2 to 5.5
change in open drain output
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0143-18/28
LC87F5DC8A
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Symbol
tSCK(5)
Specification
Pins/
Conditions
Remarks
SCK2
VDD[V]
• See Fig. 6.
tSCKL(5)
tSCKH(5)
unit
1
pulse width
tSCKHA(5a)
Input clock
max
1
pulse width
High level
typ
2
(SI2P2)
Low level
min
• Continuous data transmission/
reception mode of SIO0 is not
in use simultaneous.
2.2 to 5.5
4
tCYC
• See Fig. 6.
• (Note 4-3-2)
tSCKHA(5b)
• Continuous data transmission/
reception mode of SIO0 is in
use simultaneous.
7
Serial clock
• See Fig. 6.
• (Note 4-3-2)
Frequency
Low level
tSCK(6)
tSCKL(6)
• CMOS output selected.
(SI2P2),
• See Fig. 6.
4/3
SCK2O
1/2
(SI2P3)
pulse width
High level
SCK2
tSCK
tSCKH(6)
1/2
Output clock
pulse width
tSCKHA(6a)
• Continuous data transmission/
reception mode of SIO0 is not
in use simultaneous.
2.2 to 5.5
• CMOS output selected.
tSCKH(6)
tSCKH(6)
+
+
(5/3)tCYC
(10/3)tCYC
• See Fig. 6.
tSCKHA(6b)
tCYC
• Continuous data transmission/
reception mode of SIO0 is in
tSCKH(6)
use simultaneous.
• CMOS output selected.
tSCKH(6)
+
+
(5/3)tCYC
(19/3)tCYC
• See Fig. 6.
Serial input
Data setup time
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
Data hold
thDI(3)
0.03
2.2 to 5.5
Time
Output delay time
Serial output
tsDI(3)
0.03
tdD0(5)
SO2
(SI2P0),
SB2(SI2P1)
µs
• Must be specified with respect
to falling edge of SIOCLK
• Must be specified as the time
to the beginning of output state
change in open drain output
2.2 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A0143-19/28
LC87F5DC8A
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
min
typ
max
unit
are enabled.
INT4(P20 to P23),
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
INT5(P24 to P27),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are enabled.
tCYC
constant is 1/1
tPIH(3)
INT3(P73)
• Interrupt source flag can be set.
tPIL(3)
(The noise rejection
• Event inputs for timer 0 are enabled.
clock is selected to
1/32.)
tPIH(4)
INT3(P73)
• Interrupt source flag can be set.
tPIL(4)
(The noise rejection
• Event inputs for timer 0 are enabled.
clock is selected to
1/128.)
tPIL(5)
RES
Reset acceptable.
μs
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Resolution
N
AN0(P80) to
Absolute
ET
AN7(P87),
(Note 6-1)
precision
AN8(P70),
Conversion
AN9(P71),
AD conversion time=32 × tCYC
AN10(XT1),
(when ADCR2=0) (Note 6-2)
TCAD
time
typ
max
unit
8
bit
±1.5
3.0 to 5.5
11.74
97.92
(tCYC=
(tCYC=
AN11(XT2) ,
0.367μs)
3.06μs)
AN12(PA3),
31.36
97.92
(tCYC=
(tCYC=
0.980μs)
3.06μs)
15.68
97.92
AN13(PA4),
4.5 to 5.5
3.0 to 5.5
AN14(PA5)
AD conversion time=64 × tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
Analog input
min
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
(tCYC=
(tCYC=
0.245μs)
1.53μs)
31.36
97.92
(tCYC=
(tCYC=
0.490μs)
1.53μs)
VSS
VDD
1
-1
LSB
μs
V
μA
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0143-20/28
LC87F5DC8A
Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
VDD1
consumption
=VDD2
current
=VDD3
(Note 7-1)
Specification
Pin/
Conditions
Remarks
VDD [V]
min
typ
max
unit
• FmCF=12MHz ceramic oscillation
mode
• FmX’tal=32.768kHz by crystal
4.5 to 5.5
9.5
22
2.8 to 4.5
5.5
15
4.5 to 5.5
7
16.5
2.5 to 4.5
4
12
4.5 to 5.5
2.8
6.5
oscillation mode
• System clock set to 12MHz side
IDDOP(2)
• Internal RC oscillation stopped
• frequency variable RC oscillation
stopped
• 1/1 frequency division ratio.
IDDOP(3)
• FmCF=8MHz ceramic oscillation
mode
• FmX’tal=32.768kHz by crystal
oscillation mode
• System clock set to 8MHz side
IDDOP(4)
• Internal RC oscillation stopped
• frequency variable RC oscillation
stopped
• 1/1 frequency division ratio.
IDDOP(5)
• FmCF=4MHz ceramic oscillation
mode
• FmX’tal=32.768kHz by crystal
mA
oscillation mode
IDDOP(6)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation
2.2 to 4.5
1.5
4.5
4.5 to 5.5
1
4.5
2.2 to 4.5
0.55
3.5
4.5 to 5.5
1.3
5.5
2.2 to 4.5
0.7
4.5
4.5 to 5.5
40
120
stopped
• 1/2 frequency division ratio.
IDDOP(7)
• FmCF=0Hz(oscillation stopped)
• FmX’tal=32.768kHz by crystal
oscillation mode
• System clock set to internal RC
IDDOP(8)
oscillation
• frequency variable RC oscillation
stopped
•1/2 frequency division ratio.
IDDOP(9)
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal
oscillation mode.
• System clock set to 1MHz with
IDDOP(10)
frequency variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDOP(11)
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal
oscillation mode.
• System clock set to 32.768kHz side.
IDDOP(12)
µA
• Internal RC oscillation stopped
• frequency variable RC oscillation
stopped
2.2 to 4.5
20
80
• 1/2 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0143-21/28
LC87F5DC8A
Continued from preceding page.
Parameter
Symbol
consumption
current
=VDD3
IDDHALT(1)
Conditions
Remarks
VDD1
=VDD2
HALT mode
Specification
Pin/
VDD [V]
min
typ
max
unit
• HALT mode
• FmCF=12MHz ceramic oscillation
mode
4.5 to 5.5
3.8
8.2
2.8 to 5.5
2.2
4.4
4.5 to 5.5
2.8
5.9
2.5 to 5.5
1.5
3.0
4.5 to 5.5
1.2
2.7
• FmX’tal=32.768kHz by crystal
(Note 7-1)
oscillation mode
IDDHALT(2)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation
stopped
• 1/1 frequency division ratio.
IDDHALT(3)
• HALT mode
• FmCF=8MHz ceramic oscillation
mode
• FmX’tal=32.768kHz by crystal
oscillation mode
IDDHALT(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation
stopped
• 1/1 frequency division ratio.
IDDHALT(5)
• HALT mode
• FmCF=4MHz ceramic oscillation
mode
mA
• FmX’tal=32.768kHz by crystal
oscillation mode
IDDHALT(6)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation
2.2 to 4.5
0.6
1.5
4.5 to 5.5
0.4
1.1
2.2 to 4.5
0.2
0.8
4.5 to 5.5
1.2
4
2.2 to 4.5
0.6
3
4.5 to 5.5
20
70
stopped
• 1/2 frequency division ratio.
IDDHALT(7)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX’tal=32.768kHz by crystal
oscillation mode
IDDHALT(8)
• System clock set to internal RC
oscillation
• frequency variable RC oscillation
stopped
•1/2 frequency division ratio.
IDDHALT(9)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal
oscillation mode.
IDDHALT(10)
• System clock set to 1MHz with
frequency variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDHALT(11)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal
oscillation mode.
μA
• System clock set to 32.768kHz side.
IDDHALT(12)
• Internal RC oscillation stopped
• frequency variable RC oscillation
2.2 to 4.5
10
50
stopped
• 1/2 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0143-22/28
LC87F5DC8A
Continued from preceding page.
Parameter
Symbol
IDDHOLD(1)
Current drain
Specification
Pin/
Conditions
Remarks
VDD1
VDD [V]
• HOLD mode
min
typ
max
unit
4.5 to 5.5
0.04
10
2.2 to 4.5
0.02
5
4.5 to 5.5
18
60
2.2 to 4.5
6
40
• CF1=VDD or open
during HOLD
IDDHOLD(2)
mode
IDDHOLD(3)
Current drain
(External clock mode)
VDD1
• Timer HOLD mode
• CF1=VDD or open
during time-base
clock HOLD
(External clock mode)
IDDHOLD(4)
mode
μA
• FmX'tal=32.768kHz by crystal
oscillation mode
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Onboard
IDDFW(1)
VDD1
programming
min
typ
max
unit
• 128-byte programming
• Erasing current including
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
current
Programming
tFW(1)
• 128-byte programming
time
• Erasing current including
• Time for setting up 128 byte data is
excluded.
UART (Full Duplex) Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Clock rate
UBR,UBR2
min
typ
max
unit
8192/3
tCYC
UTX1(P32),
RTX1(P33),
2.2 to 5.5
UTX2(P22),
16/3
RTX2(P23)
Data length:
Stop bits:
Parity bits:
7/8/9 bits (LSB first)
1-bit(2-bit in continuous data transmission)
None
*Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Stop bit
Start bit
Start of
transmission
Transmit data (LSB first)
End of
transmission
UBR,
UBR2
*Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR,
UBR2
No.A0143-23/28
LC87F5DC8A
VDD1, VSS1 Terminal condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1μF.
• Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
VDD3, VSS3 Terminal condition
It is necessary to place capacitors between VDD3 and VSS3 as describe below.
• Place capacitors as close to VDD3 and VSS3 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3’).
• Capacitance of C3 must be more than 0.1μF.
• Use thicker pattern for VDD3 and VDD3.
L3
VSS3
C3
VDD3
L3’
No.A0143-24/28
LC87F5DC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
12MHz
Stabilization
Voltage
Oscillator Name
CSTCE12M0G52-R0
Oscillation
Operating
Circuit Constant
C1
C2
Rf1
Rd1
[pF]
[pF]
[Ω]
[Ω]
(10)
(10)
OPEN
470
Time
Range
typ
[V]
2.8V to 5.5V
Remarks
max
[ms]
[ms]
0.05
0.15
Internal C1,C2
CSTCE8M00G52-R0
(10)
(10)
OPEN
2.2k
2.7V to 5.5V
0.05
0.15
Internal C1,C2
CSTLS8M00G53-B0
(15)
(15)
OPEN
680
2.5V to 5.5V
0.05
0.15
Internal C1,C2
CSTCR4M00G53-R0
(15)
(15)
OPEN
3.3k
2.2V to 5.5V
0.05
0.15
Internal C1,C2
CSTLS4M00G53-R0
(15)
(15)
OPEN
3.3k
2.2V to 5.5V
0.05
0.15
Internal C1,C2
8MHz
MURATA
4MHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
SEIKO
EPSON
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
560k
2.2 to 5.5
1.3
3.0
Remarks
Applicable
MC-306
CL value =
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
Rf1
Rf2
Rd1
C1
C2
XT2
Rd2
C3
C4
X’tal
CF
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Point
No.A0143-25/28
LC87F5DC8A
VDD
VDD limit
Power supply
GND
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilizing Time
HOLD release signal
HOLD release signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilizating Time
Figure 4 Oscillation Stabilizating Times
No.A0143-26/28
LC87F5DC8A
VDD
RRES
Note :
Select CRES and RRES value to assure that at least
200µs reset time is generated after the VDD becomes
higher than the minimum operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transmission period
(only SIO0,2)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transmission period
(only SIO0,2)
tSCKLA
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial Input/Output Test Condition
tPIL
tPIH
Figure 7 Pulse Input Timing Condition
No.A0143-27/28
LC87F5DC8A
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
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