LV8483CS-TE-L-H

Ordering number : ENA1609 Bi-CMOS IC For Camera Modules LV8483CS Composite Channel Lens Driver Overview LV8483CS is a constant current driver IC for voice coil motors (VCM) that includes a constant current 1.5-channel driver. It uses an ultraminiature wafer level package (WLP), which makes the IC ideal for VCM motor, shutter (SH), and iris (IR) drivers used in a wide variety of portable equipment including camera cell phones. Functions • Constant current driver for AF VCM + constant current 1.5-channel H-bridge driver for SH and IR • I2C bus interface • Low power consumption achieved using MOS process technologies • Built-in 4-bit DAC for constant current operation (used for SH and IR H-bridges) • Built-in 10-bit DAC for constant current control (used for AF VCM driver) • Built-in constant current detection resistance • Wafer level package. WLP10 (0.97mm × 2.47mm × 0.5mmt) • Built-in thermal shutdown circuit and LVS circuit. • AF VCM overshoot prevention function (current slope function) • Built-in SH/IR control pin (energization timing control function using trigger input) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 5.0 Output applied voltage VOUT max OUT1, OUT2, OUT3, OUT4 V 5.0 V Input applied voltage VIN max ENA, SCL, SDA, SH/IRTR GND pin flow-out current IGND Per channel 400 mA Allowable power dissipation Pd max With specified substrate * 550 mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +150 °C -0.3 to +5.0 V * Specified substrate : 50mm × 50mm × 1.6mm, glass epoxy 2-layer board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 31710 SY PC 20091013-S00004 No.A1609-1/9 LV8483CS Allowable Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Conditions Ratings Unit 2.5 to 4.5 V 0.4 × VCC to V to VCC × 0.13 V ENA, SCL, SDA and SH/IRTR Electrical Characteristics at Ta = 25°C, VCC = 2.8V Parameter Symbol Ratings Conditions min Supply current typ Unit max 1 μA 1 mA 1 μA ICCO ENA = L ICCO1 ENA = H Pin input current 1 IIN1 ENA, SCL, SDA Pin input current 2 IIN2 SH/IR TR VCC low-voltage cutoff voltage VthVCC Thermal shutdown temperature TSD Thermal hysteresis width ΔTSD Design target value 35 Output ON resistance 1 Ron11 VCC = 2.8V, IOUT = 80mA 2.0 2.55 Ω 2.4 2.95 Ω 2.0 2.4 Ω ±4 LSB ±1 LSB μA 28 2.0 V 175 °C °C (N-channel on-resistance + internal sensing resistor) (out1 + senceR) Output ON resistance 2 Design target value 0.7 Ron21 VCC = 2.8V, IOUT = 80mA (upper side + lower side + internal sensing resistor) (out2 to out4 + senceR) Ron22 VCC = 4.5V, IOUT = 100mA (upper side + lower side + internal sensing resistor) AF DAC block Resolution 10 Relative accuracy INL Differential linearity DNL Full code current Ifull Error code current 0 Izero bit 100 mA 1 μA H bridge driver block Output constant current DAC1 IOUT1 D3-D0code : 0000 260 mA Output constant current DAC9 IOUT9 D3-D0code : 1000 180 mA 110 mA Output constant current DAC16 IOUT16 D3-D0code : 1111 Energization time TSH D5-D4code : 00 Output turn ON time Traise OUT2-OUT4 1 3 μs Output turn OFF time Tfall OUT2-OUT4 0.2 1 μs SDA pin low level output VOL IO = 300μA 0.2 0.3 V 10 ms * Design guarantee value and no measurement is made. No.A1609-2/9 LV8483CS Package Dimensions unit : mm (typ) 3362 Pd max -- Ta SIDE VIEW BOTTOM VIEW 0.235 TOP VIEW Allowable power dissipation, Pd max -- W 0.8 5 4 0.27 3 2 1 0.5 0.97 2.47 0.235 0.5 MAX 0.5 0.14 SIDE VIEW 0.6 0.55 0.4 0.29 0.2 0 – 30 – 20 0 SANYO : WLP10(2.47X0.97) 20 40 60 75 80 100 Ambient temperature, Ta -- °C Pin Assignment 1 2 3 4 5 A SH/IR TR VCC ENA SDA SCL B OUT4 OUT3 GND OUT2 OUT1 Top view No.A1609-3/9 LV8483CS Block Diagram VCC AF VCM 10bit DAC SCL Current Slope Timing + OUT1 I2C DEC I2C I/F 0.5Ω SDA SH CONTROL ENA SH/IR TR OUT2 4bit DAC OUT3 OUT4 + - IR 0.5Ω VREF LVS TSD GND No.A1609-4/9 LV8483CS Serial Bus Communication Specifications I2C serial transfer timing conditions Standard mode twH SCL twL th2 ts1 tbus SDA th1 ts2 ts3 Start condition Stop condition ton toff Input waveform condition Standard mode Parameter symbol Conditions min typ unit fscl SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 μs th1 Hold time of SCL with respect to the falling edge of SDA 4.0 μs th2 Hold time of SDA with respect to the falling edge of SCL 0 μs twL SCL low period pulse width 4.7 μs twH SCL high period pulse width 4.0 ton SCL, SDA rising time 1000 ns toff SCL, SDA falling time 300 ns tbus Interval between stop condition and start condition Data hold time Pulse width Input waveform conditions Bus free time 0 max SCL clock frequency 100 kHz μs μs μs 4.7 High-speed mode Parameter Symbol Conditions min typ unit fscl SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 μs th1 Hold time of SCL with respect to the falling edge of SDA 0.6 μs th2 Hold time of SDA with respect to the falling edge of SCL 0 μs twL SCL low period pulse width 1.3 μs twH SCL high period pulse width 0.6 ton SCL, SDA (input) rising time 300 ns toff SCL, SDA (input) falling time 300 ns tbus Interval between stop condition and start condition Data hold time Pulse width Input waveform conditions Bus free time 0 max SCL clock frequency 1.3 400 kHz μs μs μs No.A1609-5/9 LV8483CS 2 I C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 th3 SCL SDA Data transfer and acknowledgement response After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) indicating the transfer direction of the subsequent data. Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the receiving end releases SDA at the falling edge of the ninth SCL clock. Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL 1st byte SDA S7 S6 S5 S4 S3 S2 S1 0 2nd byte 3rd byte A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Number of Slave Address is 0110011. (S7→S1) No.A1609-6/9 LV8483CS Data transfer write format The slave address and Write command must be allocated to the first byte and the register address in the serial map must be designated in the second byte. For the third byte, data transfer is carried out to the address designated by the register address which is written in the second byte. Subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. (*) Thus, continuous data transfer starting at the designated address is made possible. Since no auto incrementing occurs for address 02h and higher, it is necessary to send a stop condition after sending the data at address 02h. (*) Since 2-byte data is allocated to address 00h, when resister address 00h is specified in the second byte, the register address is auto-incremented to 01h after 2 bytes of data is sent. Data write example 1st byte 2nd byte S 0 1 1 0 0 1 1 0 A 0 0 0 0 0 0 0 0 A Slave address Register address set to 00h Write data to address 00h (Low byte) 5th byte Data 3 A Write data to address 01h S Start condition Master side transmission A Write data to address 00h (High byte) R/W = 0 written 4th byte Data 2 3rd byte Data 1 A 6th byte Data 4 A P Write data to address 02h P Stop condition A ACK signal Slave side transmission No.A1609-7/9 LV8483CS H-bridge Energization Timing Charts Energization time : Internal setting mode ⋅ ⋅ ⋅ Energization is automatically stopped when the time that is selected from 10ms, 13ms, and 20ms expires. IOUT External trigger mode SH/IR TR Energization starts on a rising edge of the SH/IR TR signal in the external trigger mode. IOUT Serial mode SDA Energization "ON" data transmit In the serial mode, energization is started by setting energization ON with serial data. Energization time : Free mode ⋅ ⋅ ⋅ Starting and stopping of energization must both be set using the external trigger or serial data. IOUT External trigger mode SH/IR TR In the external trigger mode, energization is started on a rising edge of the SH/IR TR signal and stopped on the falling edge. IOUT Serial mode SDA Energization "ON" data transmit Energization "OFF" data transmit In the serial mode, energization is started by setting energization ON with serial data and stopped by setting it OFF. No.A1609-8/9 LV8483CS SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2010. Specifications and information herein are subject to change without notice. PS No.A1609-9/9