NDF05N50ZH

NDF05N50Z, NDD05N50Z N-Channel Power MOSFET 500 V, 1.5 W Features • • • • • • Low ON Resistance Low Gate Charge ESD Diode−Protected Gate 100% Avalanche Tested 100% Rg Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com VDSS RDS(on) (MAX) @ 2.2 A 500 V 1.5 W N−Channel ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Symbol NDF VDSS NDD 500 V Continuous Drain Current RqJC ID 5.5 (Note 1) 4.7 A Continuous Drain Current RqJC, TA = 100°C ID 3.5 (Note 1) 3 A Pulsed Drain Current, VGS @ 10 V IDM 20 19 A Power Dissipation RqJC PD 30 83 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy, ID = 5.0 A EAS 130 mJ ESD (HBM) (JESD22−A114) Vesd 3000 V RMS Isolation Voltage (t = 0.3 sec., R.H. ≤ 30%, TA = 25°C) (Figure 17) VISO Peak Diode Recovery (Note 2) dV/dt 4.5 V/ns MOSFET dV/dt dV/dt 60 V/ns Continuous Source Current (Body Diode) IS 5 A Maximum Temperature for Soldering Leads TL 260 °C TJ, Tstg −55 to 150 °C Operating Junction and Storage Temperature Range D (2) Unit 4500 G (1) S (3) V 1 2 3 NDF05N50ZG, NDF05N50ZH TO−220FP CASE 221AH 4 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. IS = 4.4 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C 4 1 2 3 NDD05N50Z−1G IPAK CASE 369D 1 2 3 NDD05N50ZT4G DPAK CASE 369AA ORDERING AND MARKING INFORMATION See detailed ordering, marking and shipping information on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 8 1 Publication Order Number: NDF05N50Z/D NDF05N50Z, NDD05N50Z THERMAL RESISTANCE Parameter Junction−to−Case (Drain) Junction−to−Ambient Steady State Symbol Value Unit NDF05N50Z NDD05N50Z RqJC 4.2 1.5 °C/W (Note 3) NDF05N50Z (Note 4) NDD05N50Z (Note 3) NDD05N50Z−1 RqJA 50 38 80 3. Insertion mounted 4. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Conditions Min Drain−to−Source Breakdown Voltage BVDSS VGS = 0 V, ID = 1 mA 500 Breakdown Voltage Temperature Coefficient DBVDSS/ DTJ Reference to 25°C, ID = 1 mA Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current Gate−to−Source Forward Leakage IDSS VDS = 500 V, VGS = 0 V IGSS VGS = ±20 V Static Drain−to−Source On−Resistance RDS(on) VGS = 10 V, ID = 2.2 A Gate Threshold Voltage VGS(th) VDS = VGS, ID = 50 mA gFS VDS = 15 V, ID = 2.5 A V 0.6 V/°C 25°C 1 150°C 50 mA ±10 mA 1.25 1.5 W 3.9 4.5 V ON CHARACTERISTICS (Note 5) Forward Transconductance 3.0 3.5 S DYNAMIC CHARACTERISTICS Input Capacitance (Note 6) Ciss Output Capacitance (Note 6) Coss Reverse Transfer Capacitance (Note 6) Crss Total Gate Charge (Note 6) Qg Gate−to−Source Charge (Note 6) Qgs Gate−to−Drain (“Miller”) Charge (Note 6) Qgd Plateau Voltage VGP Gate Resistance Rg VDS = 25 V, VGS = 0 V, f = 1.0 MHz VDD = 250 V, ID = 5 A, VGS = 10 V 421 530 632 50 68 80 8 15 25 9 18.5 28 2 4 6 5 10 15 6.5 1.5 4.5 pF nC V 8 W RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) ns 11 VDD = 250 V, ID = 5 A, VGS = 10 V, RG = 5 W tf 15 24 14 SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) VSD IS = 5 A, VGS = 0 V Reverse Recovery Time trr Reverse Recovery Charge Qrr VGS = 0 V, VDD = 30 V IS = 5 A, di/dt = 100 A/ms Diode Forward Voltage 1.6 V 255 ns 1.25 mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 6. Guaranteed by design. www.onsemi.com 2 NDF05N50Z, NDD05N50Z 10.0 10.0 9.0 9.0 VGS = 8 V to 10 V 8.0 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TYPICAL CHARACTERISTICS 7.0 V 7.0 6.5 V 6.0 5.0 4.0 6.0 V 3.0 2.0 5.5 V 1.0 0.0 8.0 7.0 6.0 5.0 TJ = 25°C 4.0 TJ = 150°C 3.0 TJ = −55°C 2.0 1.0 5.0 V 0 VDS = 25 V 5 10 15 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 25 0.0 3 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 2.50 ID = 2.2 A TJ = 25°C 2.25 2.00 1.75 1.50 1.25 1.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 2.500 VGS = 10 V TJ = 25°C 2.250 2.000 1.750 1.500 1.250 1.000 0.0 0.5 2.25 ID = 2.2 A VGS = 10 V 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 4. On−Resistance versus Drain Current and Gate Voltage BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.75 1.0 ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate−to−Source Voltage 2.50 10 150 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 Figure 5. On−Resistance Variation with Temperature −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 Figure 6. BVDSS Variation with Temperature www.onsemi.com 3 NDF05N50Z, NDD05N50Z TYPICAL CHARACTERISTICS 1200 10.0 TJ = 150°C 1100 TJ = 25°C VGS = 0 V f = 1 MHz C, CAPACITANCE (pF) 1.0 900 800 700 600 Ciss 500 400 300 200 100 0.1 0 50 0 100 150 200 250 300 350 400 450 500 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 Figure 7. Drain−to−Source Leakage Current versus Voltage 5 10 15 20 25 30 35 40 45 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 50 Figure 8. Capacitance Variation 300 VGS, GATE−TO−SOURCE VOLTAGE (V) 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 Coss Crss QT VDS, DRAIN−TO−SOURCE VOLTAGE (V) IDSS, LEAKAGE (mA) 1000 250 VDS 200 VGS QGS QGD 150 100 VDS = 250 V ID = 5 A TJ = 25°C 0 2 4 6 8 10 12 14 16 Qg, TOTAL GATE CHARGE (nC) 18 50 0 20 Figure 9. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 100 VDD = 250 V ID = 5 A VGS = 10 V 100 IS, SOURCE CURRENT (A) t, TIME (ns) 1000 td(off) tr tf td(on) 10 1.0 1 10 RG, GATE RESISTANCE (W) 10 TJ = 150°C 1.0 125°C 0.1 100 25°C −55°C 0.3 Figure 10. Resistive Switching Time Variation versus Gate Resistance 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Diode Forward Voltage versus Current www.onsemi.com 4 1.2 NDF05N50Z, NDD05N50Z TYPICAL CHARACTERISTICS 10 100 VGS ≤ 30 V SINGLE PULSE TC = 25°C 100 ms 1 ms 10 ms dc 10 ms ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1 10 100 10 VGS v 30 V SINGLE PULSE TC = 25°C 0.1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1000 100 ms 1 ms 10 ms 1 10 100 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 12. Maximum Rated Forward Biased Safe Operating Area NDF05N50Z Figure 13. Maximum Rated Forward Biased Safe Operating Area NDD05N50Z 10 50% (DUTY CYCLE) R(t) (C/W) 1 20% 10% 5.0% 0.1 2.0% 1.0% 0.01 1E−06 RqJA = 4.2°C/W Steady State SINGLE PULSE 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 PULSE TIME (s) Figure 14. Thermal Impedance (Junction−to−Case) for NDF05N50Z 10 R(t) (C/W) 1 50% (DUTY CYCLE) 20% 10% 0.1 5.0% 2.0% 1.0% 0.01 1E−06 RqJC = 1.5°C/W Steady State SINGLE PULSE 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 PULSE TIME (s) Figure 15. Thermal Impedance (Junction−to−Case) for NDD05N50Z www.onsemi.com 5 1E+02 1E+03 NDF05N50Z, NDD05N50Z TYPICAL CHARACTERISTICS R(t) (C/W) 100 10 50% (DUTY CYCLE) 20% 10% 1 5.0% 2.0% 1.0% 0.1 0.01 1E−06 RqJA = 38°C/W Steady State SINGLE PULSE 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 PULSE TIME (s) Figure 16. Thermal Impedance (Junction−to−Ambient) for NDD05N50Z LEADS HEATSINK 0.110″ MIN Figure 17. Isolation Test Diagram Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 1E+02 1E+03 NDF05N50Z, NDD05N50Z ORDERING INFORMATION Package Shipping† NDF05N50ZG TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDF05N50ZH TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDD05N50Z−1G IPAK (Pb−Free, Halogen−Free) 75 Units / Rail NDD05N50ZT4G DPAK (Pb−Free, Halogen−Free) 2500 / Tape and Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS 4 Drain Source 1 2 3 Gate Drain Source Drain TO−220FP IPAK A Y WW G, H 4 Drain YWW 5N 50ZG Gate YWW 5N 50ZG NDF05N50ZG or NDF05N50ZH AYWW = Location Code = Year = Work Week = Pb−Free, Halogen−Free Package www.onsemi.com 7 2 1 Drain 3 Gate Source DPAK NDF05N50Z, NDD05N50Z PACKAGE DIMENSIONS TO−220 FULLPACK, 3−LEAD CASE 221AH ISSUE F A E B P E/2 0.14 Q D M B A A H1 M A1 C NOTE 3 1 2 3 L L1 3X 3X SEATING PLANE b2 c b 0.25 M B A M C A2 e SIDE VIEW FRONT VIEW SECTION D−D A NOTE 6 NOTE 6 H1 D D A SECTION A−A ALTERNATE CONSTRUCTION www.onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEASURED AT OUTERMOST EXTREME OF THE PLASTIC BODY. 5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00. 6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1 AND H1 FOR MANUFACTURING PURPOSES. DIM A A1 A2 b b2 c D E e H1 L L1 P Q MILLIMETERS MIN MAX 4.30 4.70 2.50 2.90 2.50 2.90 0.54 0.84 1.10 1.40 0.49 0.79 14.70 15.30 9.70 10.30 2.54 BSC 6.60 7.10 12.50 14.73 --2.80 3.00 3.40 2.80 3.20 NDF05N50Z, NDD05N50Z PACKAGE DIMENSIONS IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T www.onsemi.com 9 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− NDF05N50Z, NDD05N50Z PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369AA ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NDF05N50Z/D