STK672-060-E

Ordering number : EN7441B Thick-Film Hybrid IC STK672-060-E Overview Unipolar Constant-current Chopper (external excitation PWM) Circuit with Built-in Microstepping Controller Stepping Motor Driver (sine wave drive) Output Current 1.2A (no heat sink*) The STK672-060-E is a stepping motor driver hybrid IC that uses power MOSFETs in the output stage. It includes a builtin microstepping controller and is based on a unipolar constant-current PWM system. The STK672-060-E supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. It supports five excitation methods: 2 phase, 1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. It also allows the motor speed to be controlled with only a clock signal. The use of this hybrid IC allows designers to implement systems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive. Applications • Facsimile stepping motor drive (send and receive) • Paper feed and optical system stepping motor drive in copiers • Laser printer drum drive • Printer carriage stepping motor drive • X-Y plotter pen drive • Other stepping motor applications Note*: Conditions: VCC1 = 24V, IOH = 1.2A, 2W1-2 excitation mode. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61108HKIM/22004TN(OT) No.7441-1/19 STK672-060-E Features • Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator. • One of five drive types can be selected with the drive mode settings (M1, M2, and M3) 1) 2 phase excitation drive 2) 1-2 phase excitation drive 3) W1-2 phase excitation drive 4) 2W1-2 phase excitation drive 5) 4W1-2 phase excitation drive • Provides four freely selectable modes for the vector locus during microstepping drive: circular mode, one inside mode, and two outside modes. • Phase retention even if excitation is switched. • The excitation phase state can be verified in real time using the MO1, MO2, and MOI signal output pins. • The CLK input counter block can be selected to be one of the following by the high/low setting of the M3 input pin. 1) Rising edge only 2) Both rising and falling edges • The CLK and RETURN input pins include built-in malfunction prevention circuits for external pulse noise. • ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20kΩ (typical) pull-up resistors. • No noise generation due to the difference between the A and B phase time constants during motor hold since external excitation is used. • Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any value between 0V and 1/2VCC2. • External excitation PWM drive allows a wide operating supply voltage range (VCC1 = 10 to 45V) to be used. • Current detection resistor (0.22Ω) built-in the hybrid IC itself. • Power MOSFETs adopted for low drive loss. • Provides a motor output drive current of IOH = 1.2A. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Input voltage Output current Repeated avalanche capacity Allowable power dissipation Operating substrate temperature Junction temperature Storage temperature Symbol VCC1 max VCC2 max VIN max IOH max Ear max Pd max Tc max Tj max Tstg θc-a = 0 No signal No signal Logic input pins 0.5s, 1 pulse, when VCC1 applied Conditions Ratings 52 -0.3 to +7.0 -0.3 to +7.0 1.6 25 7 105 150 -40 to +125 Unit V V V A mJ W °C °C °C Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Input voltage Phase driver withstand voltage Output current Symbol VCC1 VCC2 VIH VDSS IOH Tr1, 2, 3, and 4 (the A, A, B, and B outputs) Duty 50% With signals applied With signals applied Conditions Ratings 10 to 45 5 ± 5% 0 to VCC2 100 (min) 1.2 Unit V V V V A No.7441-2/19 STK672-060-E Electrical Characteristics at Tc = 25°C, VCC1 = 24V, VCC2 = 5V Parameters Control supply current Output saturation voltage Average output current FET diode forward voltage [Control Inputs] Input voltage VIH VIL IIH IIL Except for the Vref pin Except for the Vref pin Except for the Vref pin Except for the Vref pin 0 125 1 250 4 1 10 510 V V μA μA Symbols ICC Vsat Ioave Vdf Conditions min Pin 7, with ENABLE pin held low. RL = 23Ω (I ≈ 1A) Load: R = 3.5Ω / L = 3.8mH For each phase, Vref ≈ 1.69V If = 1A 0.470 Rating typ 2.5 0.8 0.524 1.2 max 14 1.1 0.580 1.8 mA V A V unit Input current [Vref Input Pin] Input voltage Input current [Control Outputs] Output voltage [Current Distribution Ratio (A·B)] 2W1-2, W1-2, 1-2 2W1-2, W1-2 2W1-2 2W1-2, W1-2, 1-2 2W1-2 2W1-2, W1-2 2W1-2 2 PWM frequency VI II Pin 8 Pin 8, VI = 2.5V 0 330 415 2.5 545 V μA VOH VOL I = –3mA, pins MOI, MO1, MO2 I = +3mA, pins MOI, MO1, MO2 2.4 0.4 V V Vref Vref Vref Vref Vref Vref Vref Vref fc θ = 1/8 θ = 2/8 θ = 3/8 θ = 4/8 θ = 5/8 θ = 6/8 θ = 7/8 100 92 83 71 55 40 21 100 37 47 57 % % % % % % % % kHz Note: A constant-voltage power supply must be used. The design target value is shown for the current distribution ratio. Package Dimensions unit:mm (typ) 4161 53.0 9.0 22.0 1 2.0 21 2=42 22 4.0 1.0 0.5 0.4 2.9 No.7441-3/19 VCC2 7 12 13 8 6 5 2 1 M4 M5 Vref A A B B Internal Block Diagram M1 Current distribution ratio switching 9 M2 10 Excitation mode control CWB 15 Phase advance counter CLK 14 Rise/fall detection and switching Pseudo-sine wave generator M3 11 RETURN 17 Rise detection RESET 16 MOI 19 Phase excitation drive signal generation MO1 20 – Excitation state monitor STK672-060-E MO2 21 + ENABLE 18 RC oscillator SG 22 SUB 4 + – Reference clock generation PWM control 3 PG ITF02264 No.7441-4/19 STK672-060-E Test Circuit Diagrams Vsat VCC2 7 14 6 5 9 10 STK672-060-E Vref=2.5V VCC2 4 + 16 22 ITF02265 Vdf VCC1 7 A A B B 23Ω Start 6 5 2 1 STK672-060-E A A B B 2 1 8 V V 4 3 22 ITF02266 3 A IIH, IIL VCC2 Ioave, ICC, fc VCC2 A M1 M2 M3 M4 M5 7 9 10 11 12 13 14 STK672-060-E 15 16 17 18 8 22 VCC1 Start 14 9 10 7 6 2 5 1 A A B B a ba SW1 b IIH A IIL SW2 CLK CWB RESET RETURN ENABLE Vref Vref=1.69V 5V Low when measuring ICC 0V 0V VCC2 8 STK672-060-E 18 VCC1 + 16 22 A ITF02267 ITF02268 When measuring Ioave: With SW1 set to ‘b’, Vref = 1.69V When measuring fc: With SW1 set to ‘a’, Vref = 0V When measuring ICC: Set ENABLE low No.7441-5/19 STK672-060-E Power-on Reset The application must perform a power-on reset operation when VCC2 power is first applied to this hybrid IC. Application circuit that used 2W1-2 phase excitation (microstepping operation) mode. VCC2=5V VCC1=10V to 45V Two-phase stepping motor 6 5 2 1 A A B B + Simple power-on reset circuit (This circuit cannot be used to detect drops in the supply voltage.) 9 10 11 12 VCC2=5V 13 14 15 CLK 14 18 16 RET MOI MO1 MO2 17 19 20 21 22 8 RoX Ro1 Vref Ro2 VCC2=5V A value of about 100Ω is recommended for Ro2 to minimize the influence of the 6kΩ internal resistance of the Vref pin. RoX: Input impedance of 6kΩ ±30% STK672-060-E 3 4 SG PG VF 0.3V + 1kΩ ENABLE RESET 100μF or higher 7 ITF02269 Setting the Motor Current The motor current IOH is set by the Vref voltage on the hybrid IC pin 8. The following formula gives the relationship between IOH and Vref. RoX = (Ro2 × 6kΩ) ÷ (Ro2 + 6kΩ) Vref = VCC2 × RoX ÷ (Ro1 + RoX) IOH = (1) (2) 1 × Vref (3) K Rs K: 7.66 (voltage divider ratio), Rs: 0.22Ω (This is the hybrid IC's internal current detection resistor. It has a tolerance of ±3%.) Applications can use motor currents from the current (0.05 to 0.1A) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, IOH = 1.2A Ioave 0A Motor current waveform A13262 IOL IOH Function Table M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 Phase switching clock edge timing 1 2W1-2 phase excitation 4W1-2 phase excitation Rising edge only Rising and falling edges Forward CWB 0 Reverse 1 ENABLE RESET Motor current is cut off when low Active low A MO1 MO2 1 0 A 0 0 B 0 1 B 1 1 No.7441-6/19 STK672-060-E Printed Circuit Board Design Recommendations This hybrid IC has two grounds, the PG pins (pins 3 and 4) and the SG pin (pin 22). These are connected internally in the hybrid IC. Two power supplies are required: a motor drive supply and a 5V supply for the hybrid IC itself. If the ground connections for these supplies are not good, the motor current waveforms may become unstable, motor noise may increase, and vibration levels may increase. Use appropriate wiring for these grounds. Here we present two methods for implementing these ground connections. If the grounds for the motor drive supply and the hybrid IC 5V supply are connected in the immediate vicinity of the power supplies: • If PG and SG are shorted at the power supply, connect only the PG line to pins 3 and 4 on the hybrid IC. Also, be sure that no problems occur due to voltage drops due to common impedances. In the specifications, this must be VCC2 ±5%. • The current waveforms will be more stable if the Vref ground is connected to pin 22. • For initial values, use 100μF or over for C1 and 10μF or over for C2. Locate C1 as close to the hybrid IC as possible, and the capacitor ground line must be as short as possible. Stepping motor + Motor drive power -supply PG 100μF or over + 5V power supply -C2 10μF or over STK672-060-E C1 + 3 PG 4 7 VCC2 + 8 Vref 14 CLK SG Oscillator circuit (CLK) 22 SG ITF02270 If the grounds for the motor drive supply and the hybrid IC 5V supply are separated: • Insert a capacitor (C1) of 100μF or over as close as possible to the hybrid IC. The capacitor ground line must be as short as possible. The capacitor C2 may be included if necessary. Its ground line should also be as short as possible. Stepping motor + Motor drive power -supply PG Separation + 5V power supply -C2 10μF or over STK672-060-E C1 + 100μF or over 3 PG 4 7 VCC2 + 8 Vref 14 CLK SG Oscillator circuit (CLK) 22 SG ITF02271 No.7441-7/19 STK672-060-E Functional Description External Excitation Chopper Drive Block Description VCC1 M4 M5 IOFF ION Enable φA (control signal) Current divider Vref L2 φA L1 φA Divider CR oscillator 800kHz A=1 45kHz S D1 MOSFET AND Q Latch circuit R Noise filter – + Rs ITF02272 Driver Block Basic Circuit Structure Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required. When a high level is input to φA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be input, the Q output will go high, and the MOSFET will be turned on as its initial value. The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to the latch circuit set pin occurs. In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when the motor is locked. Input Pin Functions Pin No. 14 15 17 18 9, 10, 11 12, 13 16 8 Symbol CLK CWB RETURN ENABLE M1, M2, M3 M4, M5 RESET Vref Function Phase switching clock Rotation direction setting (CW/CCW) Forced phase origin return Output cutoff Excitation mode setting Vector locus setting System reset Current setting Pin circuit type Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Operational amplifier input No.7441-8/19 STK672-060-E Input Signal Functions and Timing • CLK (phase switching clock) 1) Input frequency range: DC to 50kHz 2) Minimum pulse width: 10μs 3) Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.) 4) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 5) Built-in multi-stage noise rejection circuit 6) Function: - When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge. - When M3 is low: The phase is advanced one step by both rising and falling edges, for a total of two steps per cycle. CLK Input Acquisition Timing (M3 = Low) CLK input System clock Phase excitation counter clock Excitation counter up/down Control output timing Control output switching timing A13264 • CWB (Method for setting the rotation direction) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When CWB is low: The motor turns in the clockwise direction. - When CWB is high: The motor turns in the counterclockwise direction. 3) Notes: When M3 is low, the CWB input must not be changed for about 6.25μs before or after a rising or falling edge on the CLK input. • RETURN (Forcible return to the origin for the currently excited phase) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Built-in noise rejection circuit 3) Notes: The currently excited (driven) phase can be forcibly moved to the origin by switching this input from low to high. Normally, if this input is unused, it must be left open or connected to VCC2. • ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold as the internal state of this hybrid IC.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When ENABLE is high or open: Normal operating state - When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the reset input have any effect on the hybrid IC state. No.7441-9/19 STK672-060-E • M1, M2, and M3 (Excitation mode and CLK input edge timing selection) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 Phase switching clock edge timing 1 2W1-2 phase excitation 4W1-2 phase excitation Rising edge only Rising and falling edges 3) Valid mode setting timing: Applications must not change the mode in the period 5μs before or after a CLK signal rising or falling edge. Mode Setting Acquisition Timing CLK input System clock Mode setting M1 to M3 Mode switching clock Mode switching timing Hybrid IC internal setting state Phase excitation clock Excitation counter up/down A13265 • M4 and M5 (Microstepping mode rotation vector locus setting) M4 M5 Mode 1 1 Circular 0 0 1 0 0 1 Phase B 1 1 2 3 See page 11 for details on the current division ratio. Circular 2 3 Phase A ITF02273 • RESET (Resets all parts of the system.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at least 10μs.) At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to about 71% after the reset is released. 3) Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must apply a power on reset when the VCC2 power supply is first applied. • Vref (Sets the current level used as the reference for constant-current detection.) 1) Pin circuit type: Analog input structure 2) Function: - Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage VCC2 minus 2.5V. - Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5V as the upper limit. No.7441-10/19 STK672-060-E Output Pin Functions Pin No. 19 20, 21 Symbol MOI MO1, MO2 Function Phase excitation origin monitor Phase excitation state monitor Pin circuit type Standard CMOS structure Standard CMOS structure Output Signal Functions and Timing • A, A, B, and B (Motor phase excitation outputs) 1) Function: - In the 4 phase and 2 phase excitation modes, a 3.75μs (typical) interval is set up between the A and A and B and B output signal transition times. • MO1, MO2, and MOI (Phase excitation state monitors) 1) Pin circuit type: Standard CMOS structure 1) Function: - Output of the current phase excitation output state. Phase coordinate MO1 MO2 Phase A 1 0 Phase B 0 1 Phase A 0 0 Phase B 1 1 MOI outputs a 0 when each phase is at the origin, and outputs a 1 otherwise. • Current division ratios set by M3, M4, and M5 ········· Values provided for reference purposes. Mode Setting M3 = 0 M3 = 1 Circular M4 = 1 M5 = 1 15 2W1-2 21 31 2W1-2 40 47 2W1-2 Current division ratio 4W1-2 2W1-2 55 63 71 76 2W1-2 83 87 2W1-2 92 96 2W1-2 100 1 M4 = 0 M5 = 0 16 25 34 44 50 59 67 75 81 87 92 95 98 100 2 M4 = 1 M5 = 0 16 24 33 41 49 56 63 70 76 84 88 95 98 100 3 M4 = 1 M5 = 1 15 20 28 38 44 53 60 67 73 81 84 91 93 100 7/8 6/8 5/8 % 4/8 3/8 2/8 1/8 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 Units Number of steps [Load conditions] VCC1 = 24V, VCC2 = 5V, R/L = 3.5/3.8mH No.7441-11/19 STK672-060-E Phase States During Excitation Switching • Excitation phases before and after excitation mode switching 2W1-2 phase → 2 phase A 0 1 2W1-2 phase → 1-2 phase 31 28 27 25 B 24 20 8B 12 9 20 17 19 16 A 16 A W1-2 phase → 1-2 phase 30 4 28 B 24 20 22 20 18 16 A 1-2 phase → 2 phase A 0 28 28 20 20 16 A 2 phase → 1-2 phase A 0 4 B 12 12 18 A 2 phase → W1-2 phase A 30 29 5 B 24 28 20 4 12 8B 22 6 B 28 20 4 12 B 20 21 16 A A 14 13 17 A 12 B B 28 4 14 8B 22 4 26 0 28 20 4 6 B 12 16 B 10 21 13 17 A 2 phase → 2W1-2 phase A 25 28 0 4 24 8 20 12 16 B 9 14 8B 12 12 10 22 20 18 16 A 1-2 phase → W1-2 phase A 30 2 29 14 6 4 28 26 B 24 A 0 2 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 23 21 19 17 A 1-2 phase → 2W1-2 phase A 1 5 15 13 27 25 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 2W1-2 phase → W1-2 phase A 30 31 0 1 2 3 29 4 28 5 27 30 0 2 26 6 28 4 25 26 7 6 B 24 24 8 8B 22 10 23 20 9 1816 1412 22 10 11 21 20 12 13 19 18 17 161514 A W1-2 phase → 2W1-2 phase A 29 31 1 3 5 7 B 9 11 A 3 4 5 8B 11 12 28 4 B 24 28 0 4 8 24 20 16 12 15 W1-2 phase → 2 phase 30 28 26 A 0 2 B 24 Excitation phase developed by the first CLK internal pulse after the change in the excitation mode setting with M1 and M Excitation phase immediately prior to the excitation mode setting A13266 No.7441-12/19 STK672-060-E • Excitation phases before and after excitation mode switching 2W1-2 phase → 2 phase 31 A 0 28 28 B 24 23 20 8B 12 21 20 16 A W1-2 phase → 2 phase A 0 28 28 B 24 20 22 8B 12 22 20 16 A 1-2 phase → 2 phase A 0 28 28 20 20 16 A 2 phase → 1-2 phase A 0 4 B 12 12 18 A 2 phase → W1-2 phase A 2 3 27 B 24 28 20 4 12 8B 26 B 28 20 4 12 B 10 19 A A A13267 2W1-2 phase → 1-2 phase A 01 4 5 28 0 4 8 24 20 16 12 13 12 8B 9 2W1-2 phase → W1-2 phase A 30 31 0 1 2 3 29 4 28 5 27 30 0 2 26 6 28 4 25 26 7 6 B 24 24 8 8B 22 10 23 20 9 1816 1412 22 10 11 21 12 20 13 19 18 17 161514 A W1-2 phase → 2W1-2 phase A 31 1 3 5 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 29 4 7 25 B 24 15 1716 A W1-2 phase → 1-2 phase 30 A 02 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 18 16 A 1-2 phase → W1-2 phase A 30 2 14 30 29 27 25 6 4 26 B 24 7 B 9 11 13 23 21 19 14 17 A 15 1-2 phase → 2W1-2 phase A 30 27 B B 3 4 26 8B 22 28 0 4 24 20 16 12 10 14 6 28 0 4 24 8 20 12 16 B 24 7 B 11 23 19 A 15 2 phase → 2W1-2 phase A B 28 20 4 12 11 B 16 A 18 No.7441-13/19 STK672-060-E Excitation Time and Timing Charts • CLK rising edge operation 2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 1 M3 0 1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 1 1 RESET CWB CLK A A B B RESET CWB CLK A A MOSFET Gate Signal MOSFET Gate Signal MOSFET Gate Signal B B MO1 MO2 MOI 100% Comparator Reterence Voltage Comparator Reterence Voltage MO1 MO2 MOI 100% 71% 71% Vref A 100% 71% Vref A 100% 71% Vref B Vref B W1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 1 1 2W1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 M3 0 1 1 1 RESET CWB CLK A A B B RESET CWB CLK A A MOSFET Gate Signal MO1 MO2 MOI Comparator Reterence Voltage Comparator Reterence Voltage B B MO1 MO2 MOI 100% 92% 83% 71% 55% 40% 20% 100% 92% 71% 40% Vref A 100% 92% 71% 40% Vref A 100% 92% 83% 71% 55% 40% 20% Vref B Vref B ITF02274 No.7441-14/19 STK672-060-E • CLK rising and falling edge operation 1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB 1 MOSFET Gate Signal MO1 MO2 MOI 100% Comparator Reterence Voltage Comparator Reterence Voltage MO1 MO2 MOI 100% 92% 71% 40% 71% Vref A 100% 71% Vref A 100% 92% 71% 40% Vref B Vref B 2W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB 1 4W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 M2 0 M3 0 RESET CWB 1 1 CLK A A B B MO1 MO2 MOSFET Gate Signal CLK MOSFET Gate Signal MOSFET Gate Signal CLK A A B B CLK A A B B A A B B MO1 MO2 MOI Comparator Reterence Voltage MOI Comparator Reterence Voltage 100% 92% 83% 71% 55% 40% 20% Vref A 100% 92% 83% 71% 55% 40% 20% 96%100% 87% 92% 76% 83% 71% 63% 55% 47% 40% 31% 15% 21% Vref A 97%100% 88% 92% 77% 83% 63% 71% 47% 55% 40% 31% 15% 21% Vref B Vref B ITF02275 No.7441-15/19 STK672-060-E Thermal Design The main elements internal to this hybrid IC with large average power losses are the current control devices, the regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2 phase excitation. The losses in the various excitation modes are as follows. 2 phase excitation ·fclock I Pd2EX = (Vsat+Vdf) · fclock · IOH · t2 + OH · (Vsat · t1+Vdf · t3) 2 2 Pd1-2EX = 0.64 · {(Vsat+Vdf) · 1-2 phase excitation ·fclock I fclock · IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 4 4 ·fclock I fclock ·IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 8 8 W1-2 phase excitation PdW1-2EX = 0.64 · {(Vsat+Vdf) · ·fclock I 2W1-2 phase excitation Pd2W1-2EX = 0.64 · {(Vsat+Vdf) · fclock ·IOH · t2 + OH · (Vsat · t1+Vdf · t3)} 16 16 4W1-2 phase excitation Pd4W1-2EX = 0.64 · {(Vsat+Vdf) · I OH ·fclock fclock ·IOH · t2 + · (Vsat · t1+Vdf · t3)} 16 16 Here, t1 and t3 can be determined from the same formulas for all excitation methods. −L R + 0.7 t1 = · n (1 – R + 0.7 VCC 1 · IOH) VCC 1 + 0.7 t3 = − L · n ( R I OH ·R + VCC 1 + 0.7 ) However, the formula for t2 differs with the excitation method. 2 phase excitation t2 = 2 fclock – (t1+t3) 1-2 phase excitation t2 = 3 fclock – t1 W1-2 phase excitation t2 = 7 – t1 fclock 2W1-2 phase excitation 4W1-2 phase excitation t2 = 15 – t1 fclock IOH t3 t1 t2 A13270 Motor Phase Current Model Figure (2 Phase Excitation) fclock Vsat Vdf IOH t1 t2 t3 : CLK input frequency (Hz) : The voltage drop of the power MOSFET and the current detection resistor (V) : The voltage drop of the body diode and the current detection resistor (V) : Phase current peak value (A) : Phase current rise time (s) VCC1 : Supply voltage applied to the motor (V) : Constant-current operating time (s) L : Motor inductance (H) : Phase switching current regeneration time (s) R : Motor winding resistance (Ω) No.7441-16/19 STK672-060-E Determine θc-a for the heat sink from the average power loss determined in the previous item. Tc max: Hybrid IC substrate temperature (°C) Tc max - Ta [°C/W] θc-a = Ta: Application internal temperature (°C) Pd EX PdEX: Hybrid IC internal average loss (W) Determine θc-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below. The ambient temperature of the device will vary greatly according to the air flow conditions within the application. Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum plate side) will never exceed a Tc max of 105°C, whatever the operating conditions are. 20 θc-a - Pd Heat sink thermal resistance, θc-a - °C/W Heat sink thermal resistance, θc-a - °C/W θc-a= Tc max -- Ta (°C/W) Pd Tc max=105°C bie am ed nte ure ara rat Gu mpe te 2 θc-a - S 2m mA l pl at e (fla t bl ack 16 10 7 5 (no Vertical standing type Natural convection air cooling sur f ace fin ish ) ) 12 sur fac 8 60 °C 4 40° C 3 e fi nis h 50°C nt 2 0 0 No. Fin 23.0 (°C/W) 2 4 6 8 10 12 14 16 1.0 ITF02276 No. Fin 23.0 (°C/W) 10 2 3 5 7 100 2 3 5 IC internal average power loss, Pd - W Heat sink surface area, S - cm2 ITF02277 Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss from the thermal resistance of the hybrid IC substrate, namely 23°C/W. For a Tc max of 105°C at an ambient temperature of 50°C PdEX = 105 - 50 = 2.3W 23 PdEX = 105 - 40 = 2.8W 23 For a Tc max of 105°C at an ambient temperature of 40°C This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (See ΔTc – Pd curve in the graph on page 19.) The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal resistance θj-c. Tj = Tc + θj-c × Pds (°C) Here, we determine Pds, the loss for each transistor, by determining PdEX in each excitation mode. Pds = PdEX/4 The steady-state thermal resistance θj-c of a power MOSFET is 18°C/W. No.7441-17/19 STK672-060-E 60 fc - VCC2 60 fc - Tc 55 55 PWM frequency, fc - kHz 50 PWM frequency, fc - kHz 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 50 45 45 40 40 35 35 30 4.0 30 0 20 40 60 80 100 120 140 Supply voltage, VCC2 - V 2.0 1.8 ITF02278 1.4 Substrate temperature, Tc - °C ITF02279 Vsat - IOH Vdf - IOH FET diode forward voltage, Vdf - V Output saturation voltage, Vsat - V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.2 1.0 25° Tc= C °C 05 =1 Tc C 25° 0.8 ° 105 C 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Motor current, IOH - A 1.2 ITF02280 1.2 1.1 IOH - VCC1 Motor current, IOH - A ITF02281 IOH - Tc Motor current=1.0A 1.0 Motor current=1.0A 1.0 Motor current, IOH - A Motor current, IOH - A 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.8 0.6 Motor current=0.5A Motor current=0.5A 0.4 0.2 Vref=0V 15 20 25 30 35 40 45 Vref=0V 0 10 20 30 40 50 60 70 80 90 100 110 0 10 Motor supply voltage, VCC1 - V 500 ITF02282 350 Substrate temperature, Tc - °C ITF02283 IVref - Vref IVref - Tc Motor current=1.0A Reference voltage input current, IVref - μA 450 400 350 300 250 200 150 100 50 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Reference voltage input current, IVref - μA 300 250 200 Motor current=0.5A 150 100 50 0 0 20 40 60 80 100 120 ITF02285 Reference voltage, Vref - V ITF02284 Substrate temperature, Tc - °C No.7441-18/19 STK672-060-E 3.0 Vref - IOH Substrate temperature rise, ΔTc - °C 40 35 30 25 ΔTc - PPS 2e 2.5 Reference voltage, Vref - V x VCC1=24V, VCC2=5V DC Test motor: PK244-01B R=3.5Ω/L=3.3mH No heat sink, motor current=1A 2.0 2W1-2ex 20 15 10 5 0 100 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7 100k ITF02287 Motor current, IOH - A 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 ΔTc - Pd(typ) ITF02286 CLK frequency, PPS - Hz Substrate temperature rise, ΔTc - °C 5 ITF02288 Power dissipation, Pd - W SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2008. Specifications and information herein are subject to change without notice. PS No.7441-19/19