SMG2340N

SMG2340N Elektronische Bauelemente 5.2 A, 40 V, RDS(ON) 43 m N-Channel Enhancement Mode Mos.FET RoHS Compliant Product A suffix of “-C” specifies halogen and lead-free DESCRIPTION These miniature surface mount MOSFETs utilize a High Cell Density trench process to provide Low RDS(on) and ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable and battery-powered products such as computers, printer , PCMCIA cards, cellular and cordless telephones. A 3 SC-59 L 3 Top View 1 2 CB 1 2 K E D FEATURES     Low RDS(on) provides higher efficiency and extends battery life. Low thermal impedance copper leadframe SC-59 saves board Space. Fast switching speed. High performance trench technology. F G H J REF. A B C D E F Millimeter Min. Max. 2.70 3.10 2.25 3.00 1.30 1.70 1.00 1.40 1.70 2.30 0.35 0.50 REF. G H J K L Millimeter Min. Max. 0.10 REF. 0.40 REF. 0.10 0.20 0.45 0.55 0.85 1.15 PACKAGE INFORMATION Package SC-59 MPQ 3K LeaderSize 7’ inch 1 3 2 ABSOLUTE MAXIMUM RATINGS(TA=25°C unless otherwise specified) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current 1 Pulsed Drain Current Continuous Source Current (Diode Conduction) 1 Power Dissipation 1 Operating Junction and Storage Temperature Range Maximum Junction to Ambient 1 Notes 1 2 Surface Mounted on 1” x 1” FR4 Board. Pulse width limited by maximum junction temperature. 2 Symbol VDS VGS ID @ TA=25°C ID @ TA=70°C Ratings 40 ±20 5.2 4.1 30 1.6 1.3 0.8 -55 ~ 150 100 166 Unit V V A A A A W W °C °C / W ID IDM IS PD @ TA=25°C PD @ TA=70°C PD Tj, Tstg Thermal Resistance Data t ≦ 5 sec Steady State RJA http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 30-Dec-2010 Rev. A Page 1 of 2 SMG2340N Elektronische Bauelemente 5.2 A, 40 V, RDS(ON) 43 m N-Channel Enhancement Mode Mos.FET ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Gate-Threshold Voltage Gate-Body Leakage Symbol Min. VGS(th) IGSS 1.0 - Typ. Max. 40 0.7 ±100 1 Unit V nA Test Conditions VDS=VGS, ID= 250uA VDS= 0V, VGS= 20V VDS= 32V, VGS= 0V Zero Gate Voltage Drain Current IDSS 25 43 uA VDS= 32V, VGS= 0V, TJ= 55°C A VDS = 5V, VGS= 10V VGS= 10V, ID= 5.2A mΩ 64 S V VGS= 4.5V, ID= 3.7A VDS= 15V, ID= 5.2A IS= 2.3A, VGS= 0V On-State Drain Current 1 ID(on) 20 - Drain-Source On-Resistance 1 RDS(ON) Forward Transconductance 1 Diode Forward Voltage gfs VSD - Dynamic 2 Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Notes 1 2 Pulse test：PW ≦ 300 us duty cycle ≦ 2%. Guaranteed by design, not subject to production testing. Qg Qgs Qgd Td(on) Tr Td(off) Tf - 4.0 1.1 1.4 16 5 23 3 nS VDD= 25V, VGEN= 10V, RL= 25, ID= 1A nC VDS= 15V, VGS= 4.5V, ID= 5.2A http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 30-Dec-2010 Rev. A Page 2 of 2