SSD60N04-12D

SSD60N04-12D Elektronische Bauelemente N-Ch Enhancement Mode Power MOSFET 53A, 40V, RDS(ON) 12mΩ RoHS Compliant Product A suffix of “-C” specifies halogen free DESCRIPTION These miniature surface mount MOSFETs utilize a high cell density trench process to provide low RDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable And battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. TO-252(D-Pack) FEATURES     Low RDS(on) provides higher efficiency and extends battery life. Low thermal impedance copper leadframe DPAK saves board space. Fast switching speed. High performance trench technology. A B C D PRODUCT SUMMARY VDS(V) 40 PRODUCT SUMMARY RDS(on) m( 12@VGS= 10V 14@VGS= 4.5V K GE HF ID(A) 53 49  Gate  Drain M J N O P REF.  Source A B C D E F G H Millimeter Min. Max. 6.4 6.8 5.20 5.50 2.20 2.40 0.45 0.58 6.8 7.3 2.40 3.0 5.40 6.2 0.8 1.20 REF. J K M N O P Millimeter Min. Max. 2.30 REF. 0.70 0.90 0.50 1.1 0.9 1.6 0 0.15 0.43 0.58 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) PARAMETER SYMBOL RATINGS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current b a a UNIT V V A A A W °C °C / W °C / W VDS VGS ID @TA=25℃ IDM IS PD @TA=25℃ TJ, TSTG RθJA RθJC a 40 ±20 53 40 30 50 -55 ~ 175 50 3.0 Continuous Source Current (Diode Conduction) Total Power Dissipation Operating Junction and Storage Temperature Range Maximum Thermal Resistance Junction-Ambient a Maximum Thermal Resistance Junction-Case Notes： a. Surface Mounted on 1” x 1” FR4 Board. b. Pulse width limited by maximum junction temperature. THERMAL RESISTANCE RATINGS http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 10-Jun-2010 Rev.A Page 1 of 2 SSD60N04-12D Elektronische Bauelemente N-Ch Enhancement Mode Power MOSFET 53A, 40V, RDS(ON) 12mΩ ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) PARAMETER Gate-Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current a Drain-Source On-Resistance a Forward Transconductance a Diode Forward Voltage SYMBO MIN. TYP. MAX. UNIT Static VGS(th) IGSS IDSS ID(on) RDS(ON) gfs VSD 1.0 34 22 1.1 ±100 1 25 12 14 V nA μA A mΩ S V TEST CONDITIONS VDS= VGS, ID = 250 μA VDS = 0V, VGS= 20V VDS= 32V, VGS= 0V VDS= 32V, VGS= 0V, TJ=55°C VDS = 5V, VGS= 10V VGS= 10V, ID= 53 A VGS= 4.5V, ID= 49 A VDS= 15V, ID= 53 A IS= 34 A, VGS= 0 V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Qg Qgs Qgd Td(on) Tr Td(off) Tf 4.0 1.1 1.4 16 5 23 3 nS VDD= 25 V ID= 34 A VGEN = 10 V RL= 25  nC VDS = 15 V VGS = 4.5 V ID = 53 A Notes a. Pulse test：Pulse width ≦ 300 μs, duty cycle ≦ 2％. b. Guaranteed by design, not subject to production testing. http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 10-Jun-2010 Rev.A Page 2 of 2