SSP7421P

SSP7421P Elektronische Bauelemente -20 A, -20 V, RDS(ON) 8.4 m P-Channel Enhancement MOSFET RoHS Compliant Product A suffix of “-C” specifies halogen & lead-free SOP-8PP DESCRIPTION These miniature surface mount MOSFETs utilize a high cell density trench process to provide low RDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. B D C θ e E FEATURES     Low RDS(on) provides higher efficiency and extends battery life. Low thermal impedance copper leadframe SOP-8PP saves board space. Fast switching speed. High performance trench technology. d A b g F G Millimeter Min. Max. 1.00 1.10 5.70 5.80 0.20 0.30 3.61 3.98 5.40 6.10 0.08 0.20 3.60 3.99 Millimeter Min. Max. 0° 12° 0.33 0.51 1.27BSC 1.35 1.75 1.10 - PRODUCT SUMMARY PRODUCT SUMMARY VDS(V) -20 RDS(on) (m 8.4@VGS= -4.5V 10.4@VGS= -2.5V ID(A) -20 -18  Gate REF. A B C D E F G REF. θ b d e g  Drain  Source ABSOLUTE MAXIMUM RATINGS AND THERMAL DATA(TA = 25°C unless otherwise specified) PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current A Pulsed Drain Current Continuous Source Current (Diode Conduction) A Power Dissipation A B SYMBOL VDS VGS TA=25°C TA=70°C ID IDM IS RATING -20 ±8 -20 -17 ±50 -2.1 5.0 3.2 -55 ~ 150 25 65 UNIT V V A A A W °C °C / W TA=25°C PD TA=70°C Operating Junction and Storage Temperature Range TJ, TSTG THERMAL RESISTANCE DATA t≦10 sec Maximum Junction to Ambient A RθJA Steady-State Notes a. b. Surface Mounted on 1” x 1” FR4 Board. Pulse width limited by maximum junction temperature. http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 27-Jul-2010 Rev. A Page 1 of 2 SSP7421P Elektronische Bauelemente -20 A, -20 V, RDS(ON) 8.4 m P-Channel Enhancement MOSFET ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise specified) PARAMETER SYMBO MIN TYP MAX UNIT Static Gate-Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current A Drain-Source On-Resistance A Forward Transconductance A Diode Forward Voltage VGS(th) IGSS IDSS ID(ON) RDS(ON) gFS VSD -0.4 -50 70 -0.6 ±100 TEST CONDITIONS V nA μA A mΩ S V VDS = VGS, ID = -250μA VDS = 0V, VGS= ±8V VDS = -16V, VGS= 0V VDS = -16V, VGS= 0V, TJ=55°C VDS = -4.5V, VGS= -10V VGS= -4.5V, ID = -13.5A VGS= -2.5V, ID = -12A VDS= -15V,,ID = -11.5A IS= 2.5A, VGS= 0V -1 -5 8.4 10.4 - Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Notes a. b. Pulse test：PW ≦ 300 us duty cycle ≦ 2%. Guaranteed by design, not subject to production testing. Qg Qgs Qgd Td(ON) Tr Td(OFF) Tf - 66 13 17 20 23 289 134 nC ID= -13.5A VDS= -10V VGS= -4.5V ID= -1A, VDD= -10V nS VGEN= -4.5V RL= 6Ω http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. 27-Jul-2010 Rev. A Page 2 of 2