ACS8510

ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Description D escription The ACS8510 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and frame synchronization clocks. The ACS8510 is fully compliant with the required specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 devices can be used together in a Master/Slave configuration mode allowing system protection against a single ACS8510 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8510 supports IEEE 1149.1 JTAG boundary scan. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. Block Diagram B lock Figure 1. Simple Block Diagram 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8kHz 2kHz 4kHz N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz Synchronous Equipment Timing Source for SONET or SDH Network Elements FINAL Features F eatures •Suitable for Stratum 3E*, 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications •Meets AT&T, ITU-T, ETSI and Telcordia specifications •Accepts 14 individual input reference clocks •Generates 11 output clocks •Supports Free-run, Locked and Holdover modes of operation •Robust input clock source quality monitoring on all inputs •Automatic ‘hit-less’ source switchover on loss of input •Phase build out for output clock phase continuity during input switchover and mode transitions •Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM •Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz •Support for Master/Slave device configuration alignment and hot/standby redundancy •IEEE 1149.1 JTAG Boundary Scan •Single +3.3 V operation, +5 V I/O compatible •Operating temperature (ambient) -40°C to +85°C •Available in 100 pin LQFP package * Meets Holdover requirements, lowest bandwidth 0.1 Hz. Input Ports TOUT4 selector Divider PFD Digital Loop Filter Output Ports DTO DPLL/Freq. Synthesis 14xSEC Monitors 9xSEC TOUT0 selector MFrSync TCK TDI TMS TRST TDO PFD Divider Digital Loop Filter DTO APLL Frequency Dividers 1 x AMI 6 x TTL 2 x PECL/LVDS Programmable: 64/8kHz 1.544/2.048MHz 3.088/4.096MHz 6.176/8.182MHz 12.352/16.384MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz 311.04MHz 2kHz MFrSync 8kHz FrSync DPLL/Freq. Synthesis Chip Clock Generator Priority Table FrSync MFrSync IEEE 1149.1 JTAG Register Set Microprocessor Port TCXO (*OCXO) Revision 2.00/September 2003 Semtech Corp. www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Contents Table of Cont ents List of Sections Description ................................................................................................................................................................................................ 1 Block Diagram ........................................................................................................................................................................................... 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 5 Pin Descriptions ........................................................................................................................................................................................ 6 Functional Description ............................................................................................................................................................................. 9 Local Oscillator Clock ................................................................................................................................................................................... 10 ITU and ETSI Specification ............................................................................................................................................................. 10 Telcordia GR-1244 CORE Specification ....................................................................................................................................... 10 Crystal Frequency Calibration ...................................................................................................................................................... 10 Input Interfaces ............................................................................................................................................................................................. 10 Over-Voltage Protection .............................................................................................................................................................................. 10 Input Reference Clock Ports ....................................................................................................................................................................... 11 Input Wander and Jitter Tolerance .............................................................................................................................................................. 9 Output Clock Ports ........................................................................................................................................................................................ 12 Low Speed Output Clock (DPLL2) ................................................................................................................................................. 12 High Speed Output Clock (DPLL1) ............................................................................................................................................... 12 Frame Sync and Multi-Frame Sync Clocks (Part of DPLL1) ................................................................................................... 13 Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 13 Output Wander and Jitter ............................................................................................................................................................................ 13 Phase Variation ............................................................................................................................................................................................. 18 Phase Build Out ............................................................................................................................................................................................. 21 Microprocessor Interface ............................................................................................................................................................................. 21 Motorola Mode ................................................................................................................................................................................ 21 Intel Mode ........................................................................................................................................................................................ 21 Multiplexed Mode ........................................................................................................................................................................... 21 Serial Mode ...................................................................................................................................................................................... 21 EPROM Mode ................................................................................................................................................................................... 21 Register Set ..................................................................................................................................................................................... 22 Configuration Registers ................................................................................................................................................................. 22 Status Registers .............................................................................................................................................................................. 22 Register Access ............................................................................................................................................................................... 22 Interrupt Enable and Clear ......................................................................................................................................................................... 22 Register Map .................................................................................................................................................................................................. 23 Register Map Description ........................................................................................................................................................................... 27 Selection of Input Reference Clock Source ............................................................................................................................................. 36 Forced Control Selection ............................................................................................................................................................... 37 Automatic Control Selection ........................................................................................................................................................ 37 Ultra Fast Switching ....................................................................................................................................................................... 37 External Protection Switching ..................................................................................................................................................... 38 Clock Quality Monitoring ............................................................................................................................................................................. 38 Activity Monitoring ....................................................................................................................................................................................... 39 Frequency Monitoring .................................................................................................................................................................................. 39 Modes of Operation ...................................................................................................................................................................................... 41 Free-run mode ................................................................................................................................................................................. 41 Pre-Locked mode ............................................................................................................................................................................ 41 Locked mode .................................................................................................................................................................................... 41 Lost_Phase mode ........................................................................................................................................................................... 41 Holdover mode ................................................................................................................................................................................ 42 Pre-Locked(2) mode ........................................................................................................................................................................ 42 Protection Facility ........................................................................................................................................................................................ 43 Alignment of Priority Tables in Master and Slave ACS8510 ................................................................................................. 44 Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 ........... 45 Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 ....................................... 45 JTAG .................................................................................................................................................................................................................. 45 PORB ................................................................................................................................................................................................................ 45 FINAL Electrical Specification .......................................................................................................................................................................... 48 Revision 2.00/September 2003 Semtech Corp. 2 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DC Characteristics: AMI Input/Output Port ........................................................................................................................................... 54 Microprocessor Interface Timing .......................................................................................................................................................... 63 Motorola Mode .............................................................................................................................................................................................. 63 Intel Mode ....................................................................................................................................................................................................... 65 Multiplexed Mode ......................................................................................................................................................................................... 67 Serial Mode .................................................................................................................................................................................................... 69 EPROM Mode ................................................................................................................................................................................................. 71 Package Information .............................................................................................................................................................................. 72 Thermal Conditions ....................................................................................................................................................................................... 73 Application Information .......................................................................................................................................................................... 74 Revision History ...................................................................................................................................................................................... 75 Ordering Information .............................................................................................................................................................................. 76 Disclaimers ..................................................................................................................................................................................................... 76 List of Figures Figure 1. Simple Block Diagram ............................................................................................................................................................. 1 Figure 2. ACS8510 Pin Diagram ............................................................................................................................................................ 5 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) ................................................................................................................... 15 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) .......................................................................................................................... 16 Figure 5. Wander and Jitter Measured Transfer Characteristics ....................................................................................................... 18 Figure 6. Maximum Time Interval Error of TOUT0 output port ........................................................................................................... 20 Figure 7. Time Deviation of TOUT0 output port ................................................................................................................................... 20 Figure 8. Phase error accumulation of TOUT0 output port in Holdover mode .................................................................................. 20 Figure 9. Inactivity and Irregularity Monitoring ................................................................................................................................... 38 Figure 10. Master-Slave Schematic ..................................................................................................................................................... 46 Figure 11. Automatic Mode Control State Diagram ........................................................................................................................... 47 Figure 12. Recommended Line Termination for PECL Input/Output Ports ...................................................................................... 51 Figure 13. Recommended Line Termination for LVDS Input/Output Ports ...................................................................................... 53 Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface ............................................................................................ 55 Figure 15. AMI Input and Output Signal Levels .................................................................................................................................. 55 Figure 16. Recommended Line Termination for AMI Output/Output Ports ..................................................................................... 56 Figure 17. JTAG Timing ............................................................................................................................................................................ 61 Figure 18. Input/Output Timing ............................................................................................................................................................ 62 Figure 19. Read Access Timing in MOTOROLA Mode ........................................................................................................................ 63 Figure 20. Write Access Timing in MOTOROLA Mode ....................................................................................................................... 64 Figure 21. Read Access Timing in INTEL Mode ................................................................................................................................... 65 Figure 22. Write Access Timing in INTEL Mode .................................................................................................................................. 66 Figure 23. Read Access Timing in MULTIPLEXED Mode .................................................................................................................... 67 Figure 24. Write Access Timing in MULTIPLEXED Mode ................................................................................................................... 68 Figure 25. Read Access Timing in SERIAL Mode ................................................................................................................................ 69 Figure 26. Write Access Timing in SERIAL Mode ............................................................................................................................... 70 Figure 27. Access Timing in EPROM Mode ......................................................................................................................................... 71 Figure 28. LQFP Package ...................................................................................................................................................................... 72 Figure 29. Typical 100 Pin LQFP Footprint ......................................................................................................................................... 73 Figure 30. Simplified Application Schematic ...................................................................................................................................... 74 Revision 2.00/September 2003 Semtech Corp. 3 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Tables List of Tables Table 1. Power Pins .................................................................................................................................................................................... 6 Table 2. No Connections ............................................................................................................................................................................ 6 Table 3. Other Pins ..................................................................................................................................................................................... 7 Table 4. Input Reference Source Selection and Priority Table .......................................................................................................... 12 Table 5. Input ReferenceSource Jitter Tolerance ................................................................................................................................. 14 Table 6. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 15 Table 7. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 16 Table 8. Output Reference Source Selection Table ............................................................................................................................. 17 Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 17 Table 10. Microprocessor Interface Mode Selection ......................................................................................................................... 21 Table 11. Register Map .......................................................................................................................................................................... 23 Table 12. Register Map Description ..................................................................................................................................................... 27 Table 13. Master-Slave Relationship .................................................................................................................................................... 46 Table 14. Absolute Maximum Ratings .................................................................................................................................................. 48 Table 15. Operating Conditions ............................................................................................................................................................. 48 Table 16. DC Characteristics: TTL Input Port ....................................................................................................................................... 48 Table 17. DC Characteristics: TTL Input Port with Internal Pull-up .................................................................................................... 49 Table 18. DC Characteristics: TTL Input Port with Internal Pull-down ............................................................................................... 49 Table 18. DC Characteristics: TTL Output Port .................................................................................................................................... 49 Table 20. DC Characteristics: PECL Input/Output Port ...................................................................................................................... 50 Table 21. DC Characteristics: LVDS Input/Output Port ...................................................................................................................... 52 Table 22. DC Characteristics: AMI Input/Output Port ........................................................................................................................ 54 Table 23. DC Characteristics: Ouput Jitter Generation (Test Definition G.813) ............................................................................. 57 Table 24. DC Characteristics: Ouput Jitter Generation (Test Definition G.812) ............................................................................. 57 Table 25. DC Characteristics: Ouput Jitter Generation (Test Definition ETS-300-462-3) .............................................................. 58 Table 26. DC Characteristics: Ouput Jitter Generation (Test Definition GR-253-CORE) ............................................................... 58 Table 27. DC Characteristics: Ouput Jitter Generation (Test Definition AT&T 62411) ................................................................... 59 Table 28. DC Characteristics: Ouput Jitter Generation (Test Definition G.742) .............................................................................. 59 Table 29. DC Characteristics: Ouput Jitter Generation (Test Definition TR-NWT-000499) ........................................................... 59 Table 30. DC Characteristics: Ouput Jitter Generation (Test Definition GR-1244-CORE) ............................................................. 60 Table 31. JTAG Timing (for use with Figure 17) ................................................................................................................................... 61 Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) ................................................................................. 63 Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) ................................................................................ 64 Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) ............................................................................................ 65 Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) ........................................................................................... 66 Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) ............................................................................. 67 Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) ............................................................................. 68 Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) ......................................................................................... 70 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70 Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71 Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73 FINAL Revision 2.00/September 2003 Semtech Corp. 4 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Pin Diagram P in Figure 2. ACS8510 Pin Diagram FINAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AGND TRST IC NC AGND VA1+ TMS INTREQ TCK REFCLK DGND VD+ VD+ DGND DGND VD+ NC SRCSW VA2+ AGND TDO IC TDI I1 I2 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFF VDD_DIFF TO6POS TO6NEG TO7POS TO7NEG GND_DIFF VDD_DIFF I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGND VDD 1 ACS8510 SDH/SONET SETS Rev 2.1 NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SONSDHB MSTSLVB IC IC IC TO9 TO5 TO4 DGND VDD TO3 TO2 TO1 DGND VDD VDD DGND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGND VDD UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 Revision 2.00/September 2003 Semtech Corp. 5 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Pin Descriptions P in Table 1. Power Pins PIN 12, 13, 16 26 33, 39 FINAL SYMB OL VD+ VAMI+ VDD_DIFF IO IO P P P T YPE - N A M E /DE S CR I P T I O N S u p p l y v o l t a g e : Digital supply to gates in analog section, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Digital supply to AMI output, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Digital supply for differential por ts, +3.3 Volts. +/- 10% V D D 5 : Digital supply for +5 Volts tolerance to input pins. Connect to +5 Volts (+/- 10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. S u p p l y v o l t a g e : Digital supply to logic, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Analog supply to clock multipying PLL, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Analog supply to output PLL, +3.3 Volts. +/- 10% S u p p l y G r o u n d : Digital ground for logic 44 VDD5 P - 50, 61, 85, 86, 91 6 19 11, 14, 15, 49, 62, 84, 87, 92 29 32, 38 1, 5, 20 VDD VA1+ VA2+ DGN D P P P P - GN D_AMI GN D_DIFF AGN D P P P - S u p p l y G r o u n d : Digital ground for AMI output S u p p l y G r o u n d : Digital ground for differential por ts S u p p l y G r o u n d : Analog ground Table 2. No Connections PIN 4, 17 3, 22, 96, 97,98 SYMB OL NC IC IO IO - T YPE - N A M E /DE S CR I P T I O N N o t C o n n e c t e d : Leave to Float I n t e r n a l l y C o n n e c t e d : Leave to Float Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor Revision 2.00/September 2003 Semtech Corp. 6 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 3. Other Pins PIN 2 FINAL N A M E /DE S CR I P T I O N J TA G C o n t r o l R e s e t I n p u t : TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device op eration (JTAG logic transp arent). If not used connect to GN D or leave floating. J TA G Te s t M o d e S e l e c t : Boundary Scan enable. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. I n t e r r u p t R e q u e s t : Active high software Interrup t outp ut J TA G C l o c k : Boundary Scan clock inp ut. If not used connect to GN D or leave floating. This p in may require a cap acitor p laced between the p in and the nearest GN D, to reduce noise p ickup . A value of 10 p F should be adequate, but the value is dep endent on PCB layout. R e f e r e n c e C l o c k : 12.8 MHz (refer to section headed Local Oscillator Clock) S o u r c e S w i t c h i n g : Force Fast Source Switching J TA G O u t p u t : Serial test data outp ut. Up dated on falling edge of TCK. If not used leave floating. J TA G I n p u t : Serial test data Inp ut. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. I n p u t r e f e r e n c e 1 : comp osite clock 64 kHz + 8 kHz I n p u t r e f e r e n c e 2 : comp osite clock 64 kHz + 8 kHz O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz negative p ulse O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz p ositive p ulse O u t p u t r e f e r e n c e 10 : 8 kHz Frame Sync clock outp ut (square wave) O u t p u t r e f e r e n c e 1 1 : 2 kHz Multi-Frame Sync clock outp ut (square wave) O u t p u t r e f e r e n c e 6 : default 38.88 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04 MHz. Default typ e LVDS. O u t p u t r e f e r e n c e 7 : default 19.44 MHz. Also 51.84 MHz, 77.76 MHz, 155.52 MHz. Default typ e PECL. I n p u t r e f e r e n c e 5 : default 19.44 MHz, default typ e LVDS I n p u t r e f e r e n c e 6 : default 19.44 MHz, default typ e PECL SYMB OL TRST IO IO I T YPE T T LD 7 8 T MS IN T R E Q I O T T LU TTL CMOS 9 TCK I T T LD 10 18 21 23 24 25 27 28 30 31 34 35 36 37 40 41 42 43 REFCLK SRCSW TDO TDI I1 I2 TO8N EG TO8POS FrSync MFrSync TO6POS TO6N EG TO7POS TO7N EG I5POS I5N EG I6POS I6N EG I I O I I I O O O O TTL T T LD TTL CMOS T T LU A MI A MI A MI A MI TTL CMOS TTL CMOS LVDS PECL PECL LVDS LVDS PECL PECL LVDS O O I I Revision 2.00/September 2003 Semtech Corp. 7 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN 45 46 47 48 51 52 53 54 55 56 57 58 - 60 63 - 69 70 FINAL N A M E /DE S CR I P T I O N S y n c h r o n i s e 2 k H z : Connect to 2 kHz Multi-Frame Sync outp ut of p ar tner ACS8510 in redundancy system I n p u t r e f e r e n c e 3 : p rogrammable, default 8 kHz I n p u t r e f e r e n c e 4 : p rogrammable, default 8 kHz I n p u t r e f e r e n c e 7 : p rogrammable, default 19.44 MHz I n p u t r e f e r e n c e 8 : p rogrammable, default 19.44 MHz I n p u t r e f e r e n c e 9 : p rogrammable, default 19.44 MHz I n p u t r e f e r e n c e 10 : p rogrammable, default 19.44 MHz. I n p u t r e f e r e n c e 1 1 : p rogrammable, default (master mode)1.544/2.048 MHz, default (slave mode) 6.48 MHz I n p u t r e f e r e n c e 1 2 : p rogrammable, default 1.544/2.048 MHz. I n p u t r e f e r e n c e 1 3 : p rogrammable, default 1.544/2.048 MHz. I n p u t r e f e r e n c e 14 : p rogrammable, default 1.544/2.048 MHz. M i c r o p r o c e s s o r s e l e c t : Configures the inter face for a p ar ticular microp rocessor typ e. M i c r o p r o c e s s o r I n t e r f a c e A d d r e s s : Address bus for the microp rocessor inter face registers. A(0) is SDI in Serial mode. C h i p S e l e c t ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to enable the microp rocessor inter face. W r i t e ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a write cycle. In Motorola mode, WRB = 1 for Read. R e a d ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a read cycle. A d d r e s s L a t c h E n a b l e : This p in becomes the address latch enable from the microp rocessor. When this p in transitions from Low to High, the address bus inp uts are latched into the internal registers. ALE = SCLK in Serial mode. P o w e r O n R e s e t : Master reset. If PORB is forced Low, all internal states are reset back to default values. R e a d y / D a t a a c k n o w l e d g e : This p in is asser ted High to indicate the device has comp leted a read or write op eration. A d d r e s s / D a t a : Multip lexed data/address bus dep ending on the microp rocessor mode selection. AD(0) is SDO in Serial mode. 8 www.semtech.com SYMB OL SYN C2K I3 I4 I7 I8 I9 I10 I11 I12 I13 I14 UPSEL(2:0) A(6:0) CSB IO IO I I I I I I I I I I I I I I T YPE T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LD T T LU 71 WRB I T T LU 72 RDB I T T LU 73 A LE I T T LD 74 75 76 - 83 PORB RDY AD(7:0) I O IO T T LU TTL CMOS T T LD Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN 88 89 90 93 94 95 FINAL N A M E /DE S CR I P T I O N O u t p u t r e f e r e n c e 1 : default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz O u t p u t r e f e r e n c e 2 : default 38.88 MHz. Also Dig2 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz O u t p u t r e f e r e n c e 3 : 19.44 MHz - fixed. O u t p u t r e f e r e n c e 4 : 38.88 MHz - fixed. O u t p u t r e f e r e n c e 5 : 77.76 MHz - fixed. O u t p u t r e f e r e n c e 9 : 1.544/2.048 MHz. (T4 BITS) M A S T E R S L AV E B : Master slave select: sets the initial p ower up state (or state after a PORB) of the Master/Slave selection register, addr 34, bit 1. The register state can be changed after p ower up by software. S O N E T S D H B : SON ET or SDH frequency select: sets the initial p ower up state (or state after a PORB) of the SON ET/SDH frequency selection registers, addr 34h, bit 2 and addr 38, bits 5 and 6. The register states can be changed after p ower up by software. SYMB OL TO1 TO2 TO3 TO4 TO5 TO9 IO IO O O O O O O T YPE TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS 99 MSTSLVB I T T LU 100 SON SDHB I T T LD F unctional Description The ACS8510 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8510 generates a stable, lownoise clock signal from an internal oscillator. In Locked mode, the ACS8510 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8510 generates a stable, low-noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.812, G.813, G.823, and GR-1244-CORE. Revision 2.00/September 2003 Semtech Corp. 9 The ACS8510 supports all three types of reference clock source: recovered line clock (TIN1), PDH network synchronization timing (TIN2) and node synchronization (TIN3). The ACS8510 generates independent TOUT0 and TOUT4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. The ACS8510 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8510 supports protection. Two ACS8510 devices can be configured to provide protection against a single ACS8510 failure. The protection maintains alignment of the two ACS8510 devices (Master and Slave) and ensures that both ACS8510 devices maintain the same priority table, choose the same www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS reference input and generate the TOUT0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8510 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator Clock The Master system clock on the ACS8510 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperaturerelated parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70 °C. Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50 °C. ITU and ETSI Specification Tolerance: Drift*: +/- 4.6 ppm over 20 year life time. +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.01 ppm/day @ constant temp. +/- 1 ppm over temp. range 0 to +70 °C *Frequency drift over supply range of +2.7V to +3.3V. FINAL Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) Input Interfaces The ACS8510 supports up to fourteen input reference clock sources from input types TIN1, TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and AMI buffer I/O technologies. These interface technologies support +3.3 V and +5 V operation. Over-Voltage Protection The ACS8510 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book). www.semtech.com Telcordia GR-1244 CORE Specification Tolerance: Drift*: +/- 4.6 ppm over 20 year life time. +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.04 ppm/day @ constant temp. +/- 0.28 ppm over temp. range 0 to +50 °C *Frequency drift over supply range of +2.7V to +3.3V. Please contact Semtech for information on crystal oscillator suppliers. Revision 2.00/September 2003 Semtech Corp. 10 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Input Reference Clock Ports Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pin-selectable (using the SONSDHB pin). Specific frequencies and priorities are set by configuration. Although each input port is shown as belonging to one of the types, TIN1, TIN2 or TIN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are: • 2 kHz • 4 kHz • 8 kHz (and N x 8 kHz) • 1.544 MHz (SONET)/2.048 MHz (SDH) • 6.48 MHz, • 19.44 MHz, • 25.92 MHz, • 38.88 MHz, • 51.84 MHz, • 77.76 MHz. Revision 2.00/September 2003 Semtech Corp. 11 FINAL The frequency selection is programmed via the cnfg_ref_source_frequency r egister. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the ‘DivN’ feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0100s) (2) all refs evaluated & at least one ref valid Reference sources are flagged as 'valid' when active, 'in-band' and have no phase alarm set. (4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] pre-locked w ait for up to 100s (state 110) All sources are continuously checked for activity and frequency. Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds (5) selected ref phase locked locked keep ref (state 100) (10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] (6) no valid standby ref & main ref invalid (8) phase regained within 100s (7) phase lost on main ref pre-locked2 w ait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) Lost phase w ait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) holdover select ref (state 010) (15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid Revision 2.00/September 2003 Semtech Corp. 47 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Electrical Specification E lectrical Note: Important Note The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 14. Absolute Maximum Ratings PA RA METER Sup p ly Voltage VDD, VD+, VA1+,VA2+ Inp ut Voltage (non-sup p ly p ins) Outp ut Voltage (non-sup p ly p ins) Ambient Op erating Temp erature Range Storage Temp erature FINAL SYMB OL VDD Vin Vout TA Tstor M IN IN -0.5 -40 -50 M AX AX 3.6 5.5 5.5 +85 +150 U N ITS V V V °C °C Table 15. Operating Conditions PA RA METER Power Sup p ly (dc voltage) VDD, VD+,VA1+, VA2+, VAMI+, VDD_DIFF Power Sup p ly (dc voltage) VDD5 Ambient temp erature Range Sup p ly current (Typ ical - one 19 MHz outp ut) SYMB OL VDD MIN 3.0 T YP 3.3 MA X 3.6 U N ITS V VDD5 TA IDD PTOT 3.0 -40 - 3.3/5.0 110 360 5.5 +85 200 720 V °C mA mW Total p ower dissip ation Table 16. DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated PA R A M E T E R Vin High Vin Low Inp ut current SYMB OL V ih V il Ii n MIN 2.0 48 T YP - MA X 0.8 10 U N ITS V V µA www.semtech.com Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 17. DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated FINAL PA R A M E T E R Vin High Vin Low Pull-up resistor Inp ut current SYMB OL V ih V il PU Ii n MIN 2.0 30 - T YP - MA X 0.8 80 120 U N ITS V V kΩ µA Table 18. DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated PA R A M E T E R Vin High Vin Low Pull-down resistor Inp ut current SYMB OL V ih V il PD Ii n MIN 2.0 30 - T YP - MA X 0.8 80 120 U N ITS V V kΩ µA Table 19. DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R Vout Low Iol = 4mA Vout High Ioh = 4mA Drive current SYMB OL Vol Voh ID MIN 0 2.4 - T YP - MA X 0.4 U N ITS V V 4 mA Revision 2.00/September 2003 Semtech Corp. 49 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 20. DC Characteristics: PECL Input/Output Port Across all operating conditions, unless otherwise stated FINAL PA R A M E T E R PECL Inp ut Low voltage Differential inp uts (N ote 1) SYMB OL VILPECL VIHPECL VIDPECL VILPECL_S VIHPECL_S MIN VDD-2.5 VDD-2.4 0.1 VDD-2.4 VDD-1.3 T YP - MA X VDD-0.5 VDD-0.4 1.4 VDD-1.5 VDD-0.5 U N ITS V V V V V PECL Inp ut High voltage Differential inp uts (N ote 1) Inp ut Differential voltage PECL Inp ut Low voltage Single ended inp ut (N ote 2) PECL Inp ut High voltage Single ended inp ut (N ote 2) Inp ut High current Inp ut differential voltage VID = 1.4v IIHPECL -10 - +10 µA Inp ut Low current Inp ut differential voltage VID = 1.4v IILPECL -10 - +10 µA PECL Outp ut Low voltage (N ote 3) VOLPECL VOHPECL VODPECL VDD-2.10 VDD-1.25 580 - VDD-1.62 VDD-0.88 900 V V mV PECL Outp ut High voltage (N ote 3) PECL Outp ut Differential voltage (N ote 1) Notes to Table 20 Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 load on each pin to VDD-2 V. i.e. 82 to GND and 130 to VDD. Revision 2.00/September 2003 Semtech Corp. 50 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Figure 12. Recommended Line Termination for PECL Input/Output Ports V DD ZO=50Ω 130R ZO=50Ω 130R V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz I5POS ZO=50Ω 82R 130R T06POS ZO=50Ω 82R 130R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 I5NEG 82R T06NEG 82R GND GND V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω 130R ZO=50Ω 130R V DD I6POS ZO=50Ω 82R 130R T07POS ZO=50Ω 82R 130R 19.44, 51.84, 77.76, 155.52 MHz I6NEG 82R T07NEG 82R GND GND VDD = +3.3 V Revision 2.00/September 2003 Semtech Corp. 51 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Table 21. DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R LVDS Inp ut voltage range Differential inp ut voltage = 100 mV SYMB OL VVRLVDS VDITH VIDLVDS MIN 0 -100 0.1 T YP - MA X 2.40 +100 1.4 U N ITS V mV V LVDS Differential inp ut threshold LVDS Inp ut Differential voltage LVDS Inp ut termination resistance Must be p laced externally across the LVDS+/- inp ut p ins of ACS8510. Resistor should be 100Ω with 5% tolerance R TERM 95 100 105 Ω LVDS Outp ut high voltage (N ote 1) VOHLVDS VOLLVDS VODLVDS 0.885 250 - 1.585 450 V V mV LVDS Outp ut low voltage (N ote 1) LVDS Differential outp ut voltage (N ote 1) LVDS Change in magnitude of differential outp ut voltage for comp limentary states (N ote 1) VDOSLVDS - - 25 mV LVDS outp ut offset voltage Temp erature = 25°C (N ote 1) VOSLVDS 1.125 - 1.275 V Note to Table 21 Note 1. With 100 load between the differential outputs. Revision 2.00/September 2003 Semtech Corp. 52 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Figure 13. Recommended Line Termination for LVDS Input/Output Ports 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω ZO=50Ω I5POS ZO=50Ω 100R T06POS ZO=50Ω 100R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 I5NEG T06NEG 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω ZO=50Ω I6POS ZO=50Ω 100R T07POS ZO=50Ω 100R 19.44, 51.84, 77.76, 155.52 MHz I6NEG T07NEG Revision 2.00/September 2003 Semtech Corp. 53 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS DC Characteristics: AMI Input/Output Port Across all operating conditions, unless otherwise stated FINAL The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative pulses with a peak to peak voltage of 2.0 +/- 0.2 V. The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64 kbit/s centralized clock interface, from ITU G.703. Table 22. DC Characteristics: AMI Input/Output Port PA R A M E T E R Inp ut Pulse width Inp ut Pulse rise/fall time AMI Inp ut voltage high AMI Inp ut voltage middle AMI Inp ut voltage low AMI Outp ut current drive AMI Outp ut high voltage Outp ut current = 20mA SYMB OL t PW tR/F V IH A M I V V IM A M I V V IL A M I IAMIOUT VOH AMI VOLAMI RTEST V MA R K VSPACE MIN 1.56 2.5 1.5 0 VDD - 0.16 0.9 -0.1 T YP 7.8 1.65 110 1.0 0 MA X 14.04 5 VDD + 0.3 1.8 1.4 20 0.16 1.1 0.1 U N ITS us us V V V mA V V Ω V V AMI Outp ut low voltage Outp ut current = 20mA N ominal test load imp edence "Mark" amp litude after transformer "Sp ace" amp litude after transformer The electrical characteristics of 64 kbits/s interface are as follows; Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability. There should be a symmetrical pair carrying the composite timing signal (64 kHz and 8 kHz). The use of transformers is recommended. Over-voltage protection requirement; refer to Recommendation K.41. Code conversion rules; The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals convey the 64 kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the 8 kHz octet phase information by introducing violations in the code rule. The structure of the signals and voltage levels are shown in Figures 14 and 15. Revision 2.00/September 2003 Semtech Corp. 54 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface after suitable input/output transformer (also see Figure 6/G.703) FINAL 15.6us 7.8us + 1.0V IH 1V 2V p -p 0V IM 1V -1.0V IL Figure 15. AMI Input and Output Signal Levels Signal structure of 64 kHz/ 8 kHz central clock interface after suitable transformer. 15.6us 7.8us +V D D 15.6us 7.8us + 1.0V IH 0V I_1 1V 2V p -p 0V IM 1V -1.0V IL TO8POS C2 15.6us C1 I_2 C1 TO8NEG +V D D 7.8us 0V Revision 2.00/September 2003 Semtech Corp. 55 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 16. Recommended Line Termination for AMI Output/Output Ports F igure FINAL AMI input signal Turns ratio 1:1 C1 C2 TO8POS R load C3 AMI output signal to external devices AMI input signal C1 TO8NEG GND Notes The AMI inputs and should be connected to the external AMI clock source by 470 nF coupling capacitor C1. The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1. Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses. Revision 2.00/September 2003 Semtech Corp. 56 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813) Across all operating conditions, unless otherwise stated FINAL Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.058 (N ote 2) 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G.813 & G.812 for 2.048 MHz op tion 1 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Te s t d e f i n i t i o n G.813 for 155.52 MHz op tion 1 G.813 for 155.52 MHz op tion 1 F i l t er u sed 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz U I sp ec UIpp = 0.5 UIpp = 0.1 G.813 for 155.52 MHz op tion 2 12 kHz to 1.3 MHz UIpp = 0.1 Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n G.812 for 1.544 MHz G.812 for 155.52 MHz electrical G.812 for 2.048 MHz electrical F i l t er u sed 10 Hz to 40 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz U I sp ec UIpp = 0.05 UIpp = 0.5 U Ip p = 0.075 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.036 (N ote 14) 0.058 (N ote 15) 0.048 (N ote 15) Revision 2.00/September 2003 Semtech Corp. 57 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Across all operating conditions, unless otherwise stated FINAL Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3) Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n ETS-300-462-3 for 2.048 MHz SEC ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) ETS-300-462-3 for 2.048 MHz SSU ETS-300-462-3 for 155.52 MHz ETS-300-462-3 for 155.52 MHz F i l t er u sed 20 Hz to 100 kHz U I sp ec UIpp = 0.5 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.046 (N ote 14) 20 Hz to 100 kHz UIpp = 0.2 0.046 (N ote 14) 20 Hz to 100 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz UIpp = 0.05 UIpp = 0.5 UIpp = 0.1 0.046 (N ote 14) 0.058 (N ote 15) 0.048 (N ote 15) Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n GR-253-CORE net i/f, 51.84 MHz GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) GR-253-CORE net i/f, 155.52 MHz GR-253-CORE net i/f, 155.52 MHz GR-253-CORE cat II elect i/f, 155.52 MHz F i l t er u sed 100 Hz to 400 kHz U I sp ec UIpp = 1.5 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.022 (N ote 15) 18 kHz to 400 kHz UIpp = 0.15 0.019 (N ote 15) 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz UIpp = 1.5 UIpp = 0.15 UIpp = 0.1 0.058 (N ote 15) 0.048 (N ote 15) 0.057 (N ote 15) 0.006 (N ote 15) 0.017 (N ote 15) 0.003 (N ote 15) 0.036 (N ote 14) 0.0055 (N ote 14) www.semtech.com 12 kHz to 400 kHz UIrms = 0.01 UIpp = 0.1 UIrms = 0.01 UIpp = 0.1 UIrms = 0.01 58 GR-253-CORE cat II elect i/f, 51.84 MHz 12 kHz to 1.3 MHz GR-253-CORE DS1 i/f, 1.544 MHz 10 Hz to 40 kHz Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Across all operating conditions, unless otherwise stated FINAL Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411) Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz F i l t er u sed 10 Hz to 40 kHz 10 Hz to 40 kHz 10 Hz to 40 kHz Broadband U I sp ec UIrms = 0.02 UIrms = 0.025 UIrms = 0.025 UIrms = 0.05 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14) Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n G.742 for 2.048 MHz G.742 for 2.048 MHz (Filter spec 18 kHz to 100 kHz) G.742 for 2.048 MHz F i l t er u sed DC to 100 kHz 20 Hz to 100 kHz 20 Hz to 100 kHz U I sp ec UIpp = 0.25 UIpp = 0.05 UIpp = 0.05 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.047 (N ote 14) 0.046 (N ote 14) 0.046 (N ote 14) Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n TR-N WT-000499 & G824 for 1.544 MHz TR-N WT-000499 & G824 for 1.544 MHz (Filter spec 8 kHz to 40 kHz) F i l t er u sed 10 Hz to 40 kHz U I sp ec UIpp = 5.0 U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.036 (N ote 14) 10 Hz to 40 kHz UIpp = 0.1 0.036 (N ote 14) Revision 2.00/September 2003 Semtech Corp. 59 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. U I m e a s u r e m e n t o n A C S 8 510 R ev 2 0.036 (N ote 14) Te s t d e f i n i t i o n GR-1244-CORE for 1.544 MHz F i l t er u sed >10 Hz U I sp ec UIpp = 0.05 Notes for Tables 23 - 30 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Note 15. Filter used is that defined by test definition unless otherwise stated 5 Hz bandwidth, 19.44 MHz direct lock 5 Hz bandwidth, 8 kHz lock 20 Hz bandwidth, 19.44 MHz direct lock 20 Hz bandwidth, 8 kHz lock 10 Hz bandwidth, 19.44 MHz direct lock 10 Hz bandwidth, 8 kHz lock 2.5 Hz bandwidth, 19.44 MHz direct lock 2.5 Hz bandwidth, 8 kHz lock 1.2 Hz bandwidth, 19.44 MHz direct lock 1.2 Hz bandwidth, 8 kHz lock 0.6 Hz bandwidth, 19.44 MHz direct lock 0.6 Hz bandwidth, 8 kHz lock 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input Revision 2.00/September 2003 Semtech Corp. 60 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 17. JTAG Timing FINAL t CYC TCK t SU R t HT TM S TDI t DO D TDO Table 31. JTAG Timing (for use with Figure 17) PA R A M E T E R Cycle time TMS/TDI to TCK rising edge time TCK rising to TMS/TDI hold time TCK falling to TDO valid SYMB OL tCYC tSUR tHT tDOD MIN 50 3 23 - T YP - MA X 5 U N ITS ns ns ns ns Revision 2.00/September 2003 Semtech Corp. 61 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 18. Input/Output Timing FINAL Input/Output 8 kHz input Typical Delay Output ± 1.5 ns Typical Phase Alignment 8 kHz output 8 kHz 6.48 MHz input +6.5 to +8.5 ns 6.48 MHz output T1 19.44 MHz input +5.5 to +7.5 ns 19.44 MHz output 6.48 MHz 25.92 MHz input +6.5 to +8.5 ns 25.92 MHz output 25.92 MHz 38.88 MHz input +4.0 to +6.0 ns 38.88 MHz output 51.84 MHz 51.84 MHz input +6.0 to +8.0 ns 51.84 MHz output 155.52 MHz 77.76 MHz input +5.5 to +7.5 ns 77.76 MHz output < ± 1 ns +6.0 to +8.0 ns (Additional delay for this output) +2.0 to +4.0 ns +3.0 to +5.0 ns +3.0 to +5.0 ns +3.5 to +5.5 ns (Multiples have the same offset) +3.5 to +5.5 ns (Multiples have the same offset) 2 kHz < ±1 ns E1 19.44 MHz +2.5 to +4.5 ns 38.88 MHz +3.0 to +4.5 ns 77.76 MHz 311.04 MHz < ± 0.5 ns Revision 2.00/September 2003 Semtech Corp. 62 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Microprocessor Interface Timing M icroprocessor Motorola Mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus. The following figures show the timing diagrams of write and read accesses for this mode. FINAL Figure 19. Read Access Timing in MOTOROLA Mode t pw1 CSB t su2 t h2 X t su1 t h1 WRB X A X address t d1 t d3 data t d2 t pw2 t h3 t d4 X AD Z Z RDY (DTACK) Z Z Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) S y m b ol tsu1 tsu2 td 1 td 2 td 3 td 4 tp w 1 tp w 2 th 1 th 2 th 3 tp Setup A valid to CSBfalling edge Setup WRB valid to CSBfalling edge Delay CSBfalling edge to AD valid Delay CSBfalling edge to DTACKrising edge Delay CSBrising edge to AD high-Z Delay CSBrising edge to RDY high-Z CSB low time RDY high time Hold A valid after CSBrising edge Hold WRB high after CSBrising edge Hold CSB low after RDYfalling edge Time between consecutive accesses (CSBrising edge to CSBfalling edge) P ar am et er MIN 0 ns 0 ns 485 ns(1) 310 ns 0 ns 0 ns 0 ns 320 ns T YP MA X 177 ns 13 ns 0 ns 7 ns 472 ns - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 63 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 20. Write Access Timing in MOTOROLA Mode t pw1 FINAL CSB t su2 t h2 X t su1 t h1 WRB X A X address t su3 t h4 X AD X t d2 t pw2 data t h3 t d4 X RDY (DTACK) Z Z Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) S y m b ol tsu1 tsu2 tsu3 td 2 td 4 tp w 1 tp w 2 th 1 th 2 th 3 th 4 tp Setup A valid to CSBfalling edge Setup WRB valid to CSBfalling edge Setup AD valid before CSBrising edge Delay CSBfalling edge to RDYrising edge Delay CSBrising edge to RDY high-Z CSB low time RDY high time Hold A valid after CSBrising edge Hold WRB low after CSBrising edge Hold CSB low after RDYfalling edge Hold AD valid after CSBrising edge Time between consecutive accesses (CSBrising edge to CSBfalling edge) P ar am et er MIN 0 ns 0 ns 3 ns 485 ns(1) 310 ns 3 ns 0 ns 0 ns 4 ns 320 ns T YP MA X 13 ns 7 ns 472 ns - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 64 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Intel Mode In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following figures show the timing diagrams of write and read accesses for this mode. FINAL Figure 21. Read Access Timing in INTEL Mode CSB WRB t su2 t pw 1 t h2 RDB t su1 t h1 a dd re ss t d1 t d4 d ata t d2 t d3 t pw 2 t h3 t d5 Z Z A AD Z RDY Z Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) S y m b ol tsu1 tsu2 td 1 td 2 td 3 td 4 td 5 tp w 1 tp w 2 th 1 th 2 th 3 tp Setup A valid to CSBfalling edge Setup CSBfalling edge to RDBfalling edge Delay RDBfalling edge to AD valid Delay CSBfalling edge to RDY active Delay RDBfalling edge to RDYfalling edge Delay RDBrising edge to AD high-Z Delay CSBrising edge to RDY high-Z RDB low time RDY low time Hold A valid after RDBrising edge Hold CSB low after RDBrising edge Hold RDB low after RDYrising edge Time between consecutive accesses (RDBrising edge to RDBfalling edge , or RDBrising edge to WRBfalling edge) 486 ns(1) 310 ns 0 ns 0 ns 0 ns 320 ns P ar am et er MIN 0 ns 0 ns T YP MA X 177 ns 13 ns 14 ns 10 ns 9 ns 472 ns - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 65 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 22. Write Access Timing in INTEL Mode FINAL CSB t su2 t pw1 t h2 WRB RDB t su1 t h1 address t su3 t h4 A AD t d2 t d3 t pw2 data t h3 t d5 Z RDY Z Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) S y m b ol tsu1 tsu2 tsu3 td 2 td 3 td 5 tp w 1 tp w 2 th 1 th 2 th 3 th 4 tp Setup A valid to CSBfalling edge Setup CSBfalling edge to WRBfalling edge Setup AD valid to WRBrising edge Delay CSBfalling edge to RDY active Delay WRBfalling edge to RDYfalling edge Delay CSBrising edge to RDY high-Z WRB low time RDY low time Hold A valid after WRBrising edge Hold CSB low after WRBrising edge Hold WRB low after RDYrising edge Hold AD valid after WRBrising edge Time between consecutive accesses (WRBrising edge to WRBfalling edge , or WRBrising edge to RDBfalling edge) 486 ns(1) 310 ns 170 ns(2) 0 ns 0 ns 4 ns 320 ns P ar am et er MIN 0 ns 0 ns 3 ns T YP MA X 13 ns 14 ns 9 ns 472 ns - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge. Revision 2.00/September 2003 Semtech Corp. 66 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Multiplexed Mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/ data bus. The following figures show the timing diagrams of write and read accesses for this mode. FINAL Figure 23. Read Access Timing in MULTIPLEXED Mode t pw 3 t p1 ALE t su1 t h1 CSB t su2 W RB t pw 1 t h2 RDB t d1 t d a ta d4 AD a d d re s s t X t X t t d2 d3 t pw 2 h3 d5 RDY Z Z Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) S y m b ol tsu1 tsu2 td 1 td 2 td 3 td 4 td 5 tp w 1 tp w 2 tp w 3 th 1 th 2 th 3 tp 1 tp 2 P ar am et er Setup A D address valid to A LEfalling edge Setup CSBfalling edge to RDBfalling edge Delay RDBfalling edge to A D data valid Delay CSBfalling edge to RDY active Delay RDBfalling edge to RDYfalling edge Delay RDBrising edge to A D data high-Z Delay CSBrising edge to RDY high-Z RDB low time RDY low time A LE high time Hold A D address valid after A LEfalling edge Hold CSB low after RDBrising edge Hold RDB low after RDYrising edge Time b etween A LEfalling edge and RDBfalling edge Time b etween consecutive accesses (RDBrising edge to A LErising edge) MIN 2 ns 0 ns 487 ns (1) T YP - MA X 177 ns 13 ns 15 ns 9 ns 10 ns 472 ns 310 ns 2 ns 3 ns 0 ns 0 ns 0 ns 320 ns - - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 67 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Figure 24. Write Access Timing in MULTIPLEXED Mode t pw 3 FINAL t p1 ALE t su1 t h1 CSB t su2 t pw 1 t h2 W RB RDB t su3 t h4 AD a d d re s s t X t d a ta t t t X d2 d3 pw 2 h3 d5 RDY Z Z Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) S y m b ol tsu1 tsu2 tsu3 td 2 td 3 td 5 tp w 1 tp w 2 tp w 3 th 1 th 2 th 3 th 4 tp 1 tp 2 P ar am et er Setup AD address valid to ALEfalling edge Setup CSBfalling edge to WRBfalling edge Setup AD data valid to WRBrising edge Delay CSBfalling edge to RDY active Delay WRBfalling edge to RDYfalling edge Delay CSBrising edge to RDY high-Z WRB low time RDY low time ALE high time Hold AD address valid after ALEfalling edge Hold CSB low after WRBrising edge Hold WRB low after RDYrising edge AD data hold valid after WRBrising edge Time between ALEfalling edge and WRBfalling edge Time between consecutive accesses (WRBrising edge to ALErising edge) 487 ns(1) 310 ns 2 ns 3 ns 0 ns 0 ns 4 ns 0 ns 320 ns MIN 2 ns 0 ns 3 ns T YP MA X 13 ns 15 ns 9 ns 472 ns - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 68 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Serial Mode In Serial mode, the device is configured to interface with a serial microprocessor bus.The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. FINAL Figure 25. Read Access Timing in Serial Mode CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 SCLK tsu1 _ tpw2 th2 th1 R/W tpw1 SDI A0 A1 A2 A3 A4 A5 A6 td1 td2 SDO Output not driven, pulled low by internal resistor D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK _ SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 td2 SDO Output not driven, pulled low by internal resistor D0 D1 D2 D3 D4 D5 D6 D7 F8525D_013ReadAccSerial_01 Revision 2.00/September 2003 Semtech Corp. 69 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) S y m b ol tsu1 tsu2 td 1 td 2 tp w 1 P ar am et er Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid Delay CSBrising edge to SDO high-Z SCLK low time CLKE = 0 CLKE = 1 SCLK high time CLKE = 0 CLKE = 1 Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 Time b etween consecutive accesses (CSBrising edge to CSBfalling edge) MIN 0 ns 160 ns T YP MA X 17 ns 10 ns FINAL 250ns 500ns - - tp w 2 th 1 th 2 tp 250ns 500ns 170 ns 5 ns 160 ns - - - - Figure 26. Write Access Timing in SERIAL Mode CSB tsu2 ALE=SCLK tsu1 _ tpw2 th2 th1 R/W tpw1 A(0)=SDI A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 AD(0)=SDO Output not driven, pulled low by internal resistor F8110D_014WriteAccSerial_02 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) S y m b ol tsu1 tsu2 tp w 1 tp w 2 th 1 th 2 tp P ar am et er Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge SCLK low time SCLK high time Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge Time between consecutive accesses (CSBrising edge to CSBfalling edge) 70 MIN 0 ns 160 ns 180 ns 180 ns 170 ns 5 ns 160 ns T YP - MA X www.semtech.com Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS EPROM Mode In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Further details can be found in the AMD AM27C64 data sheet. FINAL Figure 27. Access Timing in EPROM Mode CSB (=OEB) A address t acc AD Z data Z Table 40. Access Timing in EPROM Mode (for use with Figure 27) S y m b ol tacc P ar am et er Delay CSBfalling edge or A change to AD valid MIN T YP MA X 920 ns Revision 2.00/September 2003 Semtech Corp. 71 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Package Information P ackage Figure 28. LQFP Package FINAL D 2 3 D1 1 AN2 AN3 1 R1 S E 2 E1 1 3 4 A A AN1 B R2 B Section A-A AN4 L L1 123 5 b 7 Section B-B A A2 e 7 c c1 7 Seating plane A1 6 b b1 7 8 Notes 1 2 3 The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. Shows plating. 4 5 6 7 8 Revision 2.00/September 2003 Semtech Corp. 72 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) 10 0 L Q F P P ack ag e Di m en si on s i n mm FINAL D/E D1/E 1 A A1 A1 A2 A2 e AN1 AN2 AN3 AN4 R1 R1 R2 R2 L L1 L1 S b b1 b1 c c1 c1 Mi n N om Max 16.00 14.00 1.40 0.05 1.50 1.60 0.10 0.15 1.35 1.40 1.45 0.50 11° 12° 13° 11° 12° 13° 0° - 0° 3.5° 7° 0.08 - 0.08 0.20 0.45 0.60 0.75 1.00 (ref) 0.20 - 0.17 0.22 0.27 0.17 0.20 0.23 0.09 0.20 0.09 0.16 Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 29. Typical 100 Pin LQFP Footprint 1.85 mm 17.0 mm (1) Pitch 0.5 mm Width 0.3 mm Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc. Revision 2.00/September 2003 Semtech Corp. 73 www.semtech.com 14.6 mm 18.3 mm ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Application Information A pplication Figure 30. Simplified Application Schematic FINAL Revision 2.00/September 2003 Semtech Corp. 74 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Revision History R evision Table 42. Changes from Revision 1.06 to 2.00 September 2003 Item 1 Section Non-Revertive Mode Page 36-37 Description Updated description of Non-Revertive Mode Operation FINAL Revision 2.00/September 2003 Semtech Corp. 75 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Ordering Information O rdering FINAL PA R T N U M B E R ACS8510 Rev2.1 DE S CR I P T I O N SON ET/SDH Synchronisation, 100 p in LQFP Disclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards. For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: Internet: USA: sales@semtech.com http://www.semtech.com Mailing Address: Street Address: P.O. Box 6097, Camarillo, CA 93011-6097 200 Flynn Road, Camarillo, CA 93012-8790 acsupport@semtech.com Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 ISO9001 CERTIFIED Revision 2.00/September 2003 Semtech Corp. 76 www.semtech.com