ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
Description D escription The ACS8515 is a highly integrated, single-chip solution for ‘hit-less’ protection switching of SEC clocks from Master and Slave SETS clockcards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching against master clock failure. A further input is provided for an optional standby SEC clock. The ACS8515 is fully compliant with the required specifications and standards. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card clock, e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. An SPI(1) compatible serial port is incorporated, providing access to the configuration and status registers for device setup. The ACS8515 can utilise either a low cost XO oscillator module, or a TCXO with full temperature calibration - as required by the application. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. Block Diagram B lock Figure 1. Simple Block Diagram
3 x SEC Input Master/Slave + Standby: N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz MFrSync
Line Card Protection Switch for SONET or SDH Network Elements FINAL
Features F eatures •Suitable for Stratum 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications •Meets AT&T, ITU-T, ETSI and Telcordia specifications •Three SEC input clocks, from 2 kHz to 155.52 MHz •Generates two SEC output clocks, up to 311.04 MHz •Frequency translation of SEC input clock to a different local line card clock •Robust input clock source frequency and activity monitoring on all inputs •Supports Free-run, Locked and Holdover modes of operation •Automatic ‘hit-less’ source switchover on loss of input •External force fast switch between SEC inputs •Phase build out for output clock phase continuity during input switchover •SPI(1) compatible serial microprocessor interface •Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz •Single +3.3 V operation. +5 V I/O compatible •Operating temperature (ambient) -40°C to +85°C •Available in 64 pin LQFP package •Lead (pb)-free version available (ACS8515 Rev2.1T) RoHS and WEEE compliant.
(1) SPI is a trademark of Motorola Corporation
3xSEC
Input Ports MFrSync
APLL DPLL Frequency Synthesis
2xSEC
Output Ports FrSync MFrSync
Monitors
Frequency Dividers
Chip Clock Generator
P riority Table
Register Set
SPI Compatible Serial Microprocessor Port
TCXO or XO
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Contents Table of Cont ents List of Sections
Description ................................................................................................................................................................................................ 1 Block Diagram ........................................................................................................................................................................................... 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Descriptions ........................................................................................................................................................................................ 5 Functional Description ............................................................................................................................................................................. 7
Local Oscillator Clock ..................................................................................................................................................................................... 7 Crystal Frequency Calibration ........................................................................................................................................................ 7 Input Reference Clock Ports ......................................................................................................................................................................... 8 Input Wander and Jitter Tolerance ............................................................................................................................................................ 10 Output Clock Ports ........................................................................................................................................................................................ 11 Low Speed Output Clock ................................................................................................................................................................ 11 High Speed Output Clock .............................................................................................................................................................. 12 Frame Sync and Multi-Frame Sync Clocks ................................................................................................................................ 12 Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 12 Output Wander and Jitter ............................................................................................................................................................................ 13 Phase Variation ............................................................................................................................................................................................. 14 Phase Build Out ............................................................................................................................................................................................. 16 Microprocessor Interface ............................................................................................................................................................................. 16 Register Set ..................................................................................................................................................................................... 16 Configuration Registers ................................................................................................................................................................. 16 Status Registers .............................................................................................................................................................................. 16 Register Access ............................................................................................................................................................................... 17 Interrupt Enable and Clear ......................................................................................................................................................................... 17 Register Map .................................................................................................................................................................................................. 18 Register Map Description ........................................................................................................................................................................... 21 Selection of Input Reference Clock Source ............................................................................................................................................. 29 Automatic Control Selection ........................................................................................................................................................ 29 Ultra Fast Switching ....................................................................................................................................................................... 30 External Protection Switching ..................................................................................................................................................... 30 Activity Monitoring ....................................................................................................................................................................................... 30 Modes of Operation ...................................................................................................................................................................................... 32 Free-run Mode ................................................................................................................................................................................. 32 Pre-Locked Mode ............................................................................................................................................................................ 32 Locked Mode .................................................................................................................................................................................... 32 Lost-Phase Mode ............................................................................................................................................................................. 33 Holdover Mode ................................................................................................................................................................................ 33 Pre-Locked(2) Mode ........................................................................................................................................................................ 33 Power On Reset - PORB ............................................................................................................................................................................... 33
FINAL
Electrical Specification .......................................................................................................................................................................... 35 Serial Microprocessor Interface Timing ............................................................................................................................................... 44 Package Information .............................................................................................................................................................................. 46
Thermal Conditions ....................................................................................................................................................................................... 47
Application Information .......................................................................................................................................................................... 48 Appendix A Rev2.1 Changes Described ............................................................................................................................................... 49 Revision History ...................................................................................................................................................................................... 49 Ordering Information .............................................................................................................................................................................. 50
Disclaimers ..................................................................................................................................................................................................... 50
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List of Figures
Figure 1. Simple Block Diagram .............................................................................................................................................................. 1 Figure 2. ACS8515 Pin Diagram ............................................................................................................................................................. 4 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) .................................................................................................................... 11 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) ........................................................................................................................... 12 Figure 5. Wander and Jitter Transfer Measured Characteristics ........................................................................................................ 14 Figure 6. Maximum Time Interval Error of TOUT0 Output Port ........................................................................................................... 15 Figure 7. Time Deviation of TOUT0 Output Port ................................................................................................................................... 15 Figure 8. Phase Error Accumulation of TOUT0 Output Port in Holdover Mode ................................................................................. 15 Figure 9. Inactivity and Irregularity Monitoring .................................................................................................................................... 30 Figure 10. Automatic Mode Control State Diagram ............................................................................................................................ 34 Figure 11. Recommended Line Termination for PECL Input/Output Ports ....................................................................................... 38 Figure 12. Recommended Line Termination for LVDS Input/Output Ports ....................................................................................... 39 Figure 13. Input/Output Timing ............................................................................................................................................................. 43 Figure 14. Serial Interface Read Access Timing .................................................................................................................................. 44 Figure 15. Serial Interface Write Access Timing ................................................................................................................................. 45 Figure 16. LQFP Package ....................................................................................................................................................................... 46 Figure 17. Typical 64 Pin LQFP Footprint .............................................................................................................................................. 47 Figure 18. Simplified Application Schematic ....................................................................................................................................... 48
FINAL
Tables List of Tables
Table 1. Power Pins .................................................................................................................................................................................... 5 Table 2. No Connections ............................................................................................................................................................................ 5 Table 3. Other Pins ..................................................................................................................................................................................... 6 Table 4. Input Reference Source Selection and Group Allocation ....................................................................................................... 9 Table 5. Input Reference Source Jitter Tolerance ................................................................................................................................ 10 Table 6. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 11 Table 7. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 12 Table 8. Output Reference Source Selection Table ............................................................................................................................. 13 Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 13 Table 10. Register Map ........................................................................................................................................................................... 18 Table 11. Register Map Description ...................................................................................................................................................... 21 Table 12. Absolute Maximum Ratings ................................................................................................................................................... 35 Table 13. Operating Conditions .............................................................................................................................................................. 35 Table 14. DC Characteristics: TTL Input Pad ......................................................................................................................................... 35 Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up ..................................................................................................... 36 Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down ................................................................................................ 36 Table 17. DC Characteristics: TTL Output Pad ...................................................................................................................................... 36 Table 18. DC Characteristics: PECL Input/Output Pad ....................................................................................................................... 37 Table 19. DC Characteristics: LVDS Input/Output Pad ....................................................................................................................... 38 Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813) .............................................................................. 39 Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) .............................................................................. 40 Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) .............................................................. 40 Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) ................................................................ 41 Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411) ................................................................... 41 Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) .............................................................................. 42 Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499) ........................................................... 42 Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE) .............................................................. 42 Table 28. Serial Interface Read Access Timing .................................................................................................................................... 45 Table 29. Serial Interface Write Access Timing ................................................................................................................................... 45 Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) ...................................................................................... 47 Table 31. Revision History ...................................................................................................................................................................... 49
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ADVANCED COMMUNICATIONS
Pin Diagram P in Figure 2. ACS8515 Pin Diagram
FINAL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND IC AGND VA1+ INTREQ REFCLK DGND VD+ VD+ DGND DGND VD+ SRCSW VA2+ AGND IC FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF SEC1_POS SEC1_NEG SEC2_POS SEC2_NEG VDD5 Sync2k SEC1 SEC2 DGND VDD
1
ACS8515
LC/P
Rev 2.1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SONSDHB IC IC IC IC NC DGND VDD O2 NC VDD DGND SDO IC IC IC PORB SCLK VDD VDD CSB SDI CLKE IC DGND VDD VDD IC VDD IC SEC3 IC
NC - Not Connected, IC - Internally Connected
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Pin Descriptions P in Table 1. Power Pins
PIN
8, 9, 12 22
FINAL
SYMB OL
VD+ VDD_DIFF
IO IO
P P
T YPE
-
N A M E /DE S CR I P T I O N
S u p p l y v o l t a g e : Digital supply to gates in analog section, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Digital supply for differential output pins 19 & 20, +3.3 Volts. +/- 10% V D D 5 : Digital supply for +5 Volts tolerance to input pins. Connect to +5 volts (+/- 10%) for clamping to +5 v. Connect to VDD for clamping to +3.3 v. Leave floating for no clamping, input pins tolerant up to +5.5 v. S u p p l y v o l t a g e : Digital supply to logic, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Analog supply to clock multipying APLL, +3.3 Volts. +/- 10% S u p p l y v o l t a g e : Analog supply to output APLL, +3.3 Volts. +/- 10% S u p p l y G r o u n d : Digital ground for logic S u p p l y G r o u n d : Digital ground for differential output pins 19 & 20 S u p p l y G r o u n d : Analog ground
27
VDD5
P
-
32, 36, 38, 39, 45, 46, 54, 57 4 14 7, 10, 11, 31, 40, 53, 58 21 1, 3, 15
VDD
P
-
VA1+ VA2+ DGN D
P P P
-
GN D_DIFF AGN D
P P
-
Table 2. No Connections
PIN
55, 59 2, 16, 33, 35, 60, 61, 62, 63 37 41 49 50 51
SYMB OL
NC IC
IO IO
-
T YPE
-
N A M E /DE S CR I P T I O N
N o t C o n n e c t e d : Leave to Float I n t e r n a l l y C o n n e c t e d : Leave to Float I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG control reset inp ut on next revision I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG test mode select inp ut on next revision I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG boundary scan clock inp ut on next revision I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG serial test data outp ut on next revision I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG serial test data inp ut on next revision
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IC IC IC IC IC
-
-
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Table 3. Other Pins
PIN
5 6 13 17 18 19 20 23 24 25 26 28 29 30 34 42 43 44
FINAL
SYMB OL
IN T R E Q REFCLK SRCSW FrSync MFrSync O1POS O1N EG SEC1_POS SEC1_N EG SEC2_POS SEC2_N EG Sync2k SEC1 SEC2 SEC3 CLKE SDI CSB
IO IO
O I I O O O I I I I I I I I I
T YPE
TTL T T LD TTL TTL LVDS/ PECL LVDS/ PECL PECL/ LVDS T T LD T T LD T T LD T T LD T T LD T T LD T T LU
N A M E /DE S CR I P T I O N
I n t e r r u p t r e q u e s t : Software Interrupt enable R e f e r e n c e c l o c k : 12.8 MHz (refer to section headed Local Oscillator Clock) S o u r c e s w i t c h i n g : Force fast source switching on SEC1 and SEC2 O u t p u t r e f e r e n c e : 8 kHz Frame Sync, 50:50 mark/space ratio output O u t p u t r e f e r e n c e : 2 kHz Multi-Frame Sync, 50:50 mark/space ratio output O u t p u t r e f e r e n c e : Programmable, default 38.88 MHz LVDS I n p u t r e f e r e n c e : Programmable, default 19.44 MHz LVDS I n p u t r e f e r e n c e : Programmable, default 19.44 MHz PECL M u l t i - Fr a m e S y n c 2 k H z : Multi-Frame Sync input I n p u t r e f e r e n c e : Programmable, default 8 kHz I n p u t r e f e r e n c e : Programmable, default 8 kHz I n p u t r e f e r e n c e : External standby reference clock source, programmable, default 19.44 MHz S C L K e d g e s e l e c t : SCLK active edge select, CLKE=1 selects falling edge of SCLK to be active, CLKE = 0 for rising edge M i c r o p r o c e s s o r i n t e r f a c e a d d r e s s : Serial data input C h i p s e l e c t ( a c t i v e l o w ) : This pin is asser ted Low by the microprocessor to enable the microprocessor inter face A d d r e s s L a t c h E n a b l e : default Serial data clock. When this pin transitions from low to high, the address bus inputs are latched into the internal registers P o w e r o n r e s e t : Master reset. If PORB is forced Low, all internal states are reset back to default values
47
SCLK
I
T T LD
48
PORB
I
T T LU
Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor
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Table 3 (continued).
PIN
52 56
FINAL
N A M E /DE S CR I P T I O N
M i c r o p r o c e s s o r i n t e r f a c e a d d r e s s : Serial data outp ut O u t p u t r e f e r e n c e : 19.44 MHz fixed S O N E T S D H B : SON ET or SDH frequency select: sets the initial p ower-up state (or state after a PORB) of the SON ET/SDH frequency selection registers, addr 34h, bit 2 and addr 38, bits 5 and 6. When low SDH rates are selected (2.048 MHz etc) and when set high SON ET rates are selected (1.544 MHz etc). The register states can be changed after p ower up by software.
SYMB OL
SDO O2
IO IO
O O
T YPE
T T LD TTL
64
SON SDHB
I
T T LD
F unctional Description The ACS8515 is a highly integrated, single-chip solution for ‘hit-less’ protection switching of SEC clocks from Master and Slave SETS clock cards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching for Master/Slave SEC clock failure. The standby SEC clock will be selected if both the Master and Slave input clocks fail. The selection of the Master/Slave input can also be forced by a Force Fast Switch pin. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card - e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. The ACS8515 has three SEC clock inputs (Master, Slave and Standby) and a single MultiFrame Sync input, for synchronising the frame and multi-frame sync outputs. The ACS8515 generates two SEC clock outputs via PECL/LVDS and TTL ports, with spot frequencies from 1.544/2.048 MHz up to 311.04 MHz. The ACS8515 also provides an 8 kHz Frame Sync and 2 kHz Multi-Frame Sync output clock. The ACS8515 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points).
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The ACS8515 includes an SPI compatible serial microprocessor port, providing access to the configuration and status registers for device setup. Local Oscillator Clock The Master system clock on the ACS8515 requires an external clock oscillator of frequency 12.80 MHz. The exact clock specification is dependent on the quality of Holdover performance required in the application. In most Line Card protection switching applications where there is a high chance that at least one SEC reference input will be available, the long term stability requirement for Holdover is not appropriate and an inexpensive crystal local oscillator can be used. In other applications where there may be a requirement for longer term Holdover stability to meet the ITU standards for Stratum 3, a higher quality oscillator can be used. Please contact Semtech for information on crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value.
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+/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, giving a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a - 5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be :
39321 - (5 / 0.02) = 39071 (decimal)
FINAL
2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 64). Specific frequencies and priorities are set by configuration. The TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. Clock speeds above 100 MHz should not be applied to the TTL ports. The PECL/LVDS ports support the full range of clock speeds, up to 155.52 MHz. The actual spot frequencies supported are: •2 kHz •4 kHz •8 kHz (and N x 8 kHz), •1.544 MHz (SONET)/2.048 MHz (SDH), •6.48 MHz, •19.44 MHz, •25.92 MHz, •38.88 MHz, •51.84 MHz, •77.76 MHz, •155.52 MHz. The frequency selection is programmed via the cnfg_ref_source_frequency r egister. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways;
1. Any of the supported spot frequencies can be divided to 8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register.
The ACS8515 supports up to three individual input reference clock sources via TTL/CMOS and PECL/ LVDS technologies. These interface technologies support +3.3 V and +5 V operation. Input Reference Clock Ports The input reference clock ports are arranged in groups. Group one comprises a TTL port (SEC1) and a PECL/LVDS port (SEC1POS and SEC1NEG). Group two comprises a TTL port (SEC2) and a PECL/LVDS port (SEC2POS and SEC2NEG). Group three comprises a TTL port (SEC3). For group one and group two, only one of the two input ports types must be active at any time, the other must not be driven by a reference input. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other low (GND), or set in LVDS mode and left floating (in which case one input is internally pulled high and the other low). SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit
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Table 4. Input Reference Source Selection and Group Allocation
P or t N am e I n p u t P or t Te c h n o l o g y
TTL/CMOS TTL/CMOS LVDS/PECL LVDS default PECL/LVDS PECL default TTL/CMOS TTL/CMOS
FINAL
Def au l t P ri ori t y
(N ote 3)
Fr e q u e n c i e s S u p p o r t e d
Up to 100MHz (N ote 1) Default (SON ET/SDH): Up to 100MHz (N ote 1) Default (SON ET/SDH):
S E C S ou r ce Gr ou p
SEC1 SEC2 SEC1 SEC2 SEC3 SYN C1
8kHz 8kHz
1 2 1 2 3 -
1 (4) 3 (5) 2 (6) 4 (7) 5 (10) -
Up to 155.52MHz (N ote 2) Default (SON ET/SDH): 19.44MHz Up to 155.52MHz (N ote 2) Default (SON ET/SDH): 19.44MHz Up to 100MHz (N ote 1) Default (SON ET/SDH): 2kHz Multi Frame Sync 19.44MHz
Notes for Table 4. Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are 2 kHz, 4 kHz, 8 kHz, N x 8 kHz, 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz. Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output clock frequencies available for SONET and SDH applications. Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the ACS8510. On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
2. Any multiple of any supported frequency can be supported by using the "DivN" feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to lock at 8 kHz independently of the frequencies and configurations of the other inputs.
Any reference input with the ‘DivN’ bit set in the c nfg_ref_source_frequency r egister will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0100s)
(2) all refs evaluated & at least one ref valid
Reference sources are flagged as 'val active, 'in-band' and have no phase al a
(4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s]
pre-locked w ait for up to 100s (state 110)
All sources are continuously checked activity and frequency. Only the main source is checked for p A phase lock alarm is only raised on a reference when that reference has los whilst being used as the main referenc micro-processor can reset the phase alarm. A s ource is considered to have phase when it has been continuously in phas for between 1 and 2 seconds
(5) selected ref phase locked
locked keep ref (state 100)
(10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ]
(6) no valid standby ref & main ref invalid
(8) phase regained within 100s
(7) phase lost on main ref
pre-locked2 w ait for up to 100s (state 101)
(12) valid standby ref & (main ref invalid or out of lock >100s)
Lost phase w ait for up to 100s (state 111)
(11) no valid standby ref & (main ref invalid or out of lock >100s)
holdover select ref (state 010)
(15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s]
(13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid
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Electrical Specification E lectrical Important Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation Note of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 12. Absolute Maximum Ratings
PA RA METER
Sup p ly Voltage VDD, VD+, VA1+,VA2+ Inp ut Voltage (non-sup p ly p ins) Outp ut Voltage (non-sup p ly p ins) Ambient Op erating Temp erature Range Storage Temp erature
FINAL
SYMB OL
VDD Vin Vout TA Tstor
M IN IN
-0.5 -40 -50
M AX AX
3.6 5.5 5.5 85 150
U N ITS
V V V °C °C
Table 13. Operating Conditions
PA RA METER
Power Sup p ly (dc voltage) VDD, VD+,VA1+, VA2+, VDD_DIFF Power Sup p ly (dc voltage) VDD5 Ambient Temp erature Range Sup p ly Current
Typ ical - one 19 MHz outp ut Maximum - 190 mA before s/w initialisation, 150 mA after s/w intialisation
SYMB OL
VDD VDD5 TA IDD
MIN
3.0 3.0 -40
T YP
3.3 3.3/5.0 -
MA X
3.6 5.5 85
U N ITS
V V °C
-
110
190/150
mA
Total p ower dissip ation
PTOT
-
360
685
mW
Table 14. DC Characteristics: TTL Input Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
Vin High Vin Low Inp ut Current
SYMB OL
V ih V il Ii n
MIN
2.0 35
T YP
-
MA X
0.8 10
U N ITS
V V µA
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Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up
Across all operating conditions, unless otherwise stated
FINAL
PA R A M E T E R
Vin High Vin Low Pull-up Resistor Inp ut Current
SYMB OL
V ih V il PU Ii n
MIN
2.0 30 -
T YP
-
MA X
0.8 80 120
U N ITS
V V k! µA
Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down
Across all operating conditions, unless otherwise stated
PA R A M E T E R
Vin High Vin Low Pull-down Resistor Inp ut Current
SYMB OL
V ih V il PD Ii n
MIN
2.0 30 -
T YP
-
MA X
0.8 80 120
U N ITS
V V k! µA
Table 17. DC Characteristics: TTL Output Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
Vout Low Iol = 4mA Vout High Ioh = 4mA Drive Current
SYMB OL
Vol Voh ID
MIN
0 2.4 -
T YP
-
MA X
0.4
U N ITS
V V
4
mA
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Table 18. DC Characteristics: PECL Input/Output Pad
Across operating conditions, unless otherwise stated
FINAL
PA R A M E T E R
PECL Inp ut Low voltage
Differential inp uts (N ote 1)
SYMB OL
VILPECL VIHPECL VIDPECL VILPECL_S VIHPECL_S
MIN
VDD-2.5 VDD-2.4 0.1 VDD-2.4 VDD-1.3
T YP
-
MA X
VDD-0.5 VDD-0.4 1.4 VDD-1.5 VDD-0.5
U N ITS
V V V V V
PECL Inp ut High voltage
Differential inp uts (N ote 1)
Inp ut Differential voltage PECL Inp ut Low voltage
Single ended inp ut (N ote 2)
PECL Inp ut High voltage
Single ended inp ut (N ote 2)
Inp ut High current
Inp ut differential voltage VID = 1.4v
IIHPECL
-10
-
+10
µA
Inp ut Low current
Inp ut differential voltage VID = 1.4v
IILPECL
-10
-
+10
µA
PECL Outp ut Low voltage
(N ote 3)
VOLPECL VOHPECL VODPECL
VDD-2.10 VDD-1.25 580
-
VDD-1.62 VDD-0.88 900
V V mV
PECL Outp ut High voltage
(N ote 3)
PECL Outp ut Differential voltage
(N ote 1)
Notes for Table 18 Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 ! load on each pin to VDD-2 V . i.e. 82 ! to GND and 130 ! to VDD.
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Figure 11. Recommended Line Termination for PECL Input/Output Ports
V DD
ZO=50Ω 130R
FINAL
8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz
SEC1_POS
ZO=50Ω 82R 130R
SEC1_NEG
82R ZO=50Ω 130R
V DD
O1POS GND
ZO=50Ω 82R 130R
19.44, 38.88, 155.52, 311.04 MHz & DIG1
V DD
ZO=50Ω 130R
O1NEG
82R
8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz
SEC2_POS
ZO=50Ω 82R 130R
GND
SEC2_NEG
82R
VDD = +3.3 V
GND
Table 19. DC Characteristics: LVDS Input/Output Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
LVDS Inp ut voltage range
Differential inp ut voltage = 100 mV
SYMB OL
VVRLVDS VDITH VIDLVDS
MIN
0 -100 0.1
T YP
-
MA X
2.40 +100 1.4
U N ITS
V mV V
LVDS Differential inp ut threshold LVDS Inp ut Differential voltage LVDS Inp ut termination resistance
Must be p laced externally across the LVDS+/- inp ut p ins of ACS8515. Resistor should be 100 ohm with 5% tolerance
R TERM
95
100
105
W
LVDS Outp ut high voltage
(N ote 1)
VOHLVDS VOLLVDS VODLVDS
0.885 250
-
1.585 450
V V mV
LVDS Outp ut low voltage
(N ote 1)
LVDS Differential outp ut voltage
(N ote 1)
LVDS Charge in magnitude of differential outp ut voltage for comp limentary states
(N ote 1)
VDOSLVDS
-
-
25
mV
LVDS outp ut offset voltage
Temp erature = 25°C (N ote 1)
VOSLVDS
1.125
-
1.275
V
Note 1. With 100 ! load between the differential outputs. Revision 2.01/December 2005 Semtech Corp. 38 www.semtech.com
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Figure 12. Recommended Line Termination for LVDS Input/Output Ports
FINAL
8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz
ZO=50Ω
SEC1_POS
ZO=50Ω 100R
SEC1_NEG O1POS
ZO=50Ω
ZO=50Ω
100R
19.44, 311.04
8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz
ZO=50Ω
O1NEG SEC2_POS
100R
ZO=50Ω
SEC2_NEG
Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N G.813 for 155.52 MHz op tion 1 G.813 for 155.52 MHz op tion 1 FIL T E R U SE D 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz U I SPE C UIpp = 0.5 UIpp = 0.1 U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.058 (N ote 2) 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G.813 & G.812 for 2.048 MHz op tion 1 20 Hz to 100 kHz
39
G.813 for 155.52 MHz op tion 2
12 kHz to 1.3 MHz
UIpp = 0.1
UIpp = 0.05
0.046 (N ote 14)
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Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812)
Across all operating conditions, unless otherwise stated
FINAL
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N G.812 for 1.544 MHz G.812 for 155.52 MHz electrical G.812 for 2.048 MHz electrical
FIL T E R U SE D 10 Hz to 40 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz
U I SPE C UIpp = 0.05 UIpp = 0.5 U Ip p = 0.075
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.036 (N ote 14) 0.058 (N ote 3) 0.048 (N ote 3)
Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N ETS-300-462-3 for 2.048 MHz SEC ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) ETS-300-462-3 for 2.048 MHz SSU ETS-300-462-3 for 155.52 MHz ETS-300-462-3 for 155.52 MHz
FIL T E R U SE D 20 Hz to 100 kHz
U I SPE C UIpp = 0.5
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.046 (N ote 14)
20 Hz to 100 kHz
UIpp = 0.2
0.046 (N ote 14)
20 Hz to 100 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz
UIpp = 0.05 UIpp = 0.5 UIpp = 0.1
0.046 (N ote 14) 0.058 (N ote 3) 0.048 (N ote 3)
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Across all operating conditions, unless otherwise stated
FINAL
Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE)
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N GR-253-CORE net i/f, 51.84 MHz GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) GR-253-CORE net i/f, 155.52 MHz GR-253-CORE net i/f, 155.52 MHz GR-253-CORE cat II elect i/f, 155.52 MHz FIL T E R U SE D 100 Hz to 400 kHz U I SPE C UIpp = 1.5 U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.022 (N ote 3)
18 kHz to 400 kHz
UIpp = 0.15
0.019 (N ote 3)
500 Hz to 1.3 MHz 65 kHz to 1.3 MHz
UIpp = 1.5 UIpp = 0.15 UIpp = 0.1
0.058 (N ote 3) 0.048 (N ote 3) 0.058 (N ote 3) 0.006 (N ote 3) 0.017 (N ote 3) 0.003 (N ote 3) 0.036 (N ote 14) 0.0055 (N ote 14)
12 kHz to 1.3 MHz UIrms = 0.01 UIpp = 0.1 UIrms = 0.01 UIpp = 0.1 UIrms = 0.01
GR-253-CORE cat II elect i/f, 51.84 MHz
12 kHz to 400 kHz
GR-253-CORE DS1 i/f, 1.544 MHz
10 Hz to 40 kHz
Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz FIL T E R U SE D 10 Hz to 40 kHz 10 Hz to 40 kHz 10 Hz to 40 kHz Broadband
41
U I SPE C UIrms = 0.02 UIrms = 0.025 UIrms = 0.025 UIrms = 0.05
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14)
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Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742)
Across all operating conditions, unless otherwise stated
FINAL
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N G.742 for 2.048 MHz G.742 for 2.048 MHz (Filter spec 18 kHz to 100 kHz) G.742 for 2.048 MHz
FIL T E R U SE D DC to 100 kHz 20 Hz to 100 kHz 20 Hz to 100 kHz
U I SPE C UIpp = 0.25 UIpp = 0.05 UIpp = 0.05
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.047 (N ote 14) 0.046 (N ote 14) 0.046 (N ote 14)
Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N TR-N WT-000499 & G.824 for 1.544 MHz TR-N WT-000499 & G.824 for 1.544 MHz (Filter spec 8 kHz to 40 kHz)
FIL T E R U SE D 10 Hz to 40 kHz
U I SPE C UIpp = 5.0
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.036 (N ote 14)
10 Hz to 40 kHz
UIpp = 0.1
0.036 (N ote 14)
Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.036 (N ote 14)
TE S T D E F I N I T I O N GR-1244-CORE for 1.544 MHz
FIL T E R U SE D >10 Hz
U I SPE C UIpp = 0.05
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Notes for tables 20 - 227 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Filter used is that defined by test definition unless otherwise stated 5 Hz bandwidth, 19.44 MHz input, direct lock 5 Hz bandwidth, 19.44 MHz input, 8 kHz lock 20 Hz bandwidth, 19.44 MHz input, direct lock 20 Hz bandwidth, 19.44 MHz input, 8 kHz lock 10 Hz bandwidth, 19.44 MHz input, direct lock 10 Hz bandwidth, 19.44 MHz input, 8 kHz lock 2.5 Hz bandwidth, 19.44 MHz input, direct lock 2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock 1.2 Hz bandwidth, 19.44 MHz input, direct lock 1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock 0.6 Hz bandwidth, 19.44 MHz input, direct lock 0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock 5 Hz bandwidth, 2.048 MHz input, 8 kHz lock
FINAL
Figure 13. Input/Output Timing
Input/Output 8 kHz input ± 1.5 ns 8 kHz output 8 kHz 6.48 MHz input +6.5 to +8.5 ns 6.48 MHz output T1 19.44 MHz input +5.5 to +7.5 ns 19.44 MHz output 6.48 MHz +3.0 to +5.0 ns +3.5 to +5.5 ns (Multiples have the same offset) +3.5 to +5.5 ns (Multiples have the same offset) Typical Delay Output Typical Phase Alignment
2 kHz
< ±1 ns
E1
25.92 MHz input +6.5 to +8.5 ns 25.92 MHz output
19.44 MHz
+2.5 to +4.5 ns
25.92 MHz 38.88 MHz input +4.0 to +6.0 ns 38.88 MHz output 51.84 MHz 51.84 MHz input +6.0 to +8.0 ns 51.84 MHz output 155.52 MHz 77.76 MHz input +5.5 to +7.5 ns 77.76 MHz output
+3.0 to +5.0 ns
38.88 MHz
+3.0 to +4.5 ns
+6.0 to +8.0 ns (Additional delay for this output) +2.0 to +4.0 ns
77.76 MHz
< ± 1 ns
311.04 MHz
< ± 0.5 ns
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Microprocessor Interface Timing M icroprocessor
The device has a Serial microprocessor interface. The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode.
FINAL
Figure 14. Read Access Timing
CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 SCLK tsu1
_
tpw2
th2
th1
R/W
tpw1
SDI
A0 A1 A2 A3 A4 A5 A6 td1 td2
SDO
Output not driven, pulled low by internal resistor
D0 D1 D2 D3 D4 D5 D6 D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK
_
SDI
R/W
A0 A1 A2 A3 A4 A5 A6 td1 td2
SDO
Output not driven, pulled low by internal resistor
D0 D1 D2 D3 D4 D5 D6 D7
F8525D_013ReadAccSerial_01
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Table 28. Read Access Timing
S y m b ol tsu1 tsu2 td 1 td 2 tp w 1 P ar am et er Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge Delay SCLKrising edge (SCLKfalling edge for CLKE = 1)to SDO valid Delay CSBrising edge to SDO high-Z SCLK low time CLKE = 0 CLKE = 1 SCLK high time CLKE = 0 CLKE = 1 Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 Time b etween consecutive accesses (CSBrising edge to CSBfalling edge) MIN 0 ns 160 ns T YP MA X 17 ns 10 ns
FINAL
250 ns 500 ns
-
-
tp w 2 th 1 th 2 tp
250 ns 500 ns 170 ns 5 ns 160 ns
-
-
-
-
Figure 15. Write Access Timing
CSB tsu2 SCLK tsu1
_
tpw2
th2
th1
R/W
tpw1
SDI
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
SDO
Output not driven, pulled low by internal resistor
F8525D_014WriteAccSerial_01
Table 29. Write Access Timing
S y m b ol tsu1 tsu2 tp w 1 tp w 2 th 1 th 2 tp P ar am et er Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge SCLK low time SCLK high time Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge Time between consecutive accesses (CSBrising edge to CSBfalling edge)
45
MIN 0 ns 160 ns 180 ns 180 ns 170 ns 5 ns 160 ns
T YP -
MA X www.semtech.com
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Package Information P ackage Figure 16. LQFP Package
FINAL
D
2 3
D1 1
AN2
1
R1 S E 2 E1 1 3 4 L1 A A AN1 B L
123
5 b e 7
A
A2 c 7
Seating plane A1 6 b b1 7
Notes 1 2 3 The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead Shows plating.
4 5 6 7 8
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Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)
64 L Q F P P ack ag e D/E D1/E 1 A A1 A1 A2 A2 e AN1 AN2 AN3 AN4 R1 R1 R2 R2 L L1 L1 S b b1 b1 c c1 c1
FINAL
Di m en si on s i n mm
Mi n N om Max 12.00 10.00
1.40 1.50 1.60
0.05 0.10 0.15
1.35 1.40 1.45 0.50
11° 12° 13°
11° 12° 13°
0° -
0° 3.5° 7°
0.08 -
0.08 0.20
0.45 0.60 0.75 1.00 (ref)
0.20 -
0.17 0.22 0.27
0.17 0.20 0.23
0.09 0.20
0.09 0.16
Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 17. Typical 64 Pin LQFP Footprint
1.85 mm
13.0 mm (1)
10.6 mm
Pitch 0.5 mm Width 0.3 mm
Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example - the user is responsible for ensuring compatibility with PCB manufacturing process, etc.
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14.3 mm
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Application Information A pplication Figure 18. Simplified Application Schematic
FINAL
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Appendix A Rev2.1 Changes Described A ppendix Summary
This section summarizes the minor changes and improvements made to the ACS8515 from Rev2.0 to Rev2.1. The bulk of these changes are designed to remove the need for software work arounds associated with Phase Build Out. Two new features have been added, necessitating changes to the control software. These are described in detail below.
FINAL
Input Edge Alignment for 8k locking mode
An additional bit in the register cnfg_control1 (Bit 2) has been allocated to select which edge of the input reference to lock to when the device is configured in 8k locking mode. This bit, when set to one ensures that the rising edge of the output clock phase locks to the rising edge of the input clock, when 8k locking mode is used on the input.
Low Jitter n x E1/DS1 Mode
A second bit of the cnfg_control1 register has been allocated to controlling what frequency is fed into the APLL. This allows the user to switch from the normal 77.76MHz to twice the dig2 output frequency. This has the effect of replacing the normal OC/STM outputs with multiples of the E1 or DS1 rate. The E1/DS1 choice is controlled by the SONET/SDH bit in the cnfg_mode register.
Revision History R evision Table 31. Changes from Revision 1.05 to 2.00 September 2003.
Item 1 Section Non-Revertive Mode Page 29 Description Updated Non-Revertive mode description
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Ordering Information O rdering
FINAL
PA R T N U M B E R
A CS8515 Rev2.1 A CS8515 Rev2.1T
DE S CR I P T I O N
SON ET/SDH Li n e Card Protecti on , 64 p i n LQFP Lead (Pb ) - free p ackage versi on of A CS8515 rev 2.1
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards.
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 acsupport@semtech.com
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