ACS8525

Line Card Protection Switch for SONET/SDH Systems ADVANCED COMMUNICATIONS Description FINAL Features DATASHEET ACS8525 LC/P The ACS8525 is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for Line Cards in a SONET or SDH Network Element. The ACS8525 has fast activity monitors on the SEC clock inputs and will implement automatic system protection switching against the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clocks fail, the Stand-by “Group” is selected or, if no Stand-by is available, the device enters Digital Holdover mode. The ACS8525 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. Master and Slave SEC inputs to the device support TTL/CMOS and PECL/LVDS. The Stand-by SEC and three Sync inputs are TTL/CMOS only. The ACS8525 generates two SEC clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot frequencies from 2 kHz up to 311.04 MHz (up to 155.52 MHz on the TTL/CMOS port). It also provides an 8 kHz Frame Sync and a 2 kHz Multi-Frame Sync signal output with programmable pulse width and polarity. The ACS8525 includes a Serial Port, which can be SPI compatible, providing access to the configuration and status registers for device setup. IEEE 1149.1 JTAG Boundary Scan is supported. Block Diagram Figure 1 Block Diagram of the ACS8525 LC/P 3 x SEC/Sync Input Groups SEC1 & SEC2: TTL/PECL/LVDS, SEC3 and all Syncs TTL only SEC1 Master SYNC1 SEC2 Slave SYNC2 SEC3 Stand-by SYNC3 SEC Inputs: Programmable Frequencies 2 kHz, 4 kHz, TCK N x 8 kHz TDI 1.544/2.048 MHz TMS 6.48 MHz TRST 19.44 MHz TDO 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz SONET/SDH applications up to OC-3/STM-1 bit rates Switches between grouped inputs (SEC/Sync pairs) Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz multiples up to 155.52 MHz), plus Frame Sync/MultiFrame Sync Outputs: two SEC clocks at any of several spot frequencies from 2 kHz up to 77.76 MHz via the TTL/CMOS port and up to 311.04 MHz via the PECL/LVDS port Selectable clock I/O port technologies Modes for E3/DS3 and multiple E1/DS1 rate output clocks Frequency translation of SEC input clock to a different local line card clock Robust input clock source activity monitoring on all inputs Supports Free-run, Locked and Digital Holdover modes of operation Automatic “Hit-less” source switchover on loss of input External force fast switch between SEC1/SEC2 inputs Phase Build-out for output clock phase continuity during input switchover PLL “Locked” and “Acquisition” bandwidths individually selectable from 18, 35 or 70 Hz Serial interface for device set-up Single 3.3 V operation, 5 V I/O compatible Operating temperature (ambient) of -40 to +85°C Available in LQFP 64 package Lead (Pb)-free version available (ACS8525T), RoHS and WEEE compliant DPLL1 Input SEC Port Monitors and Input Selection Control DPLL2 MUX 2 APLL2 Output Port Frequency Selection MUX 1 APLL 1 SEC Outputs: 01 (PECL/LVDS) 02 (TTL) Selector Digital Feedback E1/DS1 Synthesis APLL3 Sync Outputs: MFrSync 2 kHz (TTL) FrSync 8 kHz (TTL) 01 and 02: E1/DS1 (2.048/1.544 MHz) and frequency multiples: 1.5x, 2x, 3x, 4x, 6x, 12x, 16x, and 24x E1/DS1 E3/DS3, 2 kHz, 8 kHz. and OC-N* rates: OC-1 51.84 MHz OC-3 155.52 MHz and derivatives: 6.48 MHz (O2 port only) 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz (01 port only) 311.04 MHz (01 port only) F8525D_001BLOCKDIA_05 IEEE 1149.1 JTAG Chip Clock Generator Priority Register Set Table Serial Interface Port TCXO or XO Revision 3.01/August 2005 © Semtech Corp. Page 1 www.semtech.com Table of Contents ADVANCED COMMUNICATIONS Table of Contents Section ACS8525 LC/P DATASHEET Page FINAL Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Description........................................................................................................................................................................................... 5 Introduction................................................................................................................................................................................................ 7 General Description................................................................................................................................................................................... 7 Inputs ..................................................................................................................................................................................................7 Preconfiguring Inputs............................................................................................................................................................... 8 PECL/LVDS Input Port Selection ............................................................................................................................................. 9 Input Locking Frequency Modes ............................................................................................................................................. 9 Input SEC Activity Monitors ...............................................................................................................................................................9 Leaky Bucket Accumulator ................................................................................................................................................... 10 Fast Activity Monitor.............................................................................................................................................................. 11 Selector............................................................................................................................................................................................ 11 Selection of Input SECs......................................................................................................................................................... 11 External Protection Switching Mode-SRCSW pin ................................................................................................................ 13 Output Clock Phase Continuity on Source Switchover ....................................................................................................... 13 Forcing of the Operating Mode of the Device...................................................................................................................... 13 Phase Locked Loops (PLLs) ........................................................................................................................................................... 13 PLL Overview ......................................................................................................................................................................... 13 PLL Architecture .................................................................................................................................................................... 14 PLL Operational Controls ...................................................................................................................................................... 17 Phase Compensation Functions .......................................................................................................................................... 19 DPLL Feature Summary ........................................................................................................................................................ 20 Outputs ............................................................................................................................................................................................ 22 PECL/LVDS Output Port Selection ....................................................................................................................................... 22 Output Frequency Selection and PLL Configuration ........................................................................................................... 22 Operating Modes (States) of the Device ....................................................................................................................................... 30 Free-run Mode ....................................................................................................................................................................... 30 Pre-locked Mode ................................................................................................................................................................... 30 Locked Mode ......................................................................................................................................................................... 30 Lost-phase Mode................................................................................................................................................................... 30 Digital Holdover Mode........................................................................................................................................................... 30 Pre-locked2 Mode ................................................................................................................................................................. 32 Local Oscillator Clock...................................................................................................................................................................... 32 Status Reporting and Phase Measurement.................................................................................................................................. 32 Input Status Interrupts.......................................................................................................................................................... 32 Input Status Information....................................................................................................................................................... 32 DPLL Frequency Reporting ................................................................................................................................................... 32 Measuring Phase Between Master and Slave/Stand-by SEC Sources ............................................................................. 33 Sync Reference Sources ................................................................................................................................................................ 33 Aligning Phase of MFrSync and FrSync Outputs to Phase of Sync Inputs......................................................................... 34 Power-On Reset............................................................................................................................................................................... 35 Serial Interface................................................................................................................................................................................ 35 Register Map........................................................................................................................................................................................... 38 Register Organization ..................................................................................................................................................................... 38 Multi-word Registers ............................................................................................................................................................. 38 Register Access ..................................................................................................................................................................... 38 Interrupt Enable and Clear ................................................................................................................................................... 38 Defaults.................................................................................................................................................................................. 38 Register Descriptions ............................................................................................................................................................................. 42 Revision 3.01/August 2005 © Semtech Corp. Page 2 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS FINAL DATASHEET Section Page Electrical Specifications ......................................................................................................................................................................... 98 JTAG ................................................................................................................................................................................................. 98 Over-voltage Protection .................................................................................................................................................................. 98 ESD Protection ................................................................................................................................................................................ 98 Latchup Protection.......................................................................................................................................................................... 98 Maximum Ratings ........................................................................................................................................................................... 99 Operating Conditions ...................................................................................................................................................................... 99 DC Characteristics .......................................................................................................................................................................... 99 Jitter Performance ........................................................................................................................................................................ 103 Input/Output Timing ..................................................................................................................................................................... 105 Package Information ............................................................................................................................................................................ 106 Thermal Conditions....................................................................................................................................................................... 107 Application Information ........................................................................................................................................................................ 108 References ............................................................................................................................................................................................ 109 Abbreviations ........................................................................................................................................................................................ 109 Notes ..................................................................................................................................................................................................... 110 Trademark Acknowledgements ........................................................................................................................................................... 110 Revision Status/History ....................................................................................................................................................................... 111 Ordering Information ............................................................................................................................................................................ 112 Disclaimers.................................................................................................................................................................................... 112 Contacts......................................................................................................................................................................................... 112 Revision 3.01/August 2005 © Semtech Corp. Page 3 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS Pin Diagram FINAL DATASHEET Figure 2 ACS8525 Pin Diagram Line Card Protection Switch for SONET/SDH Systems 1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 AGND1 IC1 AGND2 VA1+ INTREQ REFCLK DGND1 VD1+ VD2+ DGND2 DGND3 VD3+ SRCSW VA2+ AGND3 IC2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SONSDHB IC6 IC5 IC4 IC3 NC2 AGND4 VA3+ O2 NC1 VDD7 DGND6 SDO TDI TDO TCK ACS8525 LC/P 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PORB SCLK VDD6 VDD5 CSB SDI CLKE TMS DGND5 VDD4 VDD3 TRST VDD2 SYNC3 SEC3 SYNC2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF SEC1POS SEC1NEG SEC2POS SEC2NEG VDD5V SYNC1 SEC1 SEC2 DGND4 VDD1 F8525D_002PINDIAG_02 Revision 3.01/August 2005 © Semtech Corp. Page 4 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS Pin Description Table 1 Power Pins Pin Number 8, 9, 12 22 27 Symbol VD1+, VD2+, VD3+ VDD_DIFF VDD5V I/O P P P Type Description Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts ±10%. Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping. Input pins tolerant up to +5.5 Volts. Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. FINAL DATASHEET 32, 36, 38, 39, 45, 46, 54 4 14, 57 15, 58 7, 10, 11 31, 40, 53 21 1, 3 VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7 VA1+ VA2+, VA3+ AGND3, AGND4 DGND1, DGND2, DGND3 DGND4, DGND5, DGND6 GND_DIFF AGND1, AGND2 P - P P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%. Supply Voltage: Analog supply to output PLLs APLL2 and APPL1, +3.3 Volts ±10%. Supply Ground: Analog ground for output PLLs APLL2 and APPL1. Supply Ground: Digital ground for components in PLLs. Supply Ground: Digital ground for logic. Supply Ground: Digital ground for differential ports. Supply Ground: Analog grounds. P P P P - Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Internally Connected Pin Number 2, 16, 60, 61, 62, 63 55, 59 Symbol IC1, IC2, IC3, IC4, IC5, IC6, NC1, NC2 I/O Type Description Internally Connected: Leave to float. Not Connected: Leave to float. Table 3 Other Pins Pin Number 5 6 13 Symbol INTREQ REFCLK SRCSW I/O O I I Type TTL/CMOS TTL TTLD Description Interrupt Request: Active High/Low software Interrupt output. Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). Source Switching: Force Fast Source Switching on SEC1 and SEC2. Revision 3.01/August 2005 © Semtech Corp. Page 5 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS Table 3 Other Pins (cont...) Pin Number 17 18 19, 20 23, 24 25, 26 28 29 30 33 34 35 37 Symbol FrSync MFrSync O1POS, O1NEG SEC1_POS, SEC1_NEG SEC2_POS, SEC2_NEG SYNC1 SEC1 SEC2 SYNC2 SEC3 SYNC3 TRST I/O O O O I I I I I I I I I Type TTL/CMOS TTL/CMOS LVDS/PECL PECL/LVDS PECL/LVDS TTLD TTLD TTLD TTLD TTLD TTLD TTLD Description Output Reference: 8 kHz Frame Sync output. Output Reference: 2 kHz Multi-Frame Sync output. Output Reference: Programmable, default 38.88 MHz, LVDS. Input Reference: Programmable, default 19.44 MHz, PECL. Input Reference: Programmable, default 19.44 MHz PECL. (Master) Multi-Frame Sync 2kHz Input: Connect to 2 or 8 kHz Multi-Frame Sync output of Master SETS. (Master) Input Reference: Programmable, default 8 kHz. (Slave) Input Reference: Programmable, default 8 kHz. (Slave) Multi-Frame Sync 2 kHz: Connect to 2 or 8 kHz Multi-Frame Sync output of Slave SETS. (Stand-by) Input Reference: External stand-by reference clock source, programmable, default 19.44MHz. (Stand-by) Input Reference: External stand-by 2 or 8 kHz Multi-Frame Sync clock source. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 is Boundary Scan stand-by mode, still allowing normal device operation (JTAG logic transparent). NC if not used. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of SCLK to be active. Serial Interface Address: Serial Data Input. Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface. Serial Data Clock. When this pin goes High data is latched from SDI pin. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. Interface Address: SPI compatible Serial Data Output. Output Reference: Programmable, default 19.44 MHz. SONET or SDH Frequency Select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. FINAL DATASHEET 41 42 43 44 47 48 49 50 51 52 56 64 TMS CLKE SDI CSB SCLK PORB TCK TDO TDI SDO O2 SONSDHB I I I I I I I O I O O I TTLD TTLD TTLD TTL U TTLD TTL U TTLD TTL/CMOS TTLD TTLD TTL/CMOS TTLD Revision 3.01/August 2005 © Semtech Corp. Page 6 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS Introduction FINAL DATASHEET The DPLLs are clocked by the external Oscillator module (TCXO or XO) so that the Free-run or Digital Holdover frequency stability is only determined by the stability of the external oscillator module. This second key advantage confines all temperature critical components to one well defined and pre-calibrated module, whose performance can be chosen to match the application. All performance parameters of the DPLLs are programmable without the need to understand detailed PLL equations. Bandwidth, damping factor and lock range can all be set directly. The ACS8525 includes an SPI compatible serial interface port, providing access to the configuration and status registers for device setup, external control and monitoring. The device is primarily controlled according to values in this Register block. Each register (8-bit wide data field) is identified and referred to by its two-digit hexadecimal address and name, e.g. Reg. 7D cnfg_interrupt. The “Register Map” on page 38 summarizes the content of all of the registers, and each register is individually described in the subsequent Register Tables, organized in order of ascending Address (hexadecimal), in the “Register Descriptions” from page 42 onwards. An Evaluation Board and intuitive GUI-based software package is available for this device to help designers learn how to use the ACS8525 and rapidly configure the device for particular applications. This has its own documentation: “ACS8525-EVB”. The ACS8525 is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for Line Cards in a SONET or SDH Network Element. The ACS8525 has fast activity monitors on the SEC clock inputs and will implement automatic system protection switching against failure of the selected clock. The selection of the Master/Slave input can be forced by a Force Fast Switch pin. The Stand-by “Group” is selected if both the Master and Slave input clocks fail, or, if not available, the device enters a Digital Holdover mode. Digital Phase Locked Loop (DPLL) and Direct Digital Synthesis (DDS) methods are used in the device so that the overall PLL characteristics are very stable and consistent compared to traditional analog PLLs. The ACS8525 has three SEC/SYNC input groups from which it can select any group as input. It generates independent clocks on outputs 01 and 02, with a total of 53 possible output frequencies, and generates two Sync outputs on outputs FrSync and MFrSync: 8 kHz Frame Synchronization (FrSync) signal and 2 kHz Multi-Frame Synchronization (MFrSync) signal. The device has three main operating modes (states); Free-run, Locked, or Digital Holdover. In Free-Run mode, the ACS8525 generates a stable, low-noise clock signal at a frequency to the same accuracy as the external oscillator, or it can be made more accurate via software calibration to within ±0.02 ppm. In Locked mode, the ACS8525 selects the most appropriate of the three input SECs and generates a stable, low-noise clock signal locked to the selected reference. In Digital Holdover mode, the ACS8525 generates a stable, low-noise clock signal, adjusted to match the frequency of the last selected SEC. One key architectural advantage that the ACS8525 has over traditional solutions is in the use of DPLL technology for precise and repeatable performance over temperature or voltage variations and between parts. The overall PLL bandwidth, loop damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. An Analog PLL (APLL) takes the signal from the DPLL output and provides a lower jitter output. The APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. Revision 3.01/August 2005 © Semtech Corp. General Description The following description refers to the Block Diagram (Figure 1 on page 1). Inputs The ACS8525 SETS device has input ports for input clock groups from three sources, typically Master, Slave and Stand-by, where each clock group comprises one SEC and optionally one Sync signal. This is so that when any SEC input changeover is made, the corresponding Sync signal changeover is also made. TTL/CMOS and PECL/LVDS ports are provided for the Master and Slave SEC inputs to the device. The Stand-by SEC input and three Frame Sync/Multi-frame Sync inputs to the device are via TTL Ports. All the TTL/CMOS parts are 3 V and 5 V compatible (with clamping if required by connecting the VDD5V pin). Refer to the “Electrical www.semtech.com Page 7 ACS8525 LC/P ADVANCED COMMUNICATIONS Specifications” on page 98 for more information on electrical compatibility. Input frequencies supported range from 2 kHz to 155.52 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. Any input frequency, up to 100 MHz, that is a multiple of 8 kHz can also be locked to via an inbuilt programmable divider. FINAL DATASHEET Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. SDH and SONET networks use different default frequencies; the network type is selectable using the cnfg_input_mode Reg. 34 Bit 2, ip_sonsdhb. For SONET, ip_sonsdhb = 1 For SDH, ip_sonsdhb = 0 On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 64). Specific frequencies and priorities are set by configuration. The frequency selection is programmed via the cnfg_ref_source_frequency register (Reg. 22 - Reg. 28). Preconfiguring Inputs Each input device has to be preconfigured with: Expected input frequency cnfg_ref_source_frequency register (Reg. 22 to 25 and Reg. 28) Technology (TTL or PECL/LVDS) where applicable, via cnfg_differential_inputs (Reg. 36) Selection Priority (Reg. 19, 1A and 1C). Table 4 Input Reference Source Selection and Priority Table Port Name SEC1 TTL SEC2 TTL SEC1 DIFF SEC2 DIFF SYNC1 SYNC2 SEC3 SYNC3 Channel Number (Bin) 0011 0100 0101 0110 0111 1000 1001 1010 Input Port Technology TTL/CMOS TTL/CMOS PECL/LVDS PECL default PECL/LVDS PECL default TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS Frequencies Supported Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 2/4/8 kHz auto-sensing 2/4/8 kHz auto-sensing Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 2/4/8 kHz auto-sensing 2 3 0 0 n/a n/a 4 n/a Default Priority Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb). (ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for Output O1 only). (iii) SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly SEC2DIFF uses pins SEC2POS and SEC2NEG. Revision 3.01/August 2005 © Semtech Corp. Page 8 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS PECL/LVDS Input Port Selection The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL differential inputs should be fixed with one input High (VDD) and the other input Low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled High and the other Low. FINAL DATASHEET DivN = “Divide by N + 1”, i.e. it is the dividing factor used for the division of the input frequency, and has a value of (N + 1) where N is an integer from 1 to 15624 inclusive. Therefore, in DivN mode the input frequency can be divided by any integer value between 2 to 15625. Consequently, any input frequency which is a multiple of 8 kHz, between 8 kHz and 125 MHz, can be supported by using DivN mode. Note...Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. However only one value of N is allowed, so all inputs with DivN selected must be running at the same frequency. DivN Examples Input Locking Frequency Modes Each input port has to be configured to receive the expected input frequency. To achieve this, three Input Locking Frequency modes are provided: Direct Lock, Lock8K and DivN. Direct Lock Mode (a) To lock to 2.000 MHz: (i) Set the cnfg_ref_source_frequency register to 10XX0000 (binary) to enable DivN, and set the frequency to 8 kHz - the frequency required after division. (XX = “Leaky Bucket” ID for this input). In Direct Lock mode, DPLL1 can lock to the selected input at the spot frequency of the input, for example 19.44 MHz performs the DPLL phase comparisons at 19.44 MHz. In Lock8K and DivN modes (and for the special case of 155 MHz), an internal divider is used prior to DPLL1 to divide the input frequency before it is used for phase comparisons. Direct Lock Mode 155 MHz. The max frequency allowed for phase comparison is 77.76 MHz, so for the special case of a 155 MHz input set to Direct Lock mode, there is a divide-by-two function automatically selected to bring the frequency down to within the limits of operation. Lock8K Mode (ii) To achieve 8 kHz, the 2 MHz input must be divided by 250. So, if DivN = 250 = (N + 1) then N must be set to 249. This is done by writing F9 hex (249 decimal) to the DivN register pair Reg. 46/47. (b) To lock to 10.000 MHz: (i) The cnfg_ref_source_frequency register is set to 10XX0000 (binary) to set the DivN and the frequency to 8 kHz, the post-division frequency. (XX = “Leaky Bucket” ID for this input). Lock8K mode automatically sets the divider parameters to divide the input frequency down to 8 kHz. Lock8K can only be used on the supported spot frequencies (see Table 4 Note(i)). Lock8k mode is enabled by setting the Lock8k bit (Bit 6) in the appropriate cnfg_ref_source_frequency register location. Using lower frequencies for phase comparisons in the DPLL results in a greater tolerance to input jitter. It is possible to choose which edge of the input reference clock to lock to, by setting 8K Edge Polarity (Bit 2 of Reg. 03, test_register1). DivN Mode (ii) To achieve 8 kHz, the 10 MHz input must be divided by 1,250. So, if DivN, = 250 = (N+1) then N must be set to 1,249. This is done by writing 4E1 hex (1,249 decimal) to the DivN register pair Reg. 46/47. Input SEC Activity Monitors An input reference activity monitor is assigned to each of the three SEC inputs. The monitors operate continuously such that at all times the activity status of each SEC input is known. SEC activity monitoring is used to declare whether or not an input is valid. Any SEC that suffers a loss-of-activity will be declared as invalid and unavailable for selection. SEC activity monitoring is a continuous process which is used to identify clock problems. There is a difference in www.semtech.com In DivN mode, the divider parameters are set manually by configuration (Bit 7 of the cnfg_ref_source_frequency register), but must be set so that the frequency after division is 8 kHz. The DivN function is defined as: Revision 3.01/August 2005 © Semtech Corp. Page 9 ACS8525 LC/P ADVANCED COMMUNICATIONS FINAL DATASHEET dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected SECs affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. occur over a greater time period but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. Similarly, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). Figure 3 illustrates the behavior of the Leaky Bucket Accumulator. Each SEC input is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The Accumulator will continue to increment up to the point that it reaches the programmed Bucket size. The “fill rate” of the Leaky Bucket is, therefore, 8 units/second. The “leak rate” of the Leaky Bucket is programmable to be in multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to “leak” at the same time as a “fill” is avoided by preventing a leak when a fill event occurs. Leaky Bucket Accumulator Anomalies detected by the Activity Monitor are integrated in a Leaky Bucket Accumulator. There is one Leaky Bucket Accumulator per SEC input. Each Leaky Bucket can be programmed with a Bucket ID (0 to 3) which assigns to the Leaky Bucket the corresponding Leaky Bucket Configuration (from four available Configurations). Each Leaky Bucket Configuration comprises the following programmable parameters (See Reg. 50 to Reg. 5F): Bucket size Alarm trigger (set threshold) Alarm clear (reset threshold) Leak rate (decay rate) There are occasional anomalies that do not cause the Accumulator to cross the alarm setting threshold, so the selected SEC is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected SEC being rejected. Each Leaky Bucket Accumulator is a digital circuit which mimics the operation of an analog integrator. If several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events Figure 3 Inactivity and Irregularity Monitoring Inactivities/Irregularities Reference Source bucket_size Leaky Bucket Response Programmable Fall Slopes upper_threshold lower_threshold (all programmable) Alarm Revision 3.01/August 2005 © Semtech Corp. Page 10 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS FINAL [21 x (8 - 4)] /8 = 1.0 secs DATASHEET Disqualification of a non-selected SEC is based on inactivity noted by the Activity Monitors. The currently selected SEC can be disqualified for being out-of phase, inactive, or if the source is outside the DPLL lock range. If the currently selected SEC is disqualified, the next highest priority qualified SEC is selected. Interrupts for Activity Monitors The default setting is shown in the following: Fast Activity Monitor Anomalies on the selected clock have to be detected as they occur and the PLL must be temporarily isolated until the clock is once again pure. The SEC activity monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required, the PLL requires an alternative mechanism. The phase locked loop itself contains a fast activity detector such that within approximately two missing input clock cycles, a no-activity flag is raised and the DPLL is frozen in Digital Holdover mode. This flag can also be read as the DPLL1 main_ref_failed bit (from Reg. 06 sts_interrupts, Bit 6) and can be set to indicate a phase lost state by enabling Reg. 73, Bit 6. With the DPLL in Digital Holdover mode it is isolated from further disturbances. If the input becomes available again before the activity monitor rejection alarm has been raised, then the DPLL will continue to lock to the input, with little disturbance. In this scenario, with the DPLL in the “locked” state, the DPLL uses “nearest edge locking” mode (±180° capture) avoiding cycle slips or glitches caused by trying to lock to an edge 360° away, as would happen with traditional PLLs. The loss of the currently selected SEC will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the Leaky Bucket Configuration of the activity monitors. The fastest Leaky Bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected SEC is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the SEC. Some applications require the facility to switch downstream devices based on the status of the SECs. In order to provide extra flexibility, it is possible to flag the main_ref_failed interrupt (Reg. 06 Bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to Reg. 48 Bit 6. Leaky Bucket Timing The time taken (in seconds) to raise an inactivity alarm on an SEC that has previously been fully active (Leaky Bucket empty) will be: (cnfg_upper_threshold_n) / 8 where n is the number of the Leaky Bucket Configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_upper_threshold_n is 6, therefore the default time is 0.75 s. The time taken (in seconds) to cancel the activity alarm on a previously completely inactive SEC is calculated, for a particular Leaky Bucket, as: [2 (a) x (b - c)]/ 8 where: a = cnfg_decay_rate_n b = cnfg_Bucket_size_n c = cnfg_lower_threshold_n (where n = the number of the relevant Leaky Bucket Configuration in each case). Revision 3.01/August 2005 © Semtech Corp. Selector This block has two main functions: Selection of the Input reference clock source via Reg. 33 force_select_reference_source Forcing of the Operating mode of the device, via Reg. 32 cnfg_operating_mode Selection of Input SECs Under normal operation, the input SECs are selected automatically by an order of priority given in the Priority Table. For special circumstances however, such as chip or board testing, the selection may be forced by configuration. Automatic operation selects an SEC based on its predefined priority and its current validity. A table is maintained which lists all valid SECs in the order of priority. This is initially downloaded into the ACS8525 via the Serial interface by the Network Manager, and is subsequently modified by the results of the ongoing quality monitoring. In this way, when all the defined Page 11 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS FINAL DATASHEET sources are active and valid, the source with the highest programmed priority is selected, but if this source fails, the next-highest source is selected, and so on. Restoration of repaired SECs is handled carefully to avoid inadvertent disturbance of the output clock. For this, the ACS8525 has two modes of operation; Revertive and Non-revertive. In Revertive mode, if a re-validated (or newly validated) source has a higher priority than the SEC which is currently selected, a switchover will take place. Many applications prefer to minimize the clock switching events and choose Non-revertive mode. In Non-revertive mode, when a re-validated (or newly validated) source has a higher priority, then the selected source will be maintained. The re-validation of the SEC will be flagged in the sts_sources_valid register (Reg. 0E and 0F) and, if not masked, will generate an interrupt. Selection of the re-validated source can take place under software control or if the currently selected source fails. To enable software control, the software should briefly enable Revertive mode to effect a switch-over to the higher priority source. When there is a reference available with higher priority than the selected reference, there will be NO change of SEC as long as the Non-revertive mode remains on, and the currently selected source is valid. A failure of the selected reference will always trigger a switch-over regardless of whether Revertive or Non-revertive mode has been chosen. Forced Control Selection The Priority Table register cnfg_ref_selection_priority, occupying three 8-bit register addresses (Reg. 19, 1A and 1C), is organized as one 4-bit word per input SEC port. Each 4 bit word represents the desired priority of that particular port. Unused ports should be given the value 0000 in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the input priority configuration is set to the default values defined by Table 4. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each SEC should be given a unique number; the valid values are 1 to 15 (dec). A value of 0 disables the SEC. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. Revertive/Non-revertive mode has no effect on sources with the same priority value. The priority of Sync inputs is determined by the priority of their associated SEC inputs. The Sync inputs do not have their own separate priority table. Ultra Fast Switching A configuration register, force_select_reference_source Reg. 33, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). For Automatic choice of source selection, the 4 LSB bit value force_select_SEC_input is set to all zeros or all ones (default). To force a particular input, the bit value is set according to the description for Reg. 33. Forced selection is not the normal mode of operation, and force_select_SEC_input defaults to the all-ones value on reset, thereby adopting the automatic selection of the SEC. Automatic Control Selection - Priority Table An SEC is normally disqualified after the Leaky Bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if Reg. 48 Bit 5 (ultra_fast_switch) is set, then a loss of activity of just two or three reference clock cycles causes a reference switch, and sets the DPLL1_main_ref_failed bit (see Reg. 06 Bit 6) which raises an interrupt (if not masked). The sts_interrupts register Reg. 06 Bit 6 (DPLL1_main_ref_failed) is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If Reg. 48 Bit 6 of the cnfg_monitors register (los_flag_on_TDO) is set, then the state of this bit is driven onto the TDO pin of the device. Note...The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupts bit DPLL1_main_ref_failed to be reflected in the state of the TDO output pin. The pin will, therefore, remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When the TDO output from the ACS8525 is connected to the TDI pin of the next When an automatic selection is required, the force_select_reference_source register LSB 4 bits (force_select_SEC_input) must be set to all zeros or all ones. Revision 3.01/August 2005 © Semtech Corp. Page 12 www.semtech.com ACS8525 LC/P ADVANCED COMMUNICATIONS FINAL DATASHEET device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. on to the indicated reference source. Consequently the device will always indicate “Locked” state in the operating mode register (Reg. 09, Bits 2:0). External Protection Switching Mode-SRCSW pin External Protection Switching mode, for fast switching between inputs SEC1 or SEC2, can be triggered directly from the dedicated pin SRCSW, once the mode has been initialized. The mode is initialized by either holding SRCSW pin High during reset (SRCSW must remain High for at least a further 251 ms after PORB has gone High - see following Note), or by writing to Reg. 48 Bit 4. After External Protection Switching mode has been initialized, the value on this pin directly selects either SEC1 (SRCSW High) or SEC2 (SRCSW Low). If this mode is activated at reset by pulling the SRCSW pin High, then it configures the default frequency tolerance of SEC1 and SEC2 to ±80 ppm (Reg. 41 and Reg. 42), as opposed to the normal frequency tolerance of ±9.2 ppm. These registers can be subsequently set by external software, if required. Note...The 251 ms comprises 250 ms allowance for the internal reset to be removed plus 1 ms allowance for APLLs to start-up and become stable. Output Clock Phase Continuity on Source Switchover If either PBO is selected on (default), or, if DPLL frequency limit set to less than ±30 ppm (±9.2 ppm default), the device will always comply with GR-1244-CORE[13] specifications for Stratum 3 (max rate of phase change of 81 ns/1.326 ms), for all input frequencies. A well designed system would have Master and Slave clock from the clock sync cards aligned to within a few nanoseconds. In which case a complete system using the Semtech SETS clock card parts (ACS8530, ACS8520 or ACS8510) and this Line Card part would be fully compliant to GR-1244-CORE[13] specifications under all conditions due to the low frequency range and bandwidth set at the clock card end. These parts and the ACS8525 LC/P also allow easy frame sync (8 kHz) alignment both at the clock card and at the Line Card end through the use of dedicated frame sync (8 kHz) inputs, in addition to the main clock inputs. Forcing of the Operating Mode of the Device The Selector can force the following Operating modes, (cnfg_operating_mode, Reg. 32): Auto Free-run Holdover Locked Lost-phase Pre-locked Pre-locked2 See “Operating Modes (States) of the Device” on page 30. The control of TTL or DIFF selection for inputs SEC1 and SEC2 is independently determined by the priority values of the TTL inputs; if the programmed priority of SEC1 TTL is 0, then SEC1 DIFF is available for selection by SRCSW pin; similarly, if SEC2 TTL is 0 priority, SEC2 DIFF is available for selection by SRCSW pin (See Reg. 19 and 1A cnfg_ref_selection_priority and Figure 4). Figure 4 SEC1 and SEC2 Switching SEC1 TTL Priority >0 SRCSW SEC1 TTL 1 1 SEC1 DIFF 0 DPLL1 SEC2 TTL 1 0 SEC2 DIFF 0 SEC2 TTL Priority >0 F8525D_006secSwitch_01 Phase Locked Loops (PLLs) PLL Overview Figure 1 shows the PLL circuitry to comprise two Digital PLLs (DPLL1 and DPLL2), two output multiplying and filtering Analog PLLs (APLL1 and APLL2), output frequency dividers in an Output Port Frequency Selection block, a synthesis block, multiplexers MUX1 and MUX2, and a feedback Analog PLL (APLL3). These functional blocks, and their interconnections are highly configurable, www.semtech.com When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock Revision 3.01/August 2005 © Semtech Corp. Page 13 ACS8525 LC/P ADVANCED COMMUNICATIONS via register control, which provides a range of output frequencies and levels of jitter performance. The DPLLs give a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating range. They are not affected by operating conditions or silicon process variations. Digital Synthesis is used to generate all required SONET/SDH output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.800 MHz oscillator module. Hence the best resolution of the output signals from the DPLLs is one 204.8 MHz cycle or 4.9 ns. Additional resolution and lower final output jitter is provided by a de-jittering APLL that reduces the 4.9 ns p-p jitter from the digital down to 500 ps p-p and 60 ps RMS as typical final outputs measured broadband (from 10 Hz to 1 GHz). This arrangement combines the advantages of the flexibility and repeatability of a DPLL with the low jitter of an APLL. The DPLLs in the ACS8525 are programmable for PLL parameters of bandwidth (18, 35 and 70 Hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0 to 80 ppm, typically 9.2 ppm), input frequency (12 common SONET/SDH spot frequencies) and input-to-output phase offset (in 6 ps steps up to 200 ns). There is no requirement to understand the loop filter equations or detailed gain parameters since all high level factors such as overall bandwidth can be set directly via registers in the microprocessor interface. No external critical components are required for either the internal DPLLs or APLLs, providing another key advantage over traditional discrete designs. Either the software or an internal state machine controls the operation of DPLL1. The state machine for DPLL2 is very simple and cannot be manually/externally controlled. One additional feature of DPLL2 is the ability to measure a phase difference between two inputs. DPLL1 always produces an output at 77.76 MHz to feed the APLL, regardless of the frequency selected at the output pins or the locking frequency (frequency at the input of the Phase and Frequency Detector- PFD). DPLL2 can be operated at a number of frequencies. This is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz. If DPLL2 is enabled, it locks to the 8 kHz from DPLL1. This is because all of the frequencies of operation of DPLL2 can be Revision 3.01/August 2005 © Semtech Corp. FINAL DATASHEET divided to 8 kHz and this will ensure synchronization of frequencies, from 8kHz upwards, within the two DPLLs. Both of the DPLLs’ outputs can be connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number of frequencies simultaneously available for selection at the output clock ports. The various combinations of DPLL, APLL and divider configurations allow for generation of a comprehensive set of frequencies, as listed in Table 7, “Output Frequency Selection,” on page 22. A function is provided to synchronize the lower output frequencies when DPLL1 is locked to a high frequency reference input. The dividers that generate the 2 kHz and 8 kHz outputs are reset such that the output 2/8 kHz clocks are lined up with the input 2 kHz. The ACS8525 also supports Sync pulse references of 4 kHz or 8 kHz although in these cases frequencies lower than the Sync pulse reference may not necessarily be in phase. The PLL configurations for particular output frequencies is described in “Output Frequency Selection and PLL Configuration” on page 22. PLL Architecture Figure 5 shows the PLL arrangement in more detail. Each DPLL comprises a generic Phase and Frequency Detector (PFD), a Digital Loop filter, and a Digital Timed Oscillator (DTO- not shown); together with Forward, Feedback, and Low Frequency (LF) (DPLL1 only) Digital Frequency Synthesis (DFS) blocks. The DPLL architecture for DPLL1. is actually more complex than that of DPLL2, and provides greater functionality. The selected SEC input is always supplied to DPLL1. DPLL1 may use either digital feedback or analog feedback (via APLL3). DPLL2 always takes its feed from DPLL1 and cannot be used to select a different input to that of DPLL1, except in the case where the device is being used to measure phase difference between input sources. In this case, the PFD of DPLL2 is used for phase measurement and the DPLL2 normal output is rendered unusable. DPLL1 and APLLs DPLL1 always produces 77.76 MHz regardless of either the reference frequency (frequency at the input pin of the device) or the locking frequency (frequency at the input of the DPLL PFD). www.semtech.com Page 14 ACS8525 LC/P ADVANCED COMMUNICATIONS Figure 5 PLL Block Diagram FINAL DATASHEET DPLL2 Reference Input for phase measurement only DPLL2_meas_ DPLL1_ph 1 sts_current_phase DPLL2_frequency DPLL1_freq_to_APLL2 PFD and Loop Filter DPLL2_meas_ 0 DPLL1_ph 0 Locking Frequency Forward DFS 0 DPLL2_dig_ feedback 1 MUX 2 1 APLL2 APLL2 Output Dividers 01 and 02 Feedback DFS 1 0 DPLL2 8 k Hz DPLL1_frequency 0 77M Output DFS Phase Offset 1 sts_current_phase DPLL1 Reference Input 0 LF Output DFS 1 1 APLL1 APLL1 Output Dividers 01 and 02 PBO FrSync MFrSync O1 and O2 APLL3 PFD and Loop Filter 77M Forward DFS 1 DPLL1_frequency Locking Frequency Feedback DFS 0 DPLL1 Analog F8525D_017BLOCKDIA_03 The input reference is either passed directly to the PFD or via a pre-divider (not shown) to produce the reference input. The feedback 77.76 MHz is either divided or synthesized to generate the locking frequency. Any Digital Frequency Synthesis (DFS) generated clock will inherently have jitter on it equivalent to one period of the generating clock (p-p). The DPLL1 77M Forward DFS block uses DFS clocked by the 204.8 MHz system clock to synthesize the 77.76 MHz and, therefore, has an inherent 4.9 ns of p-p jitter. There is an option to use a feedback APLL (APLL3) to filter out this jitter before the 77.76 MHz is used to generate the feedback locking frequency in the DPLL1 feedback DFS block. This analog feedback option allows a lower jitter (