ACS8526

Line Card Protection Switch for PDH, SONET or SDH Systems ADVANCED COMMUNICATIONS Description FINAL Features DATASHEET ACS8526 LC/P LITE The ACS8526 is a highly integrated single-chip solution for protection switching between two SECs (SDH/SONET Equipment Clocks) from Master and Slave SETS clock cards, for line cards in a PDH, SONET or SDH Network Element. The ACS8526 has fast activity monitors on the inputs and will raise a flag on a pin if there is a loss of activity on the currently selected input. The protection switching between the input reference clock sources is controlled by an external pin. The ACS8526 has two SEC reference clock input ports, configured for expected frequency by setting hardware pins or by writing to registers via the serial interface. The ACS8526 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. The ACS8526 generates two independent SEC clock outputs, one on a PECL/LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins, or by writing to registers via the serial interface. The hardware selectable spot frequencies range from 1.544 MHz up to 155.52 MHz, with further options for N x E1/DS1 and 311.04 MHz via register selection. The ACS8526 also provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output, both with programmable pulse width and polarity. Advanced configuration possibilities are available via the serial port (which can be SPI compatible), however the basic configuration of I/O frequencies and SONET/SDH selection by hardware make the device suitable for standalone operation, i.e., no need for a microprocessor. Block Diagram Figure 1 Block Diagram of the ACS8526 LC/P LITE LOS_ALARM IP_FREQ SONSDHB 2 x SEC TTL inputs SEC1 SEC Inputs: Programmable Frequencies N x 8 kHz SEC2 1.544 MHz 2.048 MHz 6.48 MHz 19.44 MHz SRCSW 25.92 MHz 38.88 MHz TCK 51.84 MHz TDI 77.76 MHz TMS TRST TDO Input SEC Port Selector Digital Feedback E1/DS1 Synthesis APLL3 DPLL1 DPLL2 Line card protection switch - partners Semtech SETS devices for Stratum 3E/3/4E/4 PDH, SONET or SDH applications High performance DPLL/APLL solution Output jitter compliant to STM-1 Two independent SEC inputs ports (TTL) Four independent output ports: Two clock ports: one PECL/LVDS, one TTL Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz PECL/LVDS port: spot frequencies 2 kHz to 311 MHz N x E1/DS1 mode Programmable pulse width and polarity on Syncs SONET/SDH frequency translation Digital Holdover mode on input failure Separate activity monitors and register alarms on each input. “Loss of activity” on selected input flagged on dedicated pin Source switch under external hardware control PLL “Locked” and “Acquisition” bandwidth selectable from 18, 35 or 70 Hz Configurable via serial interface or hardware pins Output clock phase continuity to GR-1244-CORE[13] Single 3.3 V operation, 5 V I/O compatible IEEE 1149.1 JTAG Boundary Scan is supported Operating temperature (ambient) of -40 to +85°C Available in LQFP 64 package Lead (Pb)-free version available (ACS8526T), RoHS and WEEE compliant. MUX 2 SEC Outputs: 01 (LVDS/PECL) APLL2 Output Port Frequency Selection 02 (TTL) Sync Outputs: MFrSync 2 kHz (TTL) MUX 1 APLL 1 FrSync 8 kHz (TTL) Output Frequencies/MHz 01 Output: 02 Output: 19.44 1.544 25.92 2.048 34.368 (E3) 3.088 38.88 19.44 44.736 (DS3) 25.92 51.84 34.368 (E3) 77.76 38.88 155.52 44.736 (DS3) 51.84 77.76 IEEE 1149.1 JTAG Chip Clock Generator Priority Register Set Table SPI Compatible Serial Interface Port TCXO or XO F8526D_001BLOCKDIA_03 OP_FREQ1 OP_FREQ2 Revision 4.01/June 2006 © Semtech Corp. Page 1 www.semtech.com Table of Contents ADVANCED COMMUNICATIONS Table of Contents Section ACS8526 LC/P LITE DATASHEET Page FINAL Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 3 Pin Description........................................................................................................................................................................................... 4 Introduction................................................................................................................................................................................................ 6 General Description................................................................................................................................................................................... 6 Inputs ..................................................................................................................................................................................................6 Preconfiguring Inputs - Expected Input Frequency ................................................................................................................ 7 Preconfiguring Inputs- SONET/SDH ........................................................................................................................................ 7 Input Locking Frequency Modes ............................................................................................................................................. 7 Selection of Input SECs .....................................................................................................................................................................8 Initialization .............................................................................................................................................................................. 8 SEC Selection - SRCSW pin...................................................................................................................................................... 8 Output Clock Phase Continuity on Source Switchover .......................................................................................................... 8 Activity Monitors.................................................................................................................................................................................9 SEC Activity Monitors ............................................................................................................................................................... 9 Fast Activity Monitor.............................................................................................................................................................. 10 Phase Locked Loops (PLLs) ........................................................................................................................................................... 10 PLL Overview ......................................................................................................................................................................... 10 PLL Architecture .................................................................................................................................................................... 11 PLL Operational Controls ...................................................................................................................................................... 14 DPLL Feature Summary ........................................................................................................................................................ 16 Outputs ............................................................................................................................................................................................ 17 Output Frequency Selection by Hardware ........................................................................................................................... 17 Output Frequency Selection by Register Programming...................................................................................................... 17 Power-On Reset............................................................................................................................................................................... 25 Local Oscillator Clock...................................................................................................................................................................... 27 Crystal Frequency Calibration............................................................................................................................................... 27 Status Reporting ............................................................................................................................................................................. 27 Loss of Input Signal - LOS Flag ............................................................................................................................................. 27 Status Information ................................................................................................................................................................ 27 Serial Interface................................................................................................................................................................................ 27 Register Map........................................................................................................................................................................................... 30 Register Organization ..................................................................................................................................................................... 30 Multi-word Registers ............................................................................................................................................................. 30 Register Access ..................................................................................................................................................................... 30 Flags ....................................................................................................................................................................................... 30 Defaults.................................................................................................................................................................................. 30 Register Descriptions ............................................................................................................................................................................. 32 Electrical Specifications ......................................................................................................................................................................... 61 JTAG ................................................................................................................................................................................................. 61 Over-voltage Protection .................................................................................................................................................................. 61 ESD Protection ................................................................................................................................................................................ 61 Latchup Protection.......................................................................................................................................................................... 61 Maximum Ratings ........................................................................................................................................................................... 62 Operating Conditions ...................................................................................................................................................................... 62 Jitter Performance .......................................................................................................................................................................... 65 Input/Output Timing ....................................................................................................................................................................... 67 Package Information .............................................................................................................................................................................. 68 Thermal Conditions......................................................................................................................................................................... 69 Application Information .......................................................................................................................................................................... 70 References .............................................................................................................................................................................................. 71 Abbreviations .......................................................................................................................................................................................... 71 Notes ....................................................................................................................................................................................................... 72 Trademark Acknowledgements ............................................................................................................................................................. 72 Revision Status/History ......................................................................................................................................................................... 73 Ordering Information .............................................................................................................................................................................. 74 Disclaimers...................................................................................................................................................................................... 74 Contacts........................................................................................................................................................................................... 74 Revision 4.01/June 2006 © Semtech Corp. Page 2 www.semtech.com ACS8526 LC/P LITE ADVANCED COMMUNICATIONS Pin Diagram Figure 2 ACS8526 Pin Diagram FINAL DATASHEET 1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 AGND1 IC1 AGND2 VA1+ LOS_ALARM REFCLK DGND1 VD1+ VD2+ DGND2 DGND3 VD3+ SRCSW VA2+ AGND3 IC2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SONSDHB O1_FREQ2 IC9 IC8 IC7 NC2 AGND4 VA3+ O2 NC1 VDD3 DGND6 SDO TDI TDO TCK ACS8526 LC/P LITE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PORB SCLK O1_FREQ1 O1_FREQ0 CSB SDI CLKE TMS DGND5 VDD2 O2_FREQ1 TRST O2_FREQ2 O2_FREQ0 IP_FREQ2 IP_FREQ1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF IC3 IC4 IC5 IC6 VDD5V IP_FREQ0 SEC1 SEC2 DGND4 VDD1 F8526D_002PINDIAG_01 Revision 4.01/June 2006 © Semtech Corp. Page 3 www.semtech.com ACS8526 LC/P LITE ADVANCED COMMUNICATIONS Pin Description Table 1 Power Pins Pin Number 8, 9, 12 22 27 Symbol VD1+, VD2+, VD3+ VDD_DIFF VDD5V I/O P P P Type Description Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts ±10%. Digital Supply for +5 Volts tolerance to input pins. Connect to +5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%. Supply Voltage: Analog supply to output PLLs APLL2 and APLL1, +3.3 Volts ±10%. Supply Ground: Analog ground for output PLLs APLL2 and APLL1. Supply Ground: Digital ground for components in PLLs. Supply Ground: Digital ground for logic. Supply Ground: Digital ground for differential output pins 19 and 20. Supply Ground: Analog grounds. FINAL DATASHEET 32, 39, 54 4 14, 57 15, 58 7, 10, 11 31, 40, 53 21 1, 3 VDD1, VDD2, VDD3, VA1+ VA2+, VA3+ AGND3, AGND4 DGND1, DGND2, DGND3 DGND4, DGND5, DGND6 GND_DIFF AGND1, AGND2 P P P - P P P P - Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Internally Connected Pin Number 2, 16, 23, 24, 25, 26, 60, 61, 62 55, 59 Symbol IC1, IC2, IC3, IC4, IC5, IC6, IC7, IC8 IC9 NC1, NC2 I/O Type Description Internally Connected: Leave to float. - - Not Connected: Leave to float. Table 3 Other Pins Pin Number 5 6 13 Symbol LOS_ALARM REFCLK SRCSW I/O O I I Type TTL/CMOS TTL TTLD Description LOS_Alarm: Flag to indicate loss of activity of currently selected reference source. Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). Source Switching: Controls switchover between SEC1 and SEC2 inputs as the selected reference. SRCSW must be held High on power-up or reset, and for a further 251 ms after PORB has gone High. See “Initialization” on page 8. Output Reference: 8 kHz Frame Sync output. 17 FrSync O TTL/CMOS Revision 4.01/June 2006 © Semtech Corp. Page 4 www.semtech.com ACS8526 LC/P LITE ADVANCED COMMUNICATIONS Table 3 Other Pins (cont...) Pin Number 18 19, 20 28 29 30 33 34 35 36 37 38 41 42 43 44 45 46 47 Symbol MFrSync O1POS, O1NEG IP_FREQ0 SEC1 SEC2 IP_FREQ1 IP_FREQ2 O2_FREQ0 O2_FREQ2 TRST O2_FREQ1 TMS CLKE SDI CSB O1_FREQ0 O1_FREQ1 SCLK I/O O O I I I I I I I I I I I I I I I I Type TTL/CMOS LVDS/PECL TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLU TTLU TTLU TTLD Description Output Reference: 2 kHz Multi-Frame Sync output. Output Reference 1: Differential output., default LVDS. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference 1: Primary input. Input Reference 2: Secondary input. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Output O2 Frequency Select: Frequency select for output O2. Output O2 Frequency Select: Frequency select for output O2. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device operation (JTAG logic transparent). NC if not used. Output O2 Frequency Select: Frequency select for output O2. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of SCLK to be active. Interface Address: SPI compatible Serial Data Input. Chip Select (Active Low): This pin is asserted Low by the external device (microprocessor) to enable the Serial interface. Output O1 Frequency Select: Frequency select for output O1. Output O1 Frequency Select: Frequency select for output O1. Serial Data Clock: The Low to High transition on this input latches the data on the SDI input into the internal registers. The active clock edge (defined by CLKE) latches the data out of the internal registers onto the SDO output. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used. Interface Address: SPI compatible Serial Data Output. Output Reference: Programmable, default 19.44 MHz. Output O1 Frequency Select: Frequency select for output O1. SONET or SDH frequency select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after power-up by software. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. Page 5 www.semtech.com FINAL DATASHEET 48 49 50 51 52 56 63 64 PORB TCK TDO TDI SDO O2 O1_FREQ2 SONSDHB I I O I O O I I TTLU TTLD TTL/CMOS TTLD TTLD TTL/CMOS TTLU TTLD Revision 4.01/June 2006 © Semtech Corp. ACS8526 LC/P LITE ADVANCED COMMUNICATIONS Introduction FINAL DATASHEET APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. The DPLLs are clocked by the external oscillator module (TCXO or XO) so that prior to initial lock (with no input reference) or in Digital Holdover, the frequency stability is only determined by the stability of the external oscillator module. This gives the key advantage of confining all temperature critical components to one well defined and pre-calibrated oscillator module, whose performance can be chosen to match the application. All performance parameters of the DPLLs are programmable without the need to understand detailed PLL equations. Bandwidth, damping factor and lock range can all be configured under software control. The hardware set-up configures a subset of the registers in the register block, with the remainder adopting their default settings. If hardware set-up alone is insufficient for configuring, controlling and monitoring the device for a particular application, then access to the full set of registers for these purposes is provided by an SPI compatible serial interface port. Each register (8-bit wide data field) is identified by and referred to by its hexadecimal address and name, e.g. Reg. 7D cnfg_LOS_alarm. The “Register Map” on page 30 summarizes the content of all of the registers, and each register is individually described in the subsequent Register Tables, organized in order of ascending Address (hexadecimal), in the “Register Descriptions” from page 32 onwards. An Evaluation board and intuitive GUI-based software package is available for device introduction. This has its own documentation “ACS8526-EVB”. The ACS8526 is a highly integrated, single-chip solution for protection switching of two SEC inputs from, for example, Master and Slave SETS clock cards sources, for Line Cards in a SONET or SDH Network Element. The ACS8526 has fast activity monitors on the SEC clock inputs. The ACS8526 can be used as a standalone part without the serial interface where all input and output frequencies are set by external control using the IP_FREQ and OP_FREQ pins. These pins determine the default power-up or reset state of internal registers, that in turn determine the I/O frequencies. If more detailed control is required, then the registers within the device can be re-configured, after an initialization period, by writes through the serial interface. The SRCSW pin is used to select one of the two SEC inputs to lock to. The SRCSW pin must remain High for at least 251 ms following power-up or reset (251 ms after the PORB signal has gone High). SRCSW Low following a power-up or reset is not supported. The ACS8526 has two SEC inputs from which it can generate independent clocks on outputs 01 and 02 with a total of 53 possible output frequencies. In addition, there are two Sync outputs; 8 kHz Frame Synchronization (FrSync) signal and a 2 kHz Multi-Frame Synchronization (MFrSync) signal. Initially the ACS8526 generates a stable, low-noise clock signal at a frequency to the same accuracy as the external oscillator, or it can be made more accurate via software calibration to within ±0.02 ppm. The device always attempts to lock to one of its inputs (according to the value on the SRCSW pin). Once locked to a reference the accuracy of the output clock is determined directly by the accuracy of the input reference. In the absence of any input references the device simply maintains its most recent frequency in a Digital Holdover mode. However, as soon as the DPLL detects an input presence, it will attempt to lock to it and will not “qualify” it first. As soon as the DPLL detects a failure on the input, the DPLL freezes its operating frequency and raises the LOS alarm on device pin LOS_ALARM. The overall PLL loop bandwidth, damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. An Analog PLL (APLL) takes the signal from the DPLL output and provides a lower jitter output. The Revision 4.01/June 2006 © Semtech Corp. General Description The following description refers to the Block Diagram (Figure 1 on page 1). Inputs The ACS8526 SETS device has two TTL/CMOS compatible SEC input ports. They are 3 V and 5 V compatible (with clamping if required by connecting the VDD5V pin). Refer to the “Electrical Specifications” on page 61 for more information on electrical compatibility. www.semtech.com Page 6 ACS8526 LC/P LITE ADVANCED COMMUNICATIONS FINAL DATASHEET Input frequencies supported range from 2 kHz to 155.52 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. Any input frequency, up to 100 MHz, that is a multiple of 8 kHz can also be locked to via an inbuilt programmable divider. In addition to the SEC inputs, there are four configuration pins IP_FREQ [2:0] and SONSDHB used to configure the input to expect a particular input frequency (same value applies to both inputs), and a control pin SRCSW for switching between SEC1 and SEC2 as the selected input reference to which the device tries to lock. IP_FREQ [2:0] or SONSDHB will have no effect on the device configuration, as these are only read during the reset period. The register programming approach provides a greater range of frequencies than the hardware selection method: more spot frequencies, plus frequencies derived using DivN Mode up to 100 MHz (TTL technology limit). Table 4 Hardware Configuration for Selecting Expected Input Frequency on SEC1 and SEC2 IP_FREQ Pins 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 SONSDHB Pin X 0 1 X X X X X X Input frequency Preconfiguring Inputs - Expected Input Frequency The inputs SEC1 and SEC2 must be preconfigured to expect a particular input frequency. The expected input frequencies can be selected from a range of spot frequencies by either: Hardware selection: configuring the hardware pins IP_FREQ [2:0] and SONSDHB, which are read on reset Register programming: writing to the cnfg_ref_source_frequency and cnfg_input_mode registers. Hardware Selection of Expected I/P Frequency 8 kHz 2.048 MHz 1.544 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz Preconfiguring Inputs- SONET/SDH The cnfg_input_mode register bit ip_sonsdhb is used to select SDH or SONET mode for the entire device and its setting affects parameters other than just the expected input frequency selection, e.g. output frequency. To set the device for use in a SONET network, set ip_sonsdhb = 1. For SDH, set ip_sonsdhb = 0. The combined pin states of IP_FREQ [2:0] and SONSDHB represent a 4-bit word which addresses a particular frequency value as given in Table 4. The frequency selected by the hardware configuration is always applied to both inputs on Power-up or Reset, so both will be preconfigured to expect the same frequency. If SEC1 and SEC2 are required to expect different frequencies, then these inputs must be subsequently reconfigured by programming the appropriate registers. Register Programming of Expected I/P Frequency Input Locking Frequency Modes Each input port has to be configured to receive the expected input frequency. To achieve this, three input locking frequency modes are provided: Direct Lock, Lock8K and DivN. Direct Lock Mode The expected input frequencies can be programmed by writing to the cnfg_ref_source_frequency registers (Reg. 22 and 23) and ip_sonsdhb (Bit 2 of cnfg_input_mode,Reg. 34), via the serial interface. This must not be done until after the end of the initialization period (see “Initialization” on page 8). Note...Any subsequent reset will cause these registers to be overwritten by values that equate to the single hardware selected frequency on the pins at the time of reset, i.e both inputs will be configured to expect the same input frequency. After a reset and initialization period, any change of state on Revision 4.01/June 2006 © Semtech Corp. In Direct Lock mode, DPLL1 can lock to the selected input at the spot frequency of the input, for example 19.44 MHz performs the DPLL phase comparisons at 19.44 MHz. In Lock8K and DivN modes an internal divider is used prior to DPLL1 to divide the input frequency before it is used for phase comparisons. www.semtech.com Page 7 ACS8526 LC/P LITE ADVANCED COMMUNICATIONS Lock8K Mode FINAL DATASHEET frequency to 8 kHz, the post-division frequency. (XX = “Leaky Bucket” ID for this input). (ii) To achieve 8 kHz, the 10 MHz input must be divided by 1,250. So, if DivN, = 250 = (N+1) then N must be set to 1,249. This is done by writing 4E1 hex (1,249 decimal) to the DivN register pair Reg. 46/47. Lock8K mode automatically sets the divider parameters to divide the input frequency down to 8 kHz. Lock8K can only be used on the supported spot frequencies. See divn_SEC1 and 2 descriptions (Bit 7 of Reg. 22 and 23, cnfg_ref_source_frequency). Lock8k mode is enabled by setting the Lock8k bit (Bit 6) in the appropriate cnfg_ref_source_frequency register. Using lower frequencies for phase comparisons in the DPLL results in a greater tolerance to input jitter. It is possible to choose which edge of the input reference clock to lock to, by setting 8K Edge Polarity, (Bit 2 of Reg. 03, test_register1). DivN Mode Selection of Input SECs Initialization Switching between inputs SEC1 and SEC2 is triggered directly from a dedicated pin (SRCSW), though for the device to operate properly, the device must first be initialized by holding the pin High during reset and for at least a further 251 ms after PORB has gone High (250 ms allowance for the internal reset to be removed plus 1 ms allowance for APLLs to start-up and become stable). A simple external circuit to set SCRSW high for the required period is shown in the “Simplified Application Schematic” on page 70. If SCRSW is held Low at any time during the 251 ms initialization period, this will result in incorrect device operation. In DivN mode, the divider parameters are set manually by configuration (Bit 7 of the cnfg_ref_source_frequency register), but must be set so that the frequency after division is exactly 8 kHz. The DivN function is defined as: DivN = “Divide by N+ 1”, i.e. it is the dividing factor used for the division of the input frequency, and has a value of (N+1) where N is an integer from 1 to 12499 inclusive. Therefore, in DivN mode the input frequency can be divided by any integer value between 2 to 12499. Consequently, any input frequency which is a multiple of 8 kHz, between 8 kHz to 125 MHz, can be supported by using DivN mode. Note...Both reference inputs can be set to use DivN independently of the frequency and configuration of the other input. However only one value of N is allowed, so if both inputs have DivN selected, they must be running at the same frequency. DivN Examples SEC Selection - SRCSW pin After the ACS8526 has been initialized (see previous “Initialization” section), then the value of SRCSW pin directly selects either SEC1 (SRCSW High) or SEC2 (SRCSW Low). The default frequency tolerance of SEC1 and SEC2 is ±80 ppm (Reg. 41 and Reg. 42) with respect to the local (calibrated) oscillator clock. These registers can be subsequently set by external software, if required. After initialization, the output clocks are stable and the device will operate as a simple switch, with the DPLL trying to lock on to the selected reference source. (a) To lock to 2.000 MHz: (i) Set the cnfg_ref_source_frequency register to 10XX0000 (binary) to enable DivN, and set the frequency to 8 kHz - the frequency required after division. (XX = “Leaky Bucket” ID for this input). Output Clock Phase Continuity on Source Switchover A phase offset between SEC inputs will be seen as a phase shift on the output on source switchover equal to the input phase offset. Note...The ACS8526 has no Phase Build-out function to accommodate this. If this function is required, it is available on the AS8525 LC/P device. (ii) To achieve 8 kHz, the 2 MHz input must be divided by 250. So, if DivN = 250 = (N + 1) then N must be set to 249. This is done by writing F9 hex (249 decimal) to the DivN register pair Reg. 46/47. (b) To lock to 10.000 MHz: (i) The cnfg_ref_source_frequency register is set to 10XX0000 (binary) to set the DivN and the The rate of change of phase on the output, during the time between input switchover and the output settling to a steady state, is dependent on factors of: input frequency, www.semtech.com Revision 4.01/June 2006 © Semtech Corp. Page 8 ACS8526 LC/P LITE ADVANCED COMMUNICATIONS FINAL DATASHEET input phase change, DPLL bandwidth, DPLL frequency limit, and phase detector capture range. The ACS8526 always complies with GR-1244-CORE[13] spec for Stratum 3 (max rate of phase change of 81 ns/1.326 ms), for input frequencies at 6.48 MHz or higher, with the default 1UI phase detector capture range. For inputs at a lower frequency than 6.48 MHz (e.g. 8 kHz) with the DPLL frequency limit set to greater than ±30 ppm (note default is ±80 ppm), then to ensure compliance with GR-1244-CORE[13] at DPLL bandwidth settings of 18, 35 or 70 Hz, the input phase difference between the Master and Slave inputs to the line card PLL should be limited to less than 600, 330 ns or 190 ns respectively. Alternatively, the DPLL frequency range should be set