ACS8595T

Line Card Protection Switch for SONET/SDH AdvancedTCA Systems ADVANCED COMMUNICATIONS Description FINAL Features PRODUCT BRIEF ACS8595 ATCA The ACS8595 ATCA is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for line cards/blades in a SONET or SDH ATCA (Advanced Telecommuncications Computing Architecture) Network Element. The ACS8595 has fast activity monitors on the SEC clock inputs and will implement automatic system protection switching against the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clocks fail, the Stand-by “Group” is selected or, if no Stand-by is available, the device enters Digital Holdover mode. The ACS8595 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from the ATCA backplane into a range of spot frequencies from 2 kHz up to 311.04 MHz (up to 77.76 MHz on the TTL/CMOS ports). The output frequency is independently programmable on each of the six SEC output ports, so the ACS8595 ATCA has the potential to supply simultanously up to six different SEC frequencies, for example, to meet the individual requirements of several Advanced Mezzanine Cards (AMCs). The ACS8595 has one PECL/LVDS output port and five TTL/CMOS ports. It also provides an 8 kHz Frame Sync and a 2 kHz Multi-Frame Sync TTL/CMOS signal output with programmable pulse width and polarity. The ACS8595 includes a Serial Port, which can be SPI compatible, providing access to the configuration and status registers for device setup. Block Diagram Figure 1 Block Diagram of the ACS8595 ATCA 3 x SEC/Sync Input Groups SEC1 & SEC2: TTL/PECL/LVDS, SEC3 and all Syncs TTL only SEC1 Master SYNC1 SEC2 Slave SYNC2 SEC3 Stand-by SYNC3 SEC Inputs: Programmable Frequencies 2 kHz, 4 kHz, TCK N x 8 kHz TDI 1.544/2.048 MHz TMS 6.48 MHz TRST 19.44 MHz TDO 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz SONET/SDH applications up to OC-3/STM-1 bit rates Switches between grouped inputs (SEC/Sync pairs) Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz multiples up to 155.52 MHz), plus Frame Sync/MultiFrame Sync Outputs: Six SEC clocks at any of several spot frequencies from 2 kHz up to 77.76 MHz via the TTL/CMOS port and up to 311.04 MHz via the PECL/LVDS port Modes for E3/DS3 and multiple E1/DS1 rate output clocks Generates 8 kHz Frame Sync and 2 kHz Multi-Frame Sync output clocks with programmable pulse width and polarity Frequency translation of SEC input clock to different local line card clocks Robust activity monitoring on all clock inputs Supports Free-run, Locked and Digital Holdover modes of operation Automatic “Hit-less” source switchover on loss of input External force fast switch between SEC1/SEC2 inputs Phase Build-out for output clock phase continuity during input switchover PLL “Locked” and “Acquisition” bandwidths individually selectable from 18, 35 or 70 Hz Serial interface for device set-up IEEE 1149.1 JTAG Boundary Scan is supported. Single 3.3 V operation, 5 V I/O compatible Operating temperature (ambient) of -40 to +85°C Available in 100-pin LQFP package Lead (Pb)-free version (ACS8595T), RoHS and WEEE compliant SEC Outputs: O1 (PECL/LVDS) DPLL1 Input SEC Port Monitors and Input Selection Control DPLL2 MUX 2 APLL2 Output Port Frequency Selection MUX 1 APLL 1 O2 (TTL) O3 (TTL) O4 (TTL) O5 (TTL) O6 (TTL) Sync Outputs: MFrSync 2 kHz (TTL) FrSync 8 kHz (TTL) 01 TO O6: 8 kHz 1.544/2.048 MHz 3.088/4.096 MHz 6.176/8.192 MHz 12.352/16.384 MHz 6.48 MHz (not O1) 19.44 MHz 25.92 MHz 34.368 MHz 38.88 MHz 44.736 MHz 77.76 MHz 155.52 MHz (only O1) 311.04 MHz (only O1) F8595_001BlockDia_01 Selector Digital Feedback E1/DS1 Synthesis APLL3 IEEE 1149.1 JTAG Chip Clock Generator Priority Register Set Table Serial Interface Port TCXO or XO Revision 2.00/October 2005 © Semtech Corp. Page 1 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Pin Diagram Figure 2 ACS8595 Pin Diagram SONSDHB IC6 IC5 IC4 IC3 NC31 O6 O5 AGND4 VA3+ O2 O4 O3 DGND7 VDD7 VDD6 DGND6 SDO NC30 NC29 NC28 NC27 TDI TDO TCK FINAL Table 1 Power Pins (cont...) Pin No. 20, 92 11, 15, 14 49, 62, 84, 87 32, 38 Symbol AGND3, AGND4 DGND1, DGND2, DGND3 DGND4, DGND5, DGND6, DGND7 GND_DIFFa, GND_DIFFb P I/O Type - PRODUCT BRIEF Description Supply Ground: Analog ground for output PLLs APLL2 and APPL1. Supply Ground: Digital ground for components in PLLs. Supply Ground: Digital ground for logic. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P - 1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AGND1 NC1 IC1 NC2 AGND2 VA1+ NC3 INTREQ NC4 REFCLK DGND1 VD1+ VD3+ DGND3 DGND2 VD2+ NC5 SRCSW VA2+ AGND3 NC6 IC2 NC7 NC8 NC9 ACS8595 ATCA SONET/SDH LC/P 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC26 PORB SCLK VDD5 VDD4 CSB SDI CLKE TMS NC25 NC24 NC23 NC22 DGND5 VDD3 NC21 TRST VDD2 NC20 NC19 NC18 SYNC3 NC17 SEC3 SYNC2 P - Supply Ground: Digital ground for differential ports. Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Internally Connected and Not Connected Pins Pin No. Symbol I/O Type Description Internally Connected: Leave to float. 3, 22, IC1, IC2, 96, 97, IC3, IC4, 98, 99 IC5, IC6, 2,4, 7,9, 17, 21, 23,24, 25,26, 27,28, 29, 36, 37, 48, 53, 55, 56, 57, 60, 63, 64, 65, 66, 75, 79,80, 81, 82, 95 NC1, NC2, NC3,NC4, NC5,NC6, NC7, NC8, NC9, NC10, NC11, NC12, NC13,NC14, NC15, NC16, NC17, NC18, NC19, NC20, NC21, NC22, NC23, NC24, NC25, NC26, NC27, NC28, NC29, NC30, NC31 NC10 NC11 NC12 NC13 FrSync MFrSync GND_DIFFa VDD_DIFFa O1POS O1NEG NC14 NC15 GND_DIFFb VDD_DIFFb SEC1POS SEC1NEG SEC2POS SEC2NEG VDD5V SYNC1 SEC1 SEC2 NC16 DGND4 VDD1 - - Not Connected: Leave to float. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 F8595LPB_002PINDIAG_02 Pin Description Table 1 Power Pins Pin No. 12,16, 13, 33, 39 44 Symbol VD1+, VD2+, VD3+ VDD_DIFFa, VDD_DIFFb VDD5V I/O P P Type Description Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts ±10%. Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping. Input pins tolerant up to +5.5 Volts. Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. Table 3 Other Pins Pin No. 8 Symbol INTREQ I/O O Type TTL/CMOS Description Interrupt Request: Active High/Low software Interrupt output. Reference Clock: 12.800 MHz. Source Switching: Force Fast Source Switching on SEC1 and SEC2. Output Reference: 8 kHz Frame Sync output. Output Reference: 2 kHz Multi-Frame Sync output. P - 10 18 REFCLK SRCSW I I TTL TTLD 50, 58, 61, 71 72, 85, 86 6 VDD1, VDD2, VDD3, VDD4 VDD5, VDD6, VDD7 VA1+ P - P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%. Supply Voltage: Analog supply to output PLLs APLL2 and APPL1, +3.3 Volts ±10%. Supply Ground: Analog grounds. 30 FrSync O TTL/CMOS 19, 91 1, 5 VA2+, VA3+ AGND1, AGND2 P P - 31 MFrSync O TTL/CMOS 34, 35 O1POS, O1NEG O LVDS/PECL Output Reference: Programmable, default 38.88 MHz, LVDS. Revision 2.00/October 2005 © Semtech Corp. Page 2 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Table 3 Other Pins (cont...) Pin No. 40, 41 42, 43 45 Symbol SEC1_POS, SEC1_NEG SEC2_POS, SEC2_NEG SYNC1 I/O I Type Description FINAL Table 3 Other Pins (cont...) Pin No. 83 Symbol SDO I/O O Type TTLD PRODUCT BRIEF Description Interface Address: SPI compatible Serial Data Output. Output Reference: Programmable, disabled by default. Output Reference: Programmable, disabled by default. Output Reference: Programmable, default 19.44 MHz. Output Reference: Programmable, disabled by default. Output Reference: Programmable, disabled by default. SONET or SDH Frequency Select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. PECL/LVDS Input Reference: Programmable, default 19.44 MHz, PECL. PECL/LVDS Input Reference: Programmable, default 19.44 MHz PECL. TTLD (Master) Multi-Frame Sync 2 kHz Input: Connect to 2 or 8 kHz Multi-Frame Sync output of Master SETS. (Master) Input Reference: Programmable, default 8 kHz. I 88 O3 O TTL/CMOS I 89 O4 O TTL/CMOS 90 46 SEC1 I TTLD O2 O TTL/CMOS 93 47 SEC2 I TTLD (Slave) Input Reference: Programmable, default 8 kHz. 94 51 SYNC2 I TTLD (Slave) Multi-Frame Sync 2 kHz: Connect to 2 or 8 kHz Multi-Frame Sync output of Slave SETS. (Stand-by) Input Reference: External standby reference clock source, programmable, default 19.44 MHz. (Stand-by) Input Reference: External standby 2 or 8 kHz Multi-Frame Sync clock source. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 is Boundary Scan stand-by mode, still allowing normal device operation (JTAG logic transparent). NC if not used. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of SCLK to be active. Serial Interface Address: Serial Data Input. Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface. Serial Data Clock. When this pin goes High data is latched from SDI pin. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. O5 O TTL/CMOS O6 O TTL/CMOS 100 SONSDHB I TTLD 52 SEC3 I TTLD 54 SYNC3 I TTLD 59 TRST I TTLD Introduction The ACS8595 ATCA is a Line Card Protection device designed to complement the Semtech SETS devices which maintain the SETS functions in both SONET and SDH Network Elements. The ACS8595 ATCA extends this functionality on to the Line Card, for which it has been specifically designed. The ACS8595 ATCA uses “Hit-less” group switching between Master and Slave inputs or a third (Stand-by) input group, to generate and maintain accurate and stable SEC and frame synchronization pulse outputs for distribution on the Line Card, typically for Advanced Mezzaninie Cards (AMCs) on AdvancedTCA equipment. The ACS8595 provides a simple, compact, yet flexible solution, which can be easily tailored for use with a range of transmission formats and rates, via software configuration. The ACS8595 employs various mechanisms to maintain the integrity of its output clocks when its input clocks fail or fall below the required specification levels. By smoothing out the effects of these input anomalies, the ACS8595 improves the overall stability and reliability of www.semtech.com 67 TMS I TTLD 68 CLKE I TTLD 69 70 SDI CSB I I TTLD TTLU 73 SCLK I TTLD 74 PORB I TTLU 76 77 TCK TDO I O TTLD TTL/CMOS 78 TDI I TTLD Revision 2.00/October 2005 © Semtech Corp. Page 3 ACS8595 ATCA ADVANCED COMMUNICATIONS the downstream system synchronization, which translates to improved quality of service. The key architectural advantage that the ACS8595 has over traditional solutions is in the use of Digital Phase Locked Loop (DPLL) technology for precise and repeatable performance over temperature or voltage variations and between parts. Semtech can provide an Evaluation Board so that designers can rapidly appraise the ACS8595 ATCA device and see for themselves the benefits that a Semtech ATCA solution can bring to their designs. FINAL PRODUCT BRIEF Input frequencies supported range from 2, 4, 8 kHz (and n x 8 kHz) up to 155.52 MHz. Common E1, DS1, OC-3/STM-1 and sub-divisions are supported as spot frequencies to which the DPLLs will directly lock. Any input frequency, up to 100 MHz, that is a multiple of 8 kHz can also be locked to via a built-in programmable divider. Refer to Table 4 for details of each input port. Input Locking Frequency Modes Each input port has to be configured to receive the expected input frequency. To achieve this, three Input Locking Frequency Modes are provided: Direct Lock, Lock8K and DivN. General Description Inputs The ACS8595 SETS device has input ports for clock groups from three sources, typically Master, Slave and Stand-by, where each clock group comprises one SEC and optionally one Sync signal. This means that when any SEC input changeover is made, the corresponding Sync signal changeover is also made. Master and Slave SEC inputs to the device support TTL/CMOS and PECL/LVDS. The Stand-by SEC and three Sync inputs are TTL/CMOS only. All the TTL/CMOS ports are 3 V and 5 V compatible (with clamping if required by connecting the VDD5V pin). SEC Activity Monitors A monitoring function constantly appraises the activity of each input SEC, and reports anomalous behavior. Each of the input monitors is individually configurable, allowing flags or interrupts to be raised which can influence both the operating state of the device, and which inputs are available for selection by the PLL circuitry. Any Input SEC which suffers a loss-of-activity will be declared as unavailable. Anomalies detected by the Activity Monitor are integrated in a Leaky Bucket Accumulator. Occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. Table 4 Input Reference Source Selection and Priority Table Port Name SEC1 TTL SEC2 TTL SEC1 DIFF SEC2 DIFF SYNC1 SYNC2 SEC3 SYNC3 Channel Number 0011 0100 0101 0110 0111 1000 1001 1010 Input Port Technology TTL/CMOS TTL/CMOS PECL/LVDS PECL default PECL/LVDS PECL default TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS Frequencies Supported Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 2/4/8 kHz auto-sensing 2/4/8 kHz auto-sensing Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 2/4/8 kHz auto-sensing Default Priority 2 3 0 0 n/a n/a 4 n/a Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 bit 2, ip_sonsdhb). (ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for Output O1 only). (iii) SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly SEC2DIFF uses pins SEC2POS and SEC2NEG. Revision 2.00/October 2005 © Semtech Corp. Page 4 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS FINAL PRODUCT BRIEF Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected SEC (and Sync) being rejected. There is one Leaky Bucket Accumulator per SEC input. Each Leaky Bucket Accumulator can be programmed with a Bucket ID (0 to 3) which assigns to the Leaky Bucket the corresponding Leaky Bucket Configuration (from four available Configurations). Each Leaky Bucket Configuration comprises the following programmable parameters: Bucket size Alarm trigger (set threshold) Alarm clear (reset threshold) Leak rate (decay rate the Register Descriptions in the datasheet for advanced features and more information. DPLL1 Main Features Phase Locked Loops (PLLs) Figure 1 shows the PLL circuitry which comprises two Digital PLLs (DPLL1 and DPLL2), two output multiplying and filtering Analog PLLs (APLL1 and APLL2), output frequency dividers in an Output Port Frequency Selection block, a Synthesis block, multiplexers MUX1 and MUX2, and a feedback Analog PLL (APLL3). These functional blocks and their interconnections are highly configurable, via register control, providing a range of output frequencies and a choice of levels of jitter performance. The DPLLs give a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating range. They are not affected by operating conditions or silicon process variations. Digital Synthesis is used to generate all required SONET/SDH output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.800 MHz oscillator module. Hence the best resolution of the output signals from the DPLLs is one 204.8 MHz cycle or 4.9 ns. Both of the DPLLs’ outputs can be connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number of frequencies simultaneously available for selection at the output clock ports. The various combinations of DPLL, APLL, Multiplexer and divider configurations allow for generation of a comprehensive set of frequencies, as listed in Table 5 and Table 6. Multiple E1 and DS1 outputs supported Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs Multiple phase loss and multiple phase detectors Direct PLL locking to common SONET/SDH input frequencies or any multiple of 8 kHz Automatic mode switching between Free-run, Locked and Digital Holdover modes (states) Fast detection on input failure and entry into Digital Holdover mode (holds at the last good frequency value) Frequency translation between input and output rates via direct digital synthesis High accuracy digital architecture for stable PLL dynamics combined with an APLL for low jitter final output clocks Non-revertive mode Frame Sync pulse alignment Selectable automatic DPLL bandwidth control (auto selects either Locked bandwidth, or Acquisition bandwidth), or Locked DPLL bandwidth Two programmable bandwidth controls: • Locked bandwidth: 18, 35 or 70 Hz • Acquisition bandwidth: 18, 35 or 70 Hz Programmable damping factor, (For optional faster locking and peaking control) Factors = 1.2, 2.5, 5, 10 or 20 Programmable DPLL pull-in frequency range Phase Build-out on source switching (hit-less source switching), on/off Freeze Phase Build-out, on/off DPLL2 Main Features The main features of DPLL2 are: Always locked to DPLL1 Single programmable bandwidth control: 18, 35 or 70 Hz Programmable damping factor, (For optional faster locking and peaking control) Factors = 1.2, 2.5, 5, 10 or 20. Digital feedback, on/off Output frequency selection www.semtech.com DPLLs DPLL1 is the more feature rich of the two DPLLs. The main features of the two DPLLs are summarized here. Refer to Revision 2.00/October 2005 © Semtech Corp. Page 5 ACS8595 ATCA ADVANCED COMMUNICATIONS FINAL PRODUCT BRIEF DS3/E3 support (44.736 MHz / 34.368 MHz) independent of rates from DPLL1 • Low jitter E1/DS1 options independent of rates from DPLL1 • Frequencies of n x E1/DS1 including 16 and 12 x E1, and 16 and 24 x DS1 supported • Squelched (clock off) Can provide the source for the 2 kHz and 8 kHz outputs available at Outputs 01 to 06 Can use its phase detector to measure the input phase difference between two inputs Selectable digital feedback, on/off Either the software or an internal state machine controls the operation of DPLL1. The state machine for DPLL2 is very simple and cannot be manually/externally controlled. One additional feature of DPLL2 is the ability to measure a phase difference between two inputs. DPLL1 always produces an output at 77.76 MHz to feed the APLL, regardless of the frequency selected at the output pins or the locking frequency (frequency at the input of the Phase and Frequency Detector — PFD). DPLL2 can be operated at a number of frequencies. This is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz. If DPLL2 is enabled, it locks to the 8 kHz from DPLL1. This is because all of the frequencies of operation of DPLL2 can be divided to 8 kHz and this will ensure synchronization of frequencies, from 8 kHz upwards, within the two DPLLs. individually selectable. Output 01 is a differential port (pins O1POS and O1NEG), and can be selected PECL or LVDS. All other outputs are TTL/CMOS. Table 5 Output Port Frequencies and Technologies Port Name O1 O2, O3, O4, O5 and O6 FrSync MFrSync Output Port Technology LVDS/PECL (LVDS default) TTL/CMOS TTL/CMOS TTL/CMOS FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7C. MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7C. Frequencies Supported Frequencies as per Table 6 Table 6 Output Frequencies/Lowest Jitter Configuration (Typical Conditions) Frequency (MHz) 2 kHz 8 kHz 1.536 1.544 2.048 2.0586667 2.316 2.7306667 2.796 3.088 3.728 4.096 4.296 4.86 5.728 6.144 6.176 6.48 8.192 8.2346667 9.264 10.922667 11.184 12.288 12.352 16.384 16.46933 17.184 18.528 19.44 21.84533 22.368 24.576 24.704 25.92 32.768 34.368 37.056 via Digital1 or Digital2 (not O1) (not O5/O6) (not O5/O6) (not O5/O6) (not O5/O6) (not O5/O6) (not O5/O6) Jitter Level (typ) rms (ps) 60 60 250 150 220 150 110 220 110 110 110 3800 120 60 120 250 150 60 220 760 110 250 110 250 110 220 760 120 110 60 250 110 250 110 60 220 120 110 p-p (ns) 0.6 0.6 1.5 1.0 1.2 1.0 0.75 1.2 1.0 0.75 1.0 13 1.0 0.6 1.0 1.5 1.0 0.6 1.2 2.6 0.75 1.6 1.0 1.5 0.75 1.2 2.6 1.0 0.75 0.6 1.6 1.0 1.5 0.75 0.6 1.2 1.0 0.75 APLLs There are three APLLs. APLL1 and APLL2 provide a lower final output jitter reducing the 4.9 ns p-p jitter from the digital down to 500 ps p-p and 60 ps rms as typical final outputs measured broadband (from 10 Hz to 1 GHz). The feedback APLL (APLL3) is selected by default; it provides improved performance over the digital feedback. Each APLL has its own divider. Each divider simultaneously outputs a series of fixed ratios of its APLL input. These divided outputs are available on Output Ports O1 to O6. Outputs The ACS8595 delivers eight output signals on the following ports: Six clocks, one each on ports O1 to O6; and two Sync signals, on ports FrSync and MFrSync. Outputs O1 to O6 are independent of each other and are Revision 2.00/October 2005 © Semtech Corp. Page 6 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS FINAL Jitter Level (typ) rms (ps) 60 110 (O5/O6 only) (O1 only) (O5/O6 only) (O1 only) (O5/O6 only) (O1 only) (O5/O6 only) (O1 only) (O5/O6 only) (O1 only) (O1 only) (O1 only) (O1 only) (O5/O6 only) (O1 only) (O1 only) 250 900 150 760 60 220 120 120 110 110 60 110 900 900 760 250 120 110 60 60 p-p (ns) 0.6 1.0 1.5 4.5 1.0 2.6 0.6 1.2 1.0 1.0 0.75 0.75 0.6 1.0 4.5 4.5 2.6 1.6 1.0 0.75 0.6 0.6 PRODUCT BRIEF Table 6 Output Frequencies/Lowest Jitter Configuration (Typical Conditions) (cont...) Frequency (MHz) 38.88 44.736 49.152 49.152 49.408 49.408 51.84 65.536 65.536 68.736 74.112 74.112 77.76 89.472 98.304 98.304 98.816 131.072 137.472 148.224 155.52 311.04 replacement source is available. Digital Holdover operates instantaneously, which means the DPLL freezes at the frequency it was operating at the time of entering Digital Holdover mode. Input Selection Priorities Each input SEC can be programmed with a priority number (see Table 4) allowing references to be chosen according to the highest priority valid input. Under normal operation, the input SECs are selected automatically, according to availability and in order of priority. For special circumstances, such as chip or board testing, the selection may be forced by configuration. The priority table is initially defined by the default configuration and can be changed via the Serial interface by the Network Manager. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Table 4 gives details of the input reference ports. Specific frequencies and priorities are set by configuration. Modes of Operation The device has three principle modes of operation: Free-run Locked Digital Holdover The Free-run mode is typically used following a power-onreset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8595 are based on the 12.800 MHz clock frequency provided from the external oscillator and are not synchronized to an input SEC. The accuracy can be enhanced via software calibration to within ±0.0196229 ppm. The Locked mode is used when an input SEC has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and is locked to the selected input SEC. The priority table determines which input SEC is selected. When the ACS8595 is in Locked mode, the output frequency and phase follows that of the selected input SEC. In Digital Holdover mode, the ACS8595 provides the timing signals to maintain the Line Card when its currently selected input source becomes invalid, and no other valid Revision 2.00/October 2005 © Semtech Corp. Ultra Fast Switching SEC inputs are monitored using a leaky bucket approach to allow source qualification criterion to be monitored. A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented so that a loss of activity of just a few reference clock cycles will raise an alarm and cause a reference switch. External Forced Fast Protection Switching External Forced Fast Protection Switching mode, for fast switching between inputs SEC1 or SEC2, can be triggered directly from the dedicated pin SRCSW. Restoration Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. For this, the ACS8595 has two modes of operation; Revertive and Non-revertive. Sync Reference Sources The ACS8595 provides the facility to have a Sync reference source associated with each SEC. www.semtech.com Page 7 ACS8595 ATCA ADVANCED COMMUNICATIONS FINAL PRODUCT BRIEF The Sync inputs (SYNC1, SYNC2 and SYNC3) are used for Frame Sync output alignment and can be 2, 4 or 8 kHz (automatically detected frequency). As in all the Semtech ACS85xx series of parts supporting such a mechanism, the Sync is treated as an additional part of the SEC clock. The failure of a Sync input will never cause a source disqualification. The Sync input is used to internally align the generation of the output 2 kHz and 8 kHz Sync pulses. Performance Benefits from DPLL/APLL Technology The use of Digital Phase Locked Loop technology ensures precise and repeatable performance over temperature or voltage variations, and between parts. The overall PLL bandwidth, loop damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. An Analog PLL takes the signal from the DPLL output and provides a lower jitter output. The APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. The DPLLs are clocked by the external oscillator module therefore the Free-run or Digital Holdover frequency stability is only determined by the stability of the external oscillator module. This key advantage confines all temperature critical components to one well defined and pre-calibrated module, whose performance can be chosen to match the application. All performance parameters of the DPLLs are programmable without the need to understand detailed PLL equations. Bandwidth, damping factor and lock range, for example, can all be set directly. A high level of phase and frequency accuracy is made possible in the ACS8595 by an internal resolution of up to 54 bits and internal Holdover accuracy of up to 7.5 x 10-14 ppb (instantaneous). Serial Interface The ACS8595 device has an SPI compatible serial interface, providing access to the configuration and status registers for device set-up and monitoring. Performance Conformance The ACS8595 is designed for use in Line Cards in Network Elements which must meet the requirements of the following specifications: ITU: G. 736, G.742, G.812, G.813, G.824, K.41. Telcordia: GR-253-CORE, GR-499-CORE, GR-1244-CORE. ANSI: T1.101-1999. ETSI: ETSI 300 462-3, ETSI 300 462-5. Typical Application Figure 3 Semtech’s Product Family Solution for a Typical SONET/SDH Architecture Multiple Line cards Line Card (0C-12, OC-48) Recovered Clock Master Clock Master Sync Slave Clock Slave Sync Stand-by Clock Stand-by Sync ACS8515 ACS8525 ACS8526 ACS8527 ACS8595 ATCA Frame Sync Multi Frame Sync E1/DS1 Clock Distribution FRAMER SERDES LINE CARD PROTECTION ACS8942A JAM PLL To/from SONET/SDH/PDH Network Low Jitter/Low Skew Low Jitter up to 622 MHz Backplane Slave Sync Card Master Sync Card Input CLK Sources Config. Priorities mP/Serial Bus SSM Primary Ref. Input/ output CLK Line I/F Unit DATA DATA SEC Priorities TCLK SSM Handling Function SETS ACS8510 ACS8520 ACS8522 ACS8530 Output CLKs Clock Distribution SetsLinecardGenApp_08 Revision 2.00/October 2005 © Semtech Corp. Page 8 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Register Map Table 7 Register Map RO = Read Only R/W = Read/Write chip_id (RO) chip_revision (RO) test_register1 (R/W) test_register2 (R/W) sts_interrupts (R/W) Address (hex) Default (hex) Register Name Data Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) FINAL PRODUCT BRIEF 00 01 02 03 04 05 06 4D 21 00 14 12 FF 3F 00 10 01 00 00 00 00 00 00 No Activity SEC2 TTL No Activity SEC2 DIFF SEC2 DIFF Sync_alarm_ int Sync_alarm DPLL2_Lock DPLL1_freq_ soft_alarm operating_ mode DPLL1_main_ ref_failed status_SEC2_ DIFF Phase_alarm Disable_180 chip_id[7:0], 8 LSBs of Chip ID chip_id[15:8], 8 MSBs of Chip ID chip_revision[7:0] Resync_ analog status_SEC1_ DIFF Set to 0 Do not use status_SEC2_ TTL status_SEC1_ TTL status_SEC3 Bits [18:16] of sts_current_DPLL_frequency 8K Edge Polarity Set to 0 Set to 0 sts_current_DPLL_frequency, see OC/OD sts_interrupts (R/W) sts_operating_mode (RO) sts_priority_table (RO) 07 08 09 0A 0B DPLL2_freq_ soft_alarm DPLL1_operating_mode Currently selected source 2nd highest priority validated source Highest priority validated source 3rd highest priority validated source Bits [7:0] of sts_current_DPLL_frequency sts_current_DPLL_frequency [7:0] 0C (RO) sts_sources_valid (RO) [18:16] 07 0E 0F sts_reference_sources (RO) Alarm Status on inputs: SEC1 & SEC2 TTL 11 SEC1 & SEC2 DIFF 12 SEC3 14 cnfg_ref_selection_priority (R/W) 19 SEC1 & SEC2 TTL SEC1 & SEC2 DIFF 1A SEC3 1C cnfg_ref_source_frequency_ (R/W), where = SEC1 TTL 22 SEC2 TTL 23 SEC1 DIFF 24 SEC2 DIFF 25 SEC3 28 cnfg_operating_mode (R/W) force_select_reference_source (R/W) cnfg_input_mode (R/W) cnfg_DPLL2_path (R/W) cnfg_differential_inputs (R/W) cnfg_dig_outputs_sonsdh (R/W) cnfg_digtial_frequencies (R/W) cnfg_differential_output (R/W) cnfg_auto_bw_sel 32 33 34 35 36 38 39 3A 3B [15:8] 0D 00 Bits [15:8] of sts_current_DPLL_frequencyy Bits [18:16] of sts_current_DPLL_frequency SEC1 DIFF SEC2 TTL SEC1 TTL SEC3 Phase Lock SEC2 TTL Phase Lock SEC2 DIFF No Activity SEC1 TTL No Activity SEC1 DIFF No Activity SEC3 programmed_priority_SEC2_TTL programmed_priority_SEC2_DIFF programmed_priority_SEC1_TTL programmed_priority_SEC1_DIFF programmed_priority_SEC3 Phase Lock SEC1 TTL Phase Lock SEC1 DIFF Phase Lock SEC3 22 22 22 32 00 04 00 00 03 03 03 00 0F CA A0 03 04 08 C2 98 divn_SEC1 TTL lock8k_SEC1 TTL divn_SEC2 TTL lock8k_SEC2 TTL divn_SEC1 DIFF divn_SEC2 DIFF divn_SEC3 lock8k_SEC1 DIFF lock8k_SEC2 DIFF lock8k_SEC3 Bucket_id_SEC1 TTL Bucket_id_SEC2 TTL Bucket_id_SEC1 DIFF Bucket_id_SEC2 DIFF Bucket_id_SEC3 reference_source_frequency_SEC1 TTL reference_source_frequency_SEC2 TTL reference_source_frequency_SEC1 DIFF reference_source_frequency_SEC2 DIFF reference_source_frequency_SEC3 DPLL1_operating_mode forced_select_SEC_input auto_extsync_ en phalarm_ timeout DPLL2_dig_ feedback XO_ edge extsync_en ip_sonsdhb reversion_ mode SEC2_DIFF_ PECL dig2_sonsdh digital2_frequency auto_BW_sel dig1_sonsdh digital1_frequency SEC1_DIFF_ PECL Output O1 _LVDS_PECL DPLL1_lim_int Revision 2.00/October 2005 © Semtech Corp. Page 9 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Table 7 Register Map (cont...) RO = Read Only R/W = Read/Write cnfg_nominal_frequency (R/W) Address (hex) Default (hex) Register Name Data Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) FINAL PRODUCT BRIEF [7:0] 3C 99 76 00 00 00 00 FF 3F 04 00 freq_lim_ph_ loss 06 04 08 01 los_flag_on_ TDO ultra_fast_ switch Set to 0 operating_ mode Sync_ip_alarm Set to 0 main_ref_ failed SEC2 DIFF Bits[7:0] of cnfg_nominal_frequency Bits[15:8] of cnfg_nominal_frequency Bits[7:0] of cnfg_DPLL_freq_limit Bits[9:8] of cnfg_DPLL_freq_limit SEC1 DIFF SEC2 TTL SEC1 TTL Set to 0 SEC3 [15:8] 3D 99 cnfg_DPLL_freq_limit (R/W) [7:0] 41 cnfg_DPLL_freq_limit (R/W) [9:8] 42 cnfg_interrupt_mask (R/W) [7:0] 43 [15:8] 44 [23:16] 45 cnfg_freq_divn (R/W) cnfg_monitors (R/W) cnfg_registers_source_select (R/W) cnfg_freq_lim_ph_loss cnfg_upper_threshold_0 (R/W) cnfg_lower_threshold_0 (R/W) cnfg_bucket_size_0 (R/W) cnfg_decay_rate_0 (R/W) [7:0]. 46 [13:8] 47 48 4B 4D 50 51 52 53 divn_value [7:0] (divide Input frequency by n) divn_value [13:8] (divide Input frequency by n) ext_switch DPLL1_DPLL2 _select PBO_freeze PBO_en upper_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - set threshold) lower_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - reset threshold) Bucket_size_0_value (Activity alarm, Config. 0, Leaky Bucket - size) decay_rate_0_value (Activity alarm, Config. 0, Leaky Bucket leak rate) upper_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - set threshold) lower_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - reset threshold) Bucket_size_1_value (Activity alarm, Config. 1, Leaky Bucket - size) decay_rate_1_value (Activity alarm, Config. 1, Leaky Bucket leak rate) upper_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - set threshold) lower_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - reset threshold) Bucket_size_2_value (Activity alarm, Config. 2, Leaky Bucket - size) decay_rate_2_value (Activity alarm, Config. 2, Leaky Bucket leak rate) upper_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - set threshold) lower_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - reset threshold) Bucket_size_3_value (Activity alarm, Config. 3, Leaky Bucket - size) decay_rate_3_value (Activity alarm, Config. 3, Leaky Bucket leak rate) output_freq_O4 output_freq_O5 output_freq_O1 MFrSync_en DPLL2_meas_ DPLL1_ph FrSync_en DPLL2_frequency APLL2_for_ DPLL1_E1/DS 1 DPLL1_freq_to_APLL2 DPLL1_frequency output_freq_O3 output_freq_O2 output_freq_O6 cnfg_upper_threshold_1 (R/W) cnfg_lower_threshold_1 (R/W) cnfg_bucket_size_1 (R/W) cnfg_decay_rate_1 (R/W) 54 55 56 57 06 04 08 01 cnfg_upper_threshold_2 (R/W) cnfg_lower_threshold_2 (R/W) cnfg_bucket_size_2 (R/W) cnfg_decay_rate_2 (R/W) 58 59 5A 5B 06 04 08 01 cnfg_upper_threshold_3 (R/W) cnfg_lower_threshold_3 (R/W) cnfg_bucket_size_3 (R/W) cnfg_decay_rate_3 (R/W) 5C 5E 5F 06 08 01 5D 04 cnfg_output_frequency (R/W) 60 Outputs O4 & 03 OutputsO5 & O2 61 OutputsO1 & 06 62 (MFrSync/FrSync) 63 cnfg_DPLL2_frequency (R/W) cnfg_DPLL1_frequency (R/W) 64 65 00 06 80 C0 00 01 cnfg_DPLL2_bw (R/W) cnfg_DPLL1_locked_bw (R/W) cnfg_DPLL1_acq_bw (R/W) cnfg_DPLL2_damping (R/W) cnfg_DPLL1_damping (R/W) cnfg_DPLL2_PD2_gain (R/W) cnfg_DPLL1_PD2_gain (R/W) 66 67 69 6A 6B 6C 00 10 11 13 13 C2 DPLL2_PD2_ gain_enable DPLL1_PD2_ gain_enable DPLL2_PD2_gain_alog_8k DPLL1_PD2_gain_alog_8k DPLL2_PD2_gain_alog DPLL1_PD2_gain_alog DPLL2_bandwidth DPLL1_locked_bandwidth DPLL1_acquisition_bandwidth DPLL2_damping DPLL1_damping DPLL2_PD2_gain_digital DPLL1_PD2_gain_digital 6D C2 Revision 2.00/October 2005 © Semtech Corp. Page 10 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Table 7 Register Map (cont...) RO = Read Only R/W = Read/Write cnfg_phase_offset (R/W) Address (hex) Default (hex) Register Name Data Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) FINAL PRODUCT BRIEF [7:0] 70 [15:8] 71 72 74 76 00 00 00 A2 85 06 00 00 32 00 00 2B 2k_8k_from_ DPLL2 Indep_FrSync/ MFrSync ph_offset_ ramp Sync_OC-N_ rates fine_limit_en coarse_lim_ phaseloss_en ip_noise_ window_en noact_ph_loss wide_range_ en narrow_en multi_ph_resp phase_offset_value [7:0] phase_offset_value[15:8] PBO_phase_offset phase_loss_fine_limit phase_loss_coarse_limit cnfg_PBO_phase_offset (R/W) cnfg_phase_loss_coarse_limit (R/W) cnfg_ip_noise_window (R/W) sts_current_phase (RO) cnfg_phase_alarm_timeout (R/W) cnfg_sync_pulses (R/W) cnfg_sync_phase (R/W) cnfg_sync_monitor (R/W) cnfg_interrupt (R/W) cnfg_protection(R/W) cnfg_phase_loss_fine_limit (R/W) 73 [7:0] 77 [15:8] 78 79 7A 7B 7C current_phase[7:0] current_phase[15:8] timeout_value (in two-second intervals) 8k_invert Sync_phase_SYNC3 Sync_monitor_limit Interrupt GPO_en protection_value Interrupt tristate_en Interrupt int_polarity 8k_pulse 2k_invert 2k_pulse Sync_phase_SYNC2 Sync_phase_SYNC1 7D 02 7E 85 Revision 2.00/October 2005 © Semtech Corp. Page 11 www.semtech.com ACS8595 ATCA ADVANCED COMMUNICATIONS Ordering Information Table 8 Parts List Part Number ACS8595 ACS8595T ACS8595 EVB Description ATCA Line Card Protection Switch for SONET/SDH AdvancedTCA Systems Lead (Pb)-free package version of ACS8595; RoHs and WEEE compliant Evaluation Board and Software FINAL PRODUCT BRIEF Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 acsupport@semtech.com FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 ISO9001 CERTIFIED Revision 2.00/October 2005 © Semtech Corp. Page 12 www.semtech.com