ACS8947T

ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path ADVANCED COMMS & SENSING COMMUNICATIONS Introduction FINAL Features DATASHEET The ACS8947T JAM PLL is a general pupose, Integer N, jitter-attenuating, differential phase-locked loop for generating low jitter output clocks. Frequency translation, reference switching between clock inputs and resynchronization features are provided also. Typical application areas include Ethernet, SONET/SDH, PCI, 3G and wireless systems. Typical output jitter generation in a SONET/SDH OC-12 system is 2.8 ps RMS, making the ACS8947T an ideal dejittering solution for use with Semtech clock and line card parts ACS8510, ACS8520, ACS8525, ACS8522, ACS8530 and ACS9510. The ACS8947T has two differential frequencyprogrammable LVPECL reference inputs and one differential synchronization input. The device is capable of locking across a wide input frequency range of 580 kHz to 180 MHz. Four independently-supplied differential outputs are available, programmable as LVPECL or CML. Each output supports a maximum output frequency rate of up to 625 MHz. All device settings are fully hardwire configured. An external microprocessor is not required to program the PLL. Highly configurable high performance Integer N PLL with integrated VCO. VCO frequency range 2.35 GHz to 2.9 GHz. Configurable closed loop bandwidth from 2 kHz upwards. PLL fully configured by hardwired configuration matrix: no requirement for an external microprocessor. Full control over internal dividers allows the device to be configured for a wide range of frequency translation and jitter cleaning applications. Meets RMS jitter requirements for OC3 and OC12 telecommunications systems. Wide input frequency range of 580 kHz to 180 MHz. Wide output frequency range of 1.23 MHz to 625 MHz. Input activity monitors and lock detector. Automatic or manual control of reference selection. External feedback option. Wide tracking range of 200 ppm. Powerful evaluation board and GUI tool for configuration and device assessment. 3.3 V operation: temperature range - 40°C to +85°C. Small outline, leadless, 7 mm x 7 mm QFN48 package. Block Diagram Figure 1 Simplified Block Diagram of the ACS8947T JAM PLL Revision 1.00/September 2007© Semtech Corp. Page 1 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Table of Contents FINAL DATASHEET Section Page Introduction ................................................................................................................................................................................................1 Block Diagram............................................................................................................................................................................................ 1 Features .....................................................................................................................................................................................................1 Pin Diagram ...............................................................................................................................................................................................3 Pin Descriptions .........................................................................................................................................................................................4 Description .................................................................................................................................................................................................8 Inputs .................................................................................................................................................................................................9 Clock Inputs ..............................................................................................................................................................................9 External feedback ................................................................................................................................................................. 10 Source Switching ................................................................................................................................................................... 10 Activity Alarms ....................................................................................................................................................................... 10 SYNC Input ............................................................................................................................................................................. 10 Input Divider DIVIP ................................................................................................................................................................. 10 Feedback Divider DIVFB ........................................................................................................................................................ 10 Odd Divider DIVODD ............................................................................................................................................................... 10 Phase and Frequency Detector ............................................................................................................................................. 11 Charge Pumps and External Low-Pass Filter........................................................................................................................ 11 Voltage Controlled Oscillator ................................................................................................................................................ 11 Output Multiplexer and Divider ............................................................................................................................................ 11 Outputs ........................................................................................................................................................................................... 11 Lock Detector ................................................................................................................................................................................. 12 Jitter Filtering .................................................................................................................................................................................. 12 Input Jitter Tolerance ..................................................................................................................................................................... 12 Jitter Transfer ................................................................................................................................................................................. 12 Phase Noise Performance ............................................................................................................................................................. 13 PLL Configuration ........................................................................................................................................................................... 13 Output Jitter .................................................................................................................................................................................... 14 Device Reset .................................................................................................................................................................................. 14 Layout Recommendations ............................................................................................................................................................ 14 Example Schematic ....................................................................................................................................................................... 15 Electrical Specifications ......................................................................................................................................................................... 16 Maximum Ratings .......................................................................................................................................................................... 16 Operating Conditions ..................................................................................................................................................................... 17 AC Characteristics ................................................................................................................................................................. 18 DC Characteristics ................................................................................................................................................................. 19 Input and Output Interface Terminations ..................................................................................................................................... 20 Jitter Performance ......................................................................................................................................................................... 23 Input/Output Timing ...................................................................................................................................................................... 25 Package Information .............................................................................................................................................................................. 26 Thermal Conditions ........................................................................................................................................................................ 27 References and Related Standards ...................................................................................................................................................... 28 Abbreviations .......................................................................................................................................................................................... 28 Trademark Acknowledgements ............................................................................................................................................................. 29 Revision Status/History ......................................................................................................................................................................... 29 Ordering Information .............................................................................................................................................................................. 30 Contact Information ................................................................................................................................................................................ 30 Revision 1.00/September 2007© Semtech Corp. Page 2 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Pin Diagram Figure 2 ACS8947T Pin Diagram FINAL DATASHEET Revision 1.00/September 2007© Semtech Corp. Page 3 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Pin Descriptions I = input O = output I/O = bi-directional P = power A = analog Table 1 Power pins Pin No. 1, 4, 7, 10 26 29 43 34 38 39 49 Symbol VDDO1, VDDO2, VDDO3, VDDO4 VDDADIV VDDP1 VDDP2 VDDARF VDDOSC VSSOSC VSS0 I/O P Type Description Independent voltage supplies to power each clock output (differential pair of pins) OUT1N/P to OUT4N/P respectively. +3.3 V (±5%). To disable an output and save power, tie associated VDD to 0V. Supply voltage for internal dividers in VCO loop, kept as an isolated supply to allow for low supply noise for the output divider stages. +3.3 V (±5%). Supply voltage to differential inputs, alarm and configuration pins. +3.3 V (±5%). Supply voltage to SYNC input and output pins, rate selection pins, input selection pins and reset pin. +3.3 V (±5%). Supply voltage for phase and frequency detector (PFD), kept as an isolated supply to allow for low supply noise. +3.3 V (±5%). Supply voltage to the internal VCO. +3.3 V (+5%/-10%). Supply ground 0 V for the internal VCO. Common supply ground 0 V. This is the central leadframe pad on the underside of the package. FINAL In the Type column: DATASHEET In the I/O column of the pin description tables that follow: LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull down resistor P P P P P P P - Table 2 Internally connected pins Pin No. 37 IC1 Symbol I/O Type Connect to ground. Description Table 3 Functional Pins Pin No. 2 Symbol OUT1N I/O O Type CML or LVPECL Description One of four CML or LVPECL differential outputs, partnered with pin 3. Programmable at spot frequencies from 1.23 MHz to 625 MHz. The output frequency is defined by the configuration pin settings at power up or when RESETB is asserted (logic 0). See PLL Configuration. The output is ON when VDD01 is supplied with 3.3 V, or OFF when VDD01 is tied to zero volts. If VDD01 is connected to 0 V, remove the external biasing resistors. CML or LVPECL differential output partnered with pin 2. See pin 2 description for more detail. 3 OUT1P O CML or LVPECL Revision 1.00/September 2007© Semtech Corp. Page 4 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Table 3 Functional Pins (cont...) Pin No. 5 Symbol OUT2N I/O O Type CML or LVPECL Description One of four CML or LVPECL differential outputs, partnered with pin 6. Programmable at spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the configuration pin settings at power up or when RESETB is asserted (logic 0). See PLL Configuration. The output is ON when VDD02 is supplied with 3.3 V, or OFF when VDD02 is tied to zero volts. If VDD02 is connected to 0 V, remove the external biasing resistors. CML or LVPECL differential output partnered with pin 5. See OUT2_N (pin 5) for more detail. One of four CML or LVPECL differential outputs, partnered with pin 9. Programmable at spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the configuration pin settings at power up or when RESETB is asserted (logic 0). See PLL Configuration. The output is ON when VDD03 is supplied with 3.3 V, or OFF when VDD03 is tied to zero volts. If VDD03 is connected to 0 V, remove the external biasing resistors. CML or LVPECL differential output partnered with pin 8. See pin 8 description for more detail. One of four CML or LVPECL differential outputs, partnered with pin 12. Programmable at spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the configuration pin settings at power up or when RESETB is asserted (logic 0). See PLL Configuration. The output is ON when VDD04 is supplied with 3.3 V, or OFF when VDD04 is tied to zero volts. If VDD04 is connected to 0 V, remove the external biasing resistors. CML or LVPECL differential output partnered with pin 11. See pin 11 description for more detail. Activity alarm output for the CLK1P/CLK1N input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up, where it is used as a configuration output pin, that may be connected to CFG_IN[11:0] input pins as required. See PLL Configuration. Activity alarm output for the CLK2P/CLK2N input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up time, where it is used as a configuration output pin, that may be connected to CFG_IN[11:0] input pins as required. See PLL Configuration. Configuration pin, used in the configuration on power-up of expected input clock frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[11:0] pins as required. See PLL Configuration. Activity alarm output for the currently selected input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up, where it is used as a configuration output pin that may be connected to CFG_IN[11:0] input pins as required. See PLL Configuration. Lock detect output. This is a pulse-width modulated output current, with each pulse typically +10 μA. The output produces a pulse with a width in proportion to the phase error seen at the internal phase detector. This pin should be connected via an external parallel capacitor and resistor to ground. The pin voltage will then give an indication of phase lock: When low, the device is phase locked; when high the device has frequent large phase errors and so is not phase locked. The value of the RC components used determines the time and level of consistency required for lock indication. If LOCKB is disabled by configuration the LOCKB output is held low. FINAL DATASHEET 6 8 OUT2P OUT3N O O CML or LVPECL CML or LVPECL 9 11 OUT3P OUT4N O O CML or LVPECL CML or LVPECL 12 13 OUT4P ALARM1_CO0 O O CML or LVPECL LVTTL/ LVCMOS 14 ALARM2_CO1 O LVTTL/ LVCMOS 15 CFG_OUT2 O LVTTL/ LVCMOS LVTTL/ LVCMOS 16 ALARMC_CO3 O 17 LOCKB O Analog Revision 1.00/September 2007© Semtech Corp. Page 5 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Table 3 Functional Pins (cont...) Pin No. 18 19 20 Symbol CFG_IN0 CFG_IN1 CFG_IN2 I/O I I I Type LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD Schmitt Trigger LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVPECL Description Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. FINAL DATASHEET 21 22 23 24 25 27 CFG_IN3 CFG_IN4 CFG_IN5 CFG_IN6 CFG_IN7 CLK1N I I I I I I Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Negative differential input reference clock partnered with pin 28. Accepts a wide range of input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given suitable external interface components (see Input and Output Interface Terminations). Selection between CLK1 and CLK2 is configurable between manual or automatic. See Table 5. Positive differential input reference clock partnered with pin 27. Accepts a wide range of input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given suitable external interface components (see Input and Output Interface Terminations). Selection between CLK1 and CLK2 is configurable between manual or automatic. See Table 5. Negative differential input reference clock partnered with pin 31. Accepts a wide range of input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given suitable external interface components (see Input and Output Interface Terminations). Selection between CLK1 and CLK2 is configurable between manual or automatic. See Table 5. Positive differential input reference clock partnered with pin 30. Accepts a wide range of input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given suitable external interface components (see Input and Output Interface Terminations). Selection between CLK1 and CLK2 is configurable between manual or automatic. See Table 5. Used in combination with AUTO_SEL (pin 33) to select the CLK1 input (low) or CLK2 input (high) in manual control mode, or to select automatic switching mode as described in Table 5. Used in combination with SEL_CLK2 (pin 32) to select automatic switching mode as described in Table 5. 28 CLK1P I LVPECL 30 CLK2N I LVPECL 31 CLK2P I LVPECL 32 SEL_CLK2 I LVTTL/ LVCMOSD LVTTL/ LVCMOSD 33 AUTO_SEL I Revision 1.00/September 2007© Semtech Corp. Page 6 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Table 3 Functional Pins (cont...) Pin No. 35 VCP Symbol I/O A Type Analog Description Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output up to a level of 210 μA. Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output up to a level of 210 μA. Active low reset signal with pull up and Schmitt type input. Used to apply an active-low Power-on Reset (POR) signal during system initialization. Should be connected via a capacitor to ground or, if reset control by a microcontroller is required, via a 3.3 V control line. Differential input (typically 8 kHz) where the SYNC signal on this input is sampled and resynchronized to the rising edge of the OUT1 clock signal. Paired with pin 42 (SYNCN). Maximum input frequency is 40 MHz. Will accept LVDS, CML or LVPECL signals when suitable external biasing components are used. See Input and Output Interface Terminations. Differential input (typically 8 kHz) where the SYNC signal on this input is sampled and resynchronized to the rising edge of the OUT1 clock signal. Paired with pin 41 (SYNCP). Maximum input frequency is 40 MHz. Will accept LVDS, CML or LVPECL signals when suitable external biasing components are used. See Input and Output Interface Terminations. A sampled and resynchronized version of the SYNC signal present on SYNCP (pin 41) and SYNCN (pin 42). The SYNC_OUT signal is synchronized to the rising edge of the output clock present on OUT1. If the SYNC function is used, the output frequency on OUT1 should be at least double the frequency of the SYNCP/SYNCN input and restricted to a maximum of 80 MHz. This restriction affects the OUT1 signal only. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation software GUI. See PLL Configuration. FINAL DATASHEET 36 VCN A Analog 40 RESETB I LVTTL/ LVCMOSU Schmitt Trigger LVPECL 41 SYNCP I 42 SYNCN I LVPECL 44 SYNC_OUT O LVTTL/ LVCMOS 45 46 47 48 CFG_IN10 CFG_IN11 CFG_IN8 CFG_IN9 I I I I LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD Revision 1.00/September 2007© Semtech Corp. Page 7 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Description FINAL DATASHEET The device can be fully programmed, without the need for a microprocessor, by hardwiring the configuration input pins CFG_IN[11:0] to ALARM1_CO0, ALARM2_CO1, CFG_OUT2, ALARMC_CO3, VDD and GND as defined by the ACS8947T evaluation software GUI. The PLL has a fully differential external loop filter, allowing the closed loop bandwidth and damping factor to be customized according to target system requirements. The tables below show typical loop filter component values and divider settings for various applications. The ACS8947T is a highly configurable general purpose Integer-N, low-jitter integrated PLL for signal cleaning, dejittering and frequency translation. The PLL is built around an integrated voltage controlled oscillator(VCO) and can be used in a wide range of applications including OC12 clock cleaning for SONET, SDH, Ethernet, PCI, RapidIO, 3G and wireless systems. Table 4 Typical Loop Filter Component Values and Divider Settings Application I/P (MHz) 2.048 1.544 34.368 44.736 19.44 25 62.5 10 133 167 3.84 153.6 O/P (MHz) 65.536 49.408 68.736 44.736 622.08 625 125 100 133 167 61.44 153.6 VCO (MHz/ V) 2883 2767 2749 2863 2488 2500 2500 2800 2660 2672 2457 2457 OSC/8 PFD (MHz) 2.048 1.544 34.37 44.74 19.44 12.5 62.5 10 66.5 167 3.84 153.6 176 224 10 8 16 25 5 35 5 2 80 2 DIVIP Divided By 1 1 1 1 1 2 1 1 2 1 1 1 11 7 5 1 1 1 5 7 5 1 5 1 DIVODD Closed Damping Loop Factor Bandwidth (kHz) 2 2 10 2 2 2 2 100 2 2 30 2 3.8 3.8 1.2 1.2 1.2 1.2 1.2 3.8 1.2 3.8 1.7 3.8 ICP (μA) 210 210 160 40 160 210 40 210 40 10 210 10 CP (nF) 1.5 1.2 0.56 82 150 120 82 0.56 120 4.7 0.18 3.9 Cs (μF) 22 15 0.068 6.8 15 15 15 0.68 15 68 0.68 47 Rs (Ω) 470 680 2700 82 56 68 82 2700 68 150 1500 150 E1 DS1 E3 DS3 SONET Ethernet Ethernet Ethernet PCI Memory 3G Wireless Revision 1.00/September 2007© Semtech Corp. Page 8 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL DATASHEET The ACS8947T is available in a small form factor QFN48 package of outer dimensions 7 mm x 7 mm x 0.9 mm. Figure 3 Example of EVB GUI An evaluation board and GUI software for calculating the required loop filter component values and configuration wiring connections, and for hands-on device assessment, are available on request. Inputs Clock Inputs The ACS8947T has two LVPECL differential clock inputs (CLK1N/P and CLK2N/P) and is capable of locking across a wide frequency range of 580 kHz to 180 MHz. If both input clocks are being used, the frequency difference between the signals presented to CLK1N/P and CLK2N/P must be within ±100 ppm. Unused positive differential inputs should be wired to GND and unused negative differential inputs should be wired to VDD. The clock inputs are designed to accept LVDS, LVPECLor CML inputs, given suitable passive resistive and capacitive interface components. On device reset, the configuration protocol presets the internal divider ratios and enables a fast frequency tuning algorithm that temporarily forces PLL bandwidth and locking range to be wide. This enables the PLL to automatically scan and lock to the target reference frequency present on the selected input channel.Once lock is acquired, the PLL bandwidth is reduced and frequency tracking range limited to ±200 ppm. It is therefore important to ensure that the correct input frequency is present on CLK1N/P and CLK2N/P prior to resetting the ACS8947T. Revision 1.00/September 2007© Semtech Corp. See PLL Configuration for details on how to configure the PLL dividers. Either clock input can be manually or automatically selected as the current reference, based on the detection of clock activity. Signals AUTO_SEL and SEL_CLK2 shown in Table 5 are used to control the input clock selection. In automatic mode, the selection between CLK1 and CLK2 is non-revertive: i.e. if the PLL is locked on to CLK1 and CLK1 fails and the PLL switches to CLK2, when CLK1 becomes operational again, the PLL does not revert to CLK1. Table 5 Clock Input Selection Decoding AUTO_SEL 0 0 1 1 SEL_CLK2 0 1 0 1 Selected Reference CLK1 CLK2 CLK1 AUTOMATIC SELECTION (determined by activity monitor) Feedback Clock Internal path Internal path CLK2 Internal path Page 9 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING External feedback An external feedback mode is available and can be used for greater control of phase discrepancies: for example when using external buffers. In external feedback mode, the reference clock is presented to CLK1N/P and the external feedback signal is presented to CLK2N/P. In this mode, CLK1N/P is the only permitted input. FINAL DATASHEET ALARMC_CO3 is an additional activity alarm that monitors clock inputs to the PFD. This signal is more sensitive than ALARM1_CO0 and ALARM2_CO1, triggering after three missing clock edges to the PFD rather than at complete failure of the input reference clock. Although alarm ALARMC_CO3 has greater sensitivity than the input activity monitor, it may take longer to assert if the input divide ratio is greater than 2. All activity monitor flags are low during normal operation and active high when missing clock cycles are detected. Source Switching Figure 4 Simplified State Diagram of Source Switching ALARMC_CO3 = 1 ALARM1_CO0 = 0 SYNC Input CLK 2 CLK 1 ALARMC_CO3 = 1 ALARM2_CO1 = 0 ALARM SIGNALS: ALARMC_CO3 -- Activity alarm for the currently selected clock (from PFD) ALARM1_CO0 -- Activity alarm for CLK1 ALARM2_CO1 -- Activity alarm for CLK2 F8946D_012SimpStateDiag_01 Figure 4 shows a simplified view of the automatic switching behavior in the presence of activity alarms. Signal ALARMC_CO3 from the PFD is used to disqualify a clock, and signals ALARM1_CO0 and ALARM2_CO1 (representing no activity on input clocks CLK1 and CLK2 respectively), determine whether to select the remaining clock. Switching between CLK1 and CLK2 is nonrevertive. With ALARMC_CO3 providing a view of the currently selected clock that is independent of the ALARM1_CO0 and ALARM2_CO1 signals, source selection behavior can be more complex when these alarm signals disagree. Consequently, to accommodate such behavior, the state machine is necessarily more complex than that shown here: e.g. when a clock signal is disconnected for a very short period, or when an input clock is running at the wrong frequency. For more information, please contact Semtech Sales Support. In addition to the main input clock inputs, a single differential SYNC input is provided. It provides a resynchronization path to SYNC_OUT that is clocked and synchronized to the rising edge of the OUT1 clock. The SYNC input frequency should be limited to half the OUT1 clock rate, up to a maximum of 40 MHz. For correct operation, the OUT1 output frequency should be at least double that of the SYNC clock. Input Divider DIVIP The selected input clock is connected to the PFD via an 8-bit programable divider capable of division ratios from 1 to a maximum 256. Feedback Divider DIVFB The feedback path from the internal 2.35 GHz to 2.9 GHz oscillator to the PFD includes a 9-bit programmable divider that is capable of division ratios from 1 to a maximum of 512. Depending on the chosen output frequency, this divider is in series with a fixed divide-by-8 or the odd divider path described below. Odd Divider DIVODD The odd divider is capable of division ratios 1, 3, 5, 7, 9,11, 13 and 15. The output of the divider is connected to the output multiplexing and divider stage. If odd number division is used, the frequency adjustment factor applies to all outputs - adjusting all selected output frequencies proportionally. Under some PLL configurations, the odd divider may also be included in the feedback path to the PFD. www.semtech.com Activity Alarms Input activity monitors ALARM1_CO0 and ALARM2_CO1 flag the occurrence of six or more consecutive missing cycles from inputs CLK1N/P and CLK2N/P. The alarm signals operate on the input reference clock prior to the internal PFD, and use an internal feedback clock from the VCO to determine whether the reference clock has failed. Revision 1.00/September 2007© Semtech Corp. Page 10 ACS8947T JAM PLL ADVANCED COMMS & SENSING Phase and Frequency Detector The internal phase and frequency detector is designed to operate across the full input frequency range of 580 kHz to 180 MHz and includes the ALARMC_CO3 activity alarm. FINAL DATASHEET Refer to PLL Configuration for details on how to calculate the loop filter component values for a given closed loop bandwidth and phase margin. Automatic calculation is available in the the ACS8947T evaluation software GUI. Voltage Controlled Oscillator The internal VCO operates across a frequency range of 2.35 GHz to 2.9 GHz. The VCO frequency is divided down to the selected output rate, giving a precise 50/50 balanced mark/space ratio for the output. Charge Pumps and External Low-Pass Filter A differential charge pump is used to drive the external loop filter via pins VCN and VCP. For linear operation of the PLL, the differential voltage range is limited to ±1.2 V centered around a typical common mode voltage of 1.25 V. To maintain sensible external component values, the magnitude of the charge pump current (IC) is dependent on the OSC/8 divider ratio as defined in Table 6. Table 6 Relationship of IC and OSC/8 Divider Ratio IC (μA) 10 40 160 210 OSC/8 Divide By 1 -> 2 3 -> 8 9 -> 24 25 -> 512 Output Multiplexer and Divider A 5-bit tapped, differential CML divider tree is used in conjunction with the odd divider to generate the required output frequencies. The divider ratios are set according to the frequency list defined by the external configuration wiring and cannot be modified once the device is locked. The device automatically allocates the frequency list to outputs as part of the PLL configuration sequence. Outputs Four programmable LVPECL/CML differential outputs are provided via signal pairs OUT[4:1]N/P (pins 11/12, 8/9, 5/6 and 2/3). Interfacing to LVDS is also possible using suitable passive components (see Input and Output Interface Terminations). The frequency assigned to each output is programable between 1.23 MHz and 625 MHz and, during device reset, is set by the frequency map defined by the configuration sequence. Although the theoretical maximum output frequency of the PLL is 725 MHz, the output ports are only guaranteed to meet VOH/VOL to a maximum of 625 MHz. Each differential output has a dedicated power supply pin that should be connected to VDD if the output is required to be active. If an output port is not required, connect the dedicated power pin to ground to disable the differential output. The closed loop PLL bandwidth is set by two identical sets of passive RC components that connect to the differential charge pump outputs pins VCN and VCP. Figure 5 shows the recommended configuration of the second order loop differential filter. Figure 5 Configuration of Second Order Loop Filter Revision 1.00/September 2007© Semtech Corp. Page 11 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Lock Detector FINAL Input Jitter Tolerance DATASHEET A simple lock detector is incorporated. It combines the plus and minus phase errors output from the PFD so that, if any phase error signal is present, the LOCKB output drives a PWM +10 μA current. The mark/space ratio indicates the current input phase error. By filtering this signal with a basic external RC parallel filter as shown in Figure 6, a signal whose output level indicates PLL phase and frequency lock is obtained. Figure 6 Lock Detector External RC Filter Jitter tolerance is defined as the maximum amplitude of sinusoidal jitter that can exist on the input reference clock above which the device fails to acquire/maintain lock. For the stand-alone device, the jitter tolerance for an undivided reference (i.e. full rate PFD) is shown in Figure 7. For frequencies below the PLL bandwidth, jitter tolerance is seen to decrease at a rate of -20 dB per decade. For jitter frequencies above the PLL bandwidth, jitter tolerance is limited to 0.9 UI p-p. Note...If the reference clock is divided, then the jitter tolerance will be improved. When the ACS8947T follows an ACS8525, the input jitter tolerance is wholly defined by the latter. The system jitter tolerance is dramatically increased due to the extended phase capture range of the digital PLL within the ACS8525. Figure 7 Jitter Tolerance ACS8947T Input Jitter Tolerance With 2kHz PLL Bandwidth 1000 Input Jitter Amplitude p-p (U I) The filtering components are external so that the time to indicate lock can be optimized for the application. The output indicates both phase and frequency lock. During off-frequency conditions, the LOCKB output is predominately high. 100 ACS8947 ACS8946 Jitter Tolerance 10 OC_12 Tolerance Mask OC_48 Tolerance Mask Jitter Filtering Input jitter is attenuated by the PLL with the frequency cutoff point (Fc), at which jitter is tracked or attenuated, defined by the -3 dB point: i.e. the position of the first pole of the PLL loop filter. The bandwidth is the frequency at which the first pole occurs and is defined by the component value selected for the filter. For a 19.44 MHz input, using a loop filter bandwidth of 2 kHz and damping factor of 1.2 gives: High input jitter attenuation and roll off: - 20 dB/decade from first loop filter pole, (Fc); - 40 dB/decade from 2nd pole (typically 10 x Fc). Jitter peaking is less than 1 dB (dependent on the loop filter components); Typical final output jitter: e.g. 2.8 ps RMS measured over the integration range of 12 kHz to 20 MHz offset from carrier. Revision 1.00/September 2007© Semtech Corp. 1 10 100 1000 10000 100000 1000000 0.1 0.01 Jitter Frequency Offset from Carrier (Hz) Jitter Transfer Jitter transfer is a ratio of input jitter present on the reference clock to filtered jitter present on the output clock. The ACS8947T jitter transfer characteristic is defined solely by the loop filter bandwidth. Figure 8 is an example showing the measured jitter transfer characteristic on a 19.44 MHz reference clock with a closed loop bandwidth of 2 KHz and a damping factor of 1.2. www.semtech.com Page 12 ACS8947T JAM PLL ADVANCED COMMS & SENSING Figure 8 Jitter Transfer Characteristic - ACS8947T Stand-alone ACS8944 RMS Jitter Transfer Curve 3.0 0.0 -3.0 -6.0 -9.0 H(s) dB -12.0 -15.0 -18.0 -21.0 -24.0 -27.0 100 FINAL PLL Configuration DATASHEET TBIL On device reset all divider ratios, charge pump settings, lock detector mode and output pad types are set by the Configuration Block, which decodes the wiring connections present on CFG[11:0]. This allows the PLL to be entirely configured without the need for an external microprocessor. The configuration pins CFG[11:0] (device pins 18:25 and 48:45) are hardwired (via VDD, GND, ALARM1_CO0, ALARM2_CO1, CFG_OUT2, or ALARMC_CO3) to produce a unique programming code. On device reset, this code is decoded and used to configure the PLL. 1000 Frequency (Hz) 10000 100000 Phase Noise Performance The inherent jitter generation by the ACS8947T is shown in the phase noise plot in Figure 9, measured on a 155.52 MHz output clock using an input reference of 19.44 MHz. Figure 9 Phase Noise Offset from Carrier of ACS8947T 622.08 MHz output clock Typical Phase Noise @ 155.52MHz 1.0E+02 0 1.0E+03 1.0E+04 1.0E+05 Evaluation software that calculates the configuration hardwire connection matrix for CFG[11:0] based on the required PLL setup is available for download from Semtech. Figure 10 shows a typical connection sheet. Figure 10 Example of ACS8947T Connection Sheet Frequency (Hz) 1.0E+06 1.0E+07 -20 (dBc/Hz) -40 -60 TBIL Use of the ACS8947T evaluation software is the simplest and preferred method of calculating the required divider ratios as this will also calculate loop filter component values and configuration wiring settings. Phase Noise -80 -100 -120 -140 -160 Revision 1.00/September 2007© Semtech Corp. Page 13 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL DATASHEET Figure 11 ACS8947T - Typical Closed Loop Transfer Function Closed Loop Gain GPO Frequency FPO Output Jitter The output jitter meets all requirements of ITU, Telcordia and ETSI standards for SONET rates up to 622.08 MHz (OC-12/STM-4). See Electrical Specifications for details on the jitter figures across the different output jitter frequency bands relevant to each specification. Layout Recommendations It is highly recommended that a stable and filtered 3.3 V power supply is used for the ACS8947T. A separate filtered power and ground plane is recommended, with supply decoupling capacitors of 10 nF and 100 pF utilizing good, high-frequency chip capacitors (0402 or 0603 format surface mount package) on each VDD. For optimum jitter cleaning performance, additional care should be taken over the supply connection to VDDOSC, which should be supplied directly from a 3.3 V LDO or a 4R7/68UF low-pass filter. The wiring connections required for device configuration are calcuated by the ACS8947T Evaluation Software GUI. This program provides a schematic definition for the wired connections to CFG[11:0] and includes a loop filter component calculator. Good differential signal layout on the input and output lines should be used to ensure matched track impedance and phase. Contact Semtech directly for further layout recommendations. www.semtech.com Device Reset The RESETB pin is active low and requires a minimum reset pulse duration of 100 ms once the power supplies are stable and powered up. When the reset process is triggered, the required PLL settings are decoded from the configuration wiring connections, and the internal control logic waits for the presence of an input signal of approximately the correct frequency. When a suitable input clock signal is detected, the ACS8947T calibrates the VCO using a fast tuning algorithm, and both frequency-lock and phase-lock to the input reference. This calibration routine is run only after a reset condition, so the RESETB pin should be held low until the input frequency is within 200 ppm of nominal. Revision 1.00/September 2007© Semtech Corp. Page 14 ACS8947T JAM PLL ADVANCED COMMS & SENSING Example Schematic FINAL DATASHEET Figure 12 Generic Line Card Clock Source with Protection - Example Schematic Notes: (i) For configuration wiring information, refer to the ACS8947T evaluation software GUI. (ii) For optimal performance, use a low voltage dropout (LDO) regulator to supply VDDA2. Revision 1.00/September 2007© Semtech Corp. Page 15 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Electrical Specifications Maximum Ratings Important Note. The absolute maximum ratings given in Table 7 are stress ratings only, and functional operation of the device at conditions other than those indicated in Table 8 to Table 16 of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 7 Absolute Maximum Ratings Parameter Supply voltage (D.C.): VDD01, VDD02, VDD03, VDD04, VDDP1, VDDP2, VDDADIV, VDDARF, VDDOSC Input voltage (non-supply pins): Digital Inputs: CFG_IN0, CFG_IN1, CFG_IN2, CFG_IN3, CFG_IN4, CFG_IN5, CFG_IN6, CFG_IN7, CFG_IN8, CFG_IN9, CFG_IN10, CFG_IN11, SELCLK2, AUTO_SEL, RESETB Input voltage (non-supply pins) LVPECL Inputs: CLK1N, CLK1P, CLK2N, CLK2P, SYNCN, SYNCP ANALOG I/O: VCN, VCP, LOCKB Output voltage (non-supply pins): Digital Output: ALARM1_C01, ALARM2_CO1, CFG_OUT2, ALARMC_CO3, SYNC_OUT LVPECL Outputs: OUT1N, OUT1P, to OUT 4N/P Ambient operating temperature range Storage temperature Reflow temperature (Pb) Reflow temperature (Pb Free) ESD HBM (Human Body Model)(i), (ii) Latchup(iii) Symbol VDD VIN Minimum -0.5 -0.5 Maximum 3.6 5.5 Units V V FINAL DATASHEET VIN -0.5 VDD + 0.5 V VOUT -0.5 VDD + 0.5 V TA TSTOR TREPB TREPBFREE ESDHBM ILU -40 -50 2 ±100 +85 +150 +245 +260 - °C °C °C °C kV mA Notes: (i) All pins pass 2 kV HBM except VCN/VCP which are rated at 500 V HBM. (ii) Tested to JEDEC standard JESD22-A114. (iii) Tested to JEDEC standard JESD78. Revision 1.00/September 2007© Semtech Corp. Page 16 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Operating Conditions Table 8 Operating Conditions Parameter Supply voltage (DC): VDDP1, VDDP2, VDDADIV, VDDARF, Supply voltage (DC): VDDOSC Supply voltage (DC): VDD01, VDD02, VDD03, VDD04. * 3.135. V min required to enable output. Supply may be connected to 0 V to disable the associated output. Ambient temperature range VDD01 supply current VDD02 supply current VDD03 supply current VDD04 supply current VDDP1 supply current VDDP2 supply current VDDADIV supply current VDDARF supply current VDDOSC supply current Device total power dissipation with all outputs on @625 MHz. Excluding power dissipation in external biasing components. Symbol VDD VDDOSC VDD Minimum 3.135 3.0 3.135 or 0 V* Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 Units V V V FINAL DATASHEET TA IDD01 IDD02 IDD03 IDD04 IDDP1 IDDP2 IDDADIV IDDARF IDDVOSC PTOT -40 - 29 29 29 29 25 22 100 64 20 +85 33 33 33 33 31 30 111 72 25 1,2 °C mA mA mA mA mA mA mA mA mA W - 1,1 Note...Supply currents for VDDOn assumes CML 50Ω termination. Thermal Characteristics Table 9 Thermal Conditions Parameter Thermal resistance junction to ambient Operating junction temperature Symbol θJA TJCT Minimum Typical Maximum 25 125 Units °C/W °C Revision 1.00/September 2007© Semtech Corp. Page 17 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING AC Characteristics Table 10 AC Characteristics Parameter Output to output skew(i) Input to output delay SYNC_OUT to OUT1 delay OUT1 to SYNC set-up OUT1 to SYNC hold Input clock rise/fall time(ii) (CLK1, CLK2, SYNC) LVPECL output rise/fall time(ii), (iii) CML output rise/fall time(ii), (iv) Symbol tOSK tPDIO tPDSO tSS tSH tCRF tPECLRF tCMLRF tSRF tCDF tODC tRPW tFT FIN FOUT Minimum 0.5 -2.9 3.7 2.8 40 48 100 10 0.580 1.230 Typical 0.8 0.7 3.0 50 50 Maximum 100 3.0 -0.4 10 1.2 1.2 5.0 60 52 60 180 625 Units ps ns ns ns ns ns ns ns ns % % ms ms MHz MHz FINAL DATASHEET SYNC_OUT rise/fall time(ii), (v) Input clock duty cycle (CLK1, CLK2, SYNC) Output clock duty cycle RESETB pulse width after power-up Settling time before start of frequency tuning after RESETB high Input reference frequency Output frequency Notes: (i) Outputs running at same frequency. (ii) Rise/fall time measured 10% to 90%. (iii) Using output load specified in Figure 16. (iv) Using output load specified in Figure 13. (v) Using 50 Ω load. (vi) Using 5 pF capacitive load. Revision 1.00/September 2007© Semtech Corp. Page 18 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING DC Characteristics Across all operating conditions, unless otherwise stated. Table 11 VCN/VCP Differential Charge Pump Input/Output Port Parameter Common mode voltage VCN/VCP linear tuning range Low level output voltage High level output voltage Output current (10 μA) Output current (40 μA) Output current (160 μA) Output current (210 μA) Symbol VCM VTUNE VOL VOH IO IO IO IO Minimum 1.0 GND + 0.2 8 32 128 168 Typical 1.25 ±1.2 10 40 160 210 Maximum 1.5 VDD - 0.2 12 48 192 252 Units V V V V μA μA μA μA FINAL DATASHEET Table 12 DC Characteristics: LVCMOS Input Ports with Internal Pull-down/LVCMOS Schmitt Input Port with Internal Pull-up Parameter VIN High VIN Low Pull-down resistor Pull-up resistor (Schmitt Input) Input current Symbol VIH VIL RPD RPU IIN Minimum 2 43 53 -10 Typical Maximum 0.8 108 113 +10 Units V V kΩ kΩ μA Table 13 DC Characteristics: LVPECL Input Port Parameter LVPECL input offset voltage differential inputs (Note (ii)) Input differential voltage LVPECL input low voltage single-ended input (Note (i)) LVPECL input high voltage single-ended input (Note (i)) Input high current input differential voltage VID = 1.4 V Input low current input differential voltage VID = 1.4 V Symbol VIO_LVPECL VID_LVPECL VIL_LVPECL_S VIL_LVPECL_S IIH_LVPECL IIL_LVPECL Minimum VDD-2.0 0.1 VSS VDD-1.3 -10 -10 Typical Maximum VDD-0.5 1.4 VDD-1.5 VDD +10 +10 Units V V V V μA μA Notes: (i) Unused differential input terminated to VDD-1.4 V. (ii) Both pins must remain within the supply voltage, i.e. >VSS and