EDGE6420

Edge6420 Per-Pin Electronics Companion DAC HIGH-PERFORMANCE PRODUCTS – ATE Description The Edge6420 is a monolithic device which has 64 integrated DACs that are designed specifically for all per channel wide-voltage and current levels needed for pin electronics inside automatic test equipment. The chip can also be used for other applications requiring multiple integrated voltage or current DAC outputs. Voltage DACs • Wide voltage (17V range) • Adjustable full scale range • Adjustable minimum output • 13 bits resolution Current DACs • ~3.6 mA full scale range • Adjustable full scale range • 6/13 bits resolution The DACs are programmed using a serial interface. The inclusion of 64 total DACs into 1 package offers an extremely high density, flexible solution normally implemented using multiple components. Features 64 Total DACs/Package Including: • Wide Voltage Output Range (17V Range); Useful for Supervoltage • 44 Voltage DACs / Package • 20 Current DACs / Package • Adjustable Full Scale Range • Adjustable Output Voltage Offset • Small 13x13mm BGA Package • All DACs are Guaranteed Monotonic Applications • • Test Equipment Applications requiring multiple programmable voltage and currents Functional Block Diagram SDI Channel 0 DAC 0 VOUT_CH0_[0:10] IOUT_CH0_[0:4] Channel 1 CE VOUT_CH1_[0:10] IOUT_CH1[0:4] CK Channel 2 UPDATE VOUT_CH2_[0:10] IOUT_CH2_[0:4] RESET* Channel 3 VOUT_CH3_[0:10] DAC 63 IOUT_CH3_[0:4] SDO CK_OUT Revision 4 / April 29, 2002 1 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE PIN Description Ball Name VOUT_CH[0:3]_[0:4] Ball Location G13, G15, F14, F13, F15, G3, F1, F2, F3, E1, J3, J1, K2, K3, K1, J13, K15, K14, K13, L15 E14, E15, E2, E3, L2, L1, L14, L13 E13, D14, D1, D2, L3, M2, M15, M14 D15, D13, D3, C1, M1, M3, M13, N15 C15, C14, B1, C2, N1, N2, P15, N14 H14, H15, G14, H3, G1, G2, H2, H1, J2, H13, J15, J14 P5 P11, R10, N10, P10, R9, N9 R6, P6, N6, R5 B10 A11 C6 A10 C5 B5 A6 B11 B6 C9 C3, C12, N4, R12 C7, N7 A9, R8, B9, P9 B8, N8 A8, R7 B7, P7 C8, P8 2 Description Group A DAC output volages for channels 0 to 3. VOUT_CH[0:3]_[5:6] VOUT_CH[0:3]_[7:8] VOUT_CH[0:3]_[9:10] IOUT_CH[0:3]_[0:1] IOUT_CH[0:3]_[2:4] R_MASTER R_GAIN_(A,B,C,D,E,F) R_OFFSET_(A,B,C,D) SDI CK UPDATE CE RESET* SDO CK_OUT SCAN_OUT TEST_MODE VREF AVCC AVDD VEE AGND SGND DVDD DGND  2000 Semtech Corp. Group B DAC output voltages for channels 0 to 3. Group C DAC output voltaqges for channels 0 to 3. Group D DAC output voltages for channels 0 to 3. Group E DAC output voltages for channels 0 to 3. Group F DAC output voltages for channels 0 to 3. Master external resistor used to define the reference current for the gain and offset setting block for voltage DACs. Pins for external resistor to set current gain for both voltage and current output DACs. Pins for external resistor to set the offset voltage for Group A, B, C, and D voltage output DAC's. Serial data input. Clock for the input data shift register. Strobe to transfer the shift register data to the DACs. Chip enable. Active low chip reset. Sets the DACs to a known default state. Serial Data Out. Regenerated clock output for daisy chain purposes. Analog output test pin. Test mode pin for internal scan. Reference input (for a 2.5V band gap). Positive analog voltage supply. Analog 5V supply. Negative analog voltage supply. Analog ground (minimize noise). Supply ground. Digital voltage supply. Digital supply ground. www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE PIN Description (continued) Ball Name N/C Ball Location A1, A2, A3, A4, A5, A7, A12, A13, A14, A15, B2, B3, B4, B12, B13, B14, B15, C4, C10, C11, C13, N3, N5, N11, N12, N13, P1, P2, P3, P4, P12, P13, P14, R1, R2, R3, R4, R11, R13, R14, R15 Description Not connected.  2000 Semtech Corp. 3 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE PIN Description (continued) 13mm x 13mm CSPBGA Package A1 Ball Pad Indicator E6420 Top View 13 mm x 13 mm CSPBGA Top View A1 A2 1 N/C A3 144 N/C A4 142 N/C A5 139 N/C A6 136 N/C A7 134 131 N/C A8 128 SGND A9 125 VEE A10 122 CE A11 119 CK A12 116 N/C A13 113 N/C A14 111 N/C A15 109 N/C A B1 CK_OUT B2 3 2 N/C B3 141 N/C B4 138 N/C B5 135 SDO B6 132 TEST_MODE B7 129 DVDD B8 127 AGND B9 124 VEE B10 121 SDI B11 118 SCAN_OUT B12 115 N/C B13 112 N/C B14 110 N/C B15 108 N/C B C1 IOUT_CH1_0 C2 5 4 IOUT_CH1_1 C3 143 AVCC C4 140 N/C C5 137 RESET* C6 133 UPDATE C7 130 AVDD C8 126 DGND C9 123 VREF C10 120 N/C C11 117 N/C C12 114 AVCC C13 107 N/C C14 105 IOUT_CH0_1 C15 106 IOUT_CH0_0 C D1 VOUT_CH1_10 D2 8 7 VOUT_CH1_8 D3 6 VOUT_CH1_9 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 104 VOUT_CH0_10 D14 102 VOUT_CH0_8 D15 103 VOUT_CH0_9 D E1 VOUT_CH1_7 E2 11 10 VOUT_CH1_5 E3 9 VOUT_CH1_6 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 101 VOUT_CH0_7 E14 99 VOUT_CH0_5 E15 100 VOUT_CH0_6 E F1 VOUT_CH1_4 F2 14 13 VOUT_CH1_2 F3 12 VOUT_CH1_3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 97 VOUT_CH0_3 F14 96 VOUT_CH0_2 F15 98 VOUT_CH0_4 F VOUT_CH1_1 G1 G2 17 16 IOUT_CH1_4 G3 15 VOUT_CH1_0 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 94 VOUT_CH0_0 G14 93 IOUT_CH0_4 G15 95 VOUT_CH0_1 G H1 IOUT_CH1_3 H2 20 19 IOUT_CH2_2 H3 18 IOUT_CH1_2 H4 H5 H6 H J1 IOUT_CH2_3 J2 23 21 IOUT_CH2_4 J3 22 VOUT_CH2_0 J4 J5 J6 J K1 NOTE: Balls populating the inner 9x9 grid are for improved thermal H7 H8 H9 dissipation. This middle grid of H10 balls should be connected to the VEE plane or left floating. Order E6420BBG if populated middle J10 J7 J8 J9 is desired. K7 K8 K9 K10 H11 H12 H13 90 IOUT_CH3_2 H14 91 IOUT_CH0_2 H15 92 IOUT_CH0_3 J11 J12 J13 87 VOUT_CH3_0 J14 88 IOUT_CH3_4 J15 89 IOUT_CH3_3 VOUT_CH2_1 K2 26 24 VOUT_CH2_2 K3 25 VOUT_CH2_3 K4 K5 K6 K11 K12 K13 84 VOUT_CH3_3 K14 85 VOUT_CH3_2 K15 86 VOUT_CH3_1 K L1 VOUT_CH2_4 L2 28 27 VOUT_CH2_5 L3 29 VOUT_CH2_7 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 81 VOUT_CH3_6 L14 82 VOUT_CH3_5 L15 83 VOUT_CH3_4 L M M1 VOUT_CH2_6 M2 31 30 VOUT_CH2_8 M3 32 VOUT_CH2_10 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 78 VOUT_CH3_9 M14 79 VOUT_CH3_8 M15 80 VOUT_CH3_7 VOUT_CH2_9 N1 N2 34 33 IOUT_CH2_1 N3 35 N/C N4 42 AVCC N5 45 N/C N6 48 R_OFFSET_C N7 51 AVDD N8 54 AGND N9 58 R_GAIN_F N10 61 R_GAIN_C N11 65 N/C N12 68 N/C N13 71 N/C N14 76 IOUT_CH3_1 N15 77 VOUT_CH3_10 N P1 IOUT_CH2_0 P2 36 N/C P3 38 N/C P4 40 N/C P5 43 N/C P6 46 49 R_OFFSET_B P7 52 DVDD P8 55 DGND P9 57 VEE P10 60 R_GAIN_D P11 63 R_GAIN_A P12 66 N/C P13 69 N/C P14 74 N/C P15 75 IOUT_CH3_0 P R1 R_MASTER R2 37 N/C R3 39 N/C R4 41 N/C R5 44 N/C R6 47 50 R_OFFSET_A R7 53 SGND R8 56 VEE R9 59 R_GAIN_E R10 62 R_GAIN_B R11 64 N/C R12 67 AVCC R13 70 N/C R14 72 N/C R15 73 N/C R R_OFFSET_D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15  2000 Semtech Corp. 4 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE PIN Description (continued) 13mm x 13mm CSPBGA Package A1 Ball Pad Indicator Actual Size Bottom View 15 A15 109 N/C 14 A14 111 N/C 13 A13 113 N/C 12 A12 116 N/C 11 A11 119 CK 10 A10 122 CE 9 A9 125 VEE 8 A8 128 SGND 7 A7 131 N/C 6 A6 134 CK_OUT 5 A5 136 N/C 4 A4 139 N/C 3 A3 142 N/C 2 A2 144 N/C 1 A1 1 N/C A B15 108 N/C B14 110 N/C B13 112 N/C B12 115 N/C B11 118 SCAN_OUT B10 121 SDI B9 124 VEE B8 127 AGND B7 129 DVDD B6 132 TEST_MODE B5 135 SDO B4 138 N/C B3 141 N/C B2 2 N/C B1 3 IOUT_CH1_0 B C C15 106 IOUT_CH0_0 C14 105 IOUT_CH0_1 C13 107 N/C C12 114 AVCC C11 117 N/C C10 120 N/C C9 123 VREF C8 126 DGND C7 130 AVDD C6 133 UPDATE C5 137 RESET* C4 140 N/C C3 143 AVCC C2 4 IOUT_CH1_1 C1 5 VOUT_CH1_10 D15 103 VOUT_CH0_9 D14 102 VOUT_CH0_8 D13 104 VOUT_CH0_10 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 6 VOUT_CH1_9 D2 7 VOUT_CH1_8 D1 8 VOUT_CH1_7 D E15 100 VOUT_CH0_6 E14 99 VOUT_CH0_5 E13 101 VOUT_CH0_7 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 9 VOUT_CH1_6 E2 10 VOUT_CH1_5 E1 11 VOUT_CH1_4 E F15 98 VOUT_CH0_4 F14 96 VOUT_CH0_2 F13 97 VOUT_CH0_3 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 12 VOUT_CH1_3 F2 13 VOUT_CH1_2 F1 14 F VOUT_CH1_1 G15 95 VOUT_CH0_1 G14 93 IOUT_CH0_4 G13 94 VOUT_CH0_0 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 15 G2 16 IOUT_CH1_4 G1 17 IOUT_CH1_3 H15 92 IOUT_CH0_3 H14 91 IOUT_CH0_2 H13 90 IOUT_CH3_2 H12 H11 H10 J15 89 IOUT_CH3_3 J14 88 IOUT_CH3_4 J13 87 VOUT_CH3_0 J12 J11 J10 NOTE: Balls populating the inner 9x9 grid are for improved thermal H8 H7 H9 H6 dissipation. This middle grid of balls should be connected to the VEE plane or left floating. Order E6420BBG if populated middle J8 J7 J9 J6 is desired. K9 K8 K7 K6 G H J K L M VOUT_CH1_0 H5 H4 H3 18 IOUT_CH1_2 H2 19 IOUT_CH2_2 H1 20 IOUT_CH2_3 J5 J4 J3 22 VOUT_CH2_0 J2 21 IOUT_CH2_4 J1 23 VOUT_CH2_1 K15 86 VOUT_CH3_1 K14 85 VOUT_CH3_2 K13 84 VOUT_CH3_3 K12 K11 K10 K5 K4 K3 25 VOUT_CH2_3 K2 24 VOUT_CH2_2 K1 26 VOUT_CH2_4 L15 83 VOUT_CH3_4 L14 82 VOUT_CH3_5 L13 81 VOUT_CH3_6 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 29 VOUT_CH2_7 L2 27 VOUT_CH2_5 L1 28 VOUT_CH2_6 M15 80 VOUT_CH3_7 M14 79 VOUT_CH3_8 M13 78 VOUT_CH3_9 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 32 VOUT_CH2_10 M2 30 VOUT_CH2_8 M1 31 VOUT_CH2_9 N15 77 VOUT_CH3_10 N14 76 IOUT_CH3_1 N13 71 N/C N12 68 N/C N11 65 N/C N10 61 R_GAIN_C N9 58 R_GAIN_F N8 54 AGND N7 51 AVDD N6 48 R_OFFSET_C N5 45 N/C N4 42 AVCC N3 35 N/C N2 33 IOUT_CH2_1 N1 34 IOUT_CH2_0 N P15 75 IOUT_CH3_0 P14 74 N/C P13 69 N/C P12 66 N/C P11 63 R_GAIN_A P10 60 R_GAIN_D P9 57 VEE P8 55 DGND P7 52 DVDD P6 49 R_OFFSET_B P5 46 R_MASTER P4 43 N/C P3 40 N/C P2 38 N/C P1 36 N/C P R15 73 N/C R14 72 N/C R13 70 N/C R12 67 AVCC R11 64 N/C R10 62 R_GAIN_B R9 59 R_GAIN_E R8 56 VEE R7 53 SGND R6 50 R_OFFSET_A R5 47 R_OFFSET_D R4 44 N/C R3 41 N/C R2 39 N/C R1 37 N/C R  2000 Semtech Corp. 5 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description Chip Overview The Edge6420 provides 64 output levels (44 voltage and 20 current). These outputs can easily be configured to generate the specific analog voltage and current requirements for 4 channels of ATE pin electronics including: – 3 level driver – Window comparator – Active load – Per pin PMU without requiring any scaling or shifting via external components. The Edge6420 has the flexibility to be used in other configurations for other applications. Programming of the chip is done using a 4 bit digital interface comprised of: – Serial Data In – Clock – Update – Chip Enable. Attribute Total # of DACs in Group Type Resolution (# of bits) Output Range: Max DAC Range (Note 1) Offset Range Group A 5 per channel V 13 Group B 2 per channel V 13 Group C 2 per channel V 13 Group D 2 per channel V 13 Group E 2 per channel I 13 Group F 3 per channel I 6 Grouping of DACs DACs are separated into 4 channels of 6 distinct functional groups. Groups are defined by: – – – – Type (voltage or current output) Resolution (# of bits) Output range Output compliance. Table 1 defines the DACs on a per channel basis: 11.5V -3.5V to 2.5V 11.5V -3.5V to 2.5V 17V -3.5V to 2.5V 11.5V -3.5V to 2.5V 3.6 mA –128 LSB (Note 2) no –0.2 to AVDD – 2.2V (Note 3) 3.6 mA 0 Adjustable Output Offset Compliance yes ±100 µA yes ±100 µA yes ±100 µA yes ±100 µA no –0.2 to AVDD – 2.2V (Note 3) Note 1: Note 2: Note 3: The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details. –128 LSB is equivalent to –128 * LSB, where LSB = Range / 213. For max range case of 3.6 mA, this offset would thus be: –56.26 µA of offset current at Code 0. Compliance specified in the table is at IOUT = 1.3mA. Maximum compliance is lower at higher currents. Please refer to specifications for compliance at other output currents. Table 1. DAC Grouping  2000 Semtech Corp. 6 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) DAC Voltage Output Overview The output voltage of Group A, B, C, and D DACs is governed by the following equation: VOUT_[A:D] = KG[A:D] * VREF * R_GAIN_[A:D] * R_MASTER DATA 8192 + VOFFSET_[A:D] Minimum / Maximum Output Voltages See Table 2 for the minimum and maximum possible voltages of a voltage output. DAC Setting MSB ... LSB 0000H VOUT_[A:D] (V) VOFFSET_[A:D] VMAX_[A:D] Equation 1. where: DATA corresponds to the base-10 value of the binary data loaded into the shift register shown in Figure 2. KG[A:D] is a multiplying factor that is fixed, as follows: 1FFFH Table 2. Minimum/Maximum Output Voltages KGA = 4 KGC = 8 VREF = 2.5V Offset The offset for each of the voltage DACs is governed by the following equation: VOFFSET_[A:D] = K V OFFSET * REF * 0.5 – R_OFFSET_[A:D] R_MASTER KGB = 4 KGD = 4 where: VOFFSET[A:D] is defined in equation 2 and VMAX_[A:D] = KG[A:D] * VREF * R_GAIN_[A:D] R_MASTER * 8191 8192 + VOFFSET_[A:D] Equation 3. Equation 2. where: KOFFSET = 2 VREF = 2.5V External Resistors The most negative voltage possible for the Edge6420 is –3.5V when VEE = –4.5V. Resolution The resolution of the DACs in Groups A, B, C, and D is: VRANGE_[A:D] / 213 where VRANGE_[A:D] is defined in Equation 4. The recommended resistor values for the above equations are as follows: R_MASTER = 100KΩ (0.1% precision) R_GAIN_[A:D] = (0.4 to 1.15) * R_MASTER R_OFFSET_[A:D] = (0.0 to 1.2) * R_MASTER Range The range of the DACs in Groups A, B, C and D is: VRANGE_[A:D] = KG[A:D] * VREF * R_GAIN_[A:D] * R_MASTER 8191 8192 Equation 4.  2000 Semtech Corp. 7 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Group A DACs There are five Group A DACs/channel. Group A DACs have a centralized offset, gain and range that is independent of any other group. Group A DACs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: VOUT_A = 10 * R_GAIN_A R_MASTER * DATA 8192 + VOFFSET_A VOUT_D = 10 * R_GAIN_D R_MASTER * DATA 8192 + VOFFSET_D Group D DACs There are two Group D DACs/channel. Group D DACs have a centralized offset, gain and range that is independent of any other group. Group D DACs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: where: VOFFSET_A = 5 * .5 – R_OFFSET_A R_MASTER where: VOFFSET_D = 5 * .5 – R_OFFSET_D R_MASTER Note: VREF = 2.5V Note: VREF = 2.5V Group B DACs DAC Current Output Overview There are two Group B DACs/channel. Group B DACs have a centralized offset, gain and range that is independent of any other group. Group B DACs are characterized by 13 bit resolution and their typical outputs are governed by the following equation:. VOUT_B = 10 * R_GAIN_B R_MASTER * DATA 8192 + VOFFSET_B The output current of Group E and F DACs is governed by the following equation: IOUT_[E:F] = KG[E:F] * IREF_[E:F] * DATA MAX_COUNT_[E:F] + IOFFSET_[E:F] Equation 5. where: DATA corresponds to the base-10 value of the binary data loaded into the shift resister in Figure 2. IREF_[E:F] = VREF R_GAIN_[E:F] where: VOFFSET_B = 5 * .5 – R_OFFSET_B R_MASTER Note: VREF = 2.5V KG[E:F] is a multiplying factor that is fixed, as follows: Group C DACs KGE = 80 There are two Group C DACs/channel. Group C DACs have a centralized offset, gain and range that is independent of any other group'. Group C DACs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: VOUT_C = 20 * R_GAIN_C R_MASTER * DATA 8192 + VOFFSET_C KGF = 80 VREF = 2.5V MAX_COUNT_E = 8192 MAX_COUNT_F = 64 where: VOFFSET_C = 5 * .5 – R_OFFSET_C R_MASTER Note: VREF = 2.5V  2000 Semtech Corp. 8 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Offset The typical offset for each current DAC is governed by the following equations: IOFFSET_E =– KGE * VREF R_GAIN_E 128 * MAX_COUNT_E Equation 6. IOFFSET_F = 0 Group E DACs There are 2 Group E DACs/channel. Group E DACs are characterized by: • Current outputs (current flows out of the chip) • 13 bit resolution • Fixed offset (–128 * LSB typical) • Adjustable full scale range (but < 3.6 mA). The output current equation for Group E DACs is: IOUT_E = DATA 8192 * 200 R_GAIN_E – 3.125 R_GAIN_E where: 55 kΩ ≤ R_GAIN_E ≤ 156 kΩ Note: VREF = 2.5V Group F DACs There are 3 Group F DACs/channel. Group F DACs are characterized by: • Current outputs (current flows out of the chip) • 6 bit resolution • Fixed offset (0 typical) • Adjustable full scale range (but < 3.6 mA). The output current equation for Group F DACs is: IOUT_F = DATA * 64 200 R_GAIN_F where: 55 kΩ ≤ R_GAIN_F ≤ 156 kΩ Note: VREF = 2.5V  2000 Semtech Corp. 9 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Address Map Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 Channel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Group A A A A A B B C C D D E E F F F Type V V V V V V V V V V V I I I I I Typical Uses Driver & Comparator Levels PPMU Comparator Thresholds PPMU Force Voltage, Flash Programming Supervoltage Load Commutating Voltage Load Source and Sink Programming currents Chip Bias, Rising/Falling Slew Rate Adjust Same format as above for Channel 1. 32-47 2 Same format as above for Channel 2. 48-63 3 Same format as above for Channel 3. 64 N/A All V/I Parallel Load for all DACs 65-255 Not used (reserved for future upgradability).  2000 Semtech Corp. 10 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Decode and Individual DAC Update RESET* This is a 13-bit latch for DAC (Note: there are some current output DACs that require only 6-bit latches) L Q DAC DAC output #0 EN R L Q DAC DAC output #1 EN R . . . . Q . . . . (for Parallel Load) . L . . . DAC DAC output #63 Q63 Q64 Q0 Q1 . . . EN R ADDRESS DECODER ADDR 7 13 Delay UPDATE D CE Q LOAD R RESET CENTRAL DAC LATCH (24 Latches) CK D0:D12 A0:A6 24-BIT SHIFT REGISTER SDI RESET* CK_OUT SDO RESET Programming Logic Figure 1. DAC Functionality Block Diagram  2000 Semtech Corp. 11 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Programming Sequence The DACs are programmed serially (see Figures 1, 2a, 2b, and 3). On each rising edge of CK, SDI is loaded into a shift register. It requires 24 Clocks to fully load the shift register (8 address bits + 16 data bits). For Groups A, B, C, D, and E DACs: Address and data are loaded LSB first, MSB last. In a 24 clock sequence, A0, as shown in Figure 2a, is loaded into the shift register on the first CK rising edge, and D15 is loaded last on the 24th rising CK edge. Note that a 24th falling CK edge is required to transfer the data from the Central DAC Latch to the selected DAC latch (See Figure 1). See detailed Timing Diagrams in the "AC Characteristics" specifications section. For Group F DACs: The loading sequence is the same as Groups A-E, but high DATA Group F uses only 6 bits, and these bits must be programmed as shown in Figure 2b. 24 clock cycles are required for programming, with A0 loaded on the first rising CK edge, and D8 (as shown in Figure 2b) loaded on the 24th rising CK edge. As is the case with other groups, a 24th falling edge of CK24 is required for proper programming of Group F DACs. Chip Enable CE is a synchronous input which determines whether the Central DAC latch shown in Figure 1 is loaded with data from the shift register. CE is also necessary to update a DAC. If CE is high, rising edges of CK load data from the shift register to an internal latch. If CE is low, central DAC latch updating is disabled. CE low Central and Individual DAC Latch "Load" Status Central and individual DAC latch loading is disabled Central and individual DAC latches are loaded ADDRESS SDI D15 D14 D13 D12 D11 D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB A7 A6 A5 MSB A4 A3 A2 A1 A0 LSB Bits reserved for future upgradability Bits reserved for future upgradability Figure 2a. Format of Address and Data in Shift Register for Group A, B, C, D, and E DACs (13-bits) DATA "Don't Care" bits that must be included in programming sequence ADDRESS SDI D8 D7 D6 D5 MSB D4 D3 D2 D1 D0 LSB X X X X X X X A7 A6 A5 MSB A4 A3 A2 A1 A0 LSB Bits reserved for future upgradability Bits reserved for future upgradability Figure 2b. Format of Address and Data in Shift Register for Group F DACs (6-bits) ≈≈ ≈≈ LSB Addr. SDI A0 A1 MSB Addr. A6 A7 LSB Data D0 D1 MSB Data D14 D15 Next Set of Data A0 A1 CK ≈ ≈ CK1 TCK CK24 CE UPDATE Update Selected DAC Register SDO Previous Data A0 A1 Corresponds to A0 loaded at CK1 Figure 3. Serial Data Programming Sequence  2000 Semtech Corp. 12 www .semtech.com ≈≈ Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Digital Outputs SDO is a CMOS output, swinging rail to rail between DVDD and DGND. Chip Reset and Power Up RESET* for the Edge6420 is active low. When the Edge6420 first powers up, the latches will turn on to the same state as though RESET* had been asserted. When RESET* is brought low, the latches, and therefore the DAC levels, will go to a known state that corresponds to a specific DATA code. See the "Application Information" section for an example of how this functionality works. The known states are: GROUP A B C D E F RESET* State (Code) 1000H 1000H 1000H 1000H 0000H 1000H Power Supply Sequence Power supplies should be asserted in the following order: 1. 2. 3. 4. VEE AVDD DVDD AVCC To avoid latchup and ensure a predictable power up, the above sequence should be followed. Analog Scan Test Feature Voltage Outputs Each voltage output of the Edge6420 has high impedance FET(s) connected from the outputs to a common analog scan line. The feature utilizes the normal address decoding, as shown on page 8, as well as a "high" level on the TEST_MODE pin (see truth table below). TEST_MODE 0 1 SCAN STATE Scan Off Scan On Care should be taken to ensure RESET* is invoked properly. It is critical to ensure that if a RESET* is asserted after UPDATE has transitioned from a high to low state, that RESET* stay low, at least 2 µs. To understand this precaution, notice in Figure 1 that UPDATE is delayed in order to enable individual DAC latches. If RESET* is not brought low for sufficient time, an individual DAC update will occur. By simply forcing the RESET* pulse low for a minimum of 2 µs, when a CK frequency of 50 MHz or less is used, the 6420 will clear properly to the known states shown above. To test an output, a DAC should be loaded as shown by timing in Figure 3. The clock should be stopped after the falling edge of CK24 after UPDATE is unasserted. At this point, the SCAN_OUT pin, which is an analog output, will reflect the voltage at the addressed DAC's output pin. Note that the scan output is switched off when the parallel load is selected (address 64). This prevents a parallel connection of all the DAC outputs when the scan feature is used. VOUT_CH0_1 VOUT_CH0_2 TEST_MODE VOUT_CH0_3 Address Decoder SCAN_OUT NOTE: When address 64 is invoked (parallel load), scan is disabled. Figure 5. Voltage Output Scan  2000 Semtech Corp. 13 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Circuit Description (continued) Current Outputs The TEST_MODE and SCAN_OUT pins on the Edge6420 are used in the same way as for voltage outputs. The scan circuits for current outputs are shown in Figure 6. The voltage measured at the SCAN_OUT pin, using the configuration in Figure 6, for Group E and F current outputs are as follows: VSCAN_OUT_E = (RSENSE_E + RPAD) * IOUT_E where: RSENSE_E = 400Ω ± 30% RPAD = 30Ω ± 30% and 2) VSCAN_OUT_F = (RSENSE_F + RPAD) * IOUT_F where: RSENSE_F = 400Ω ± 30% RPAD = 30Ω ± 30% 1) If TEST_MODE inputs are ganged together, SCAN_OUT cannot be ganged, or invalid results will be observed at the SCAN_OUT pin. Hence, each SCAN_OUT pin on a 6420 will have to be measured separately. If SCAN_OUT is ganged, TEST_MODE pins cannot be ganged together. The typical "ON" resistance of the FET switch is 100 kΩ, but can vary from 60 kΩ to 180 kΩ as a function of process and output voltage. Notes when Using SCAN Feature with Multiple Chips When multiple 6420s are used on a board, and it is desired to gang the SCAN_OUT pins of these 6420s, or gang the TEST_MODE inputs to one point, it is required for proper functioning that the following rules be followed: + IDAC R SENSE R PAD IOUT_CH0_0 CONNECT TO VIRTUAL GROUND – TEST_MODE IDAC + – R SENSE R PAD IOUT_CH0_1 CONNECT TO VIRTUAL GROUND ADDRESS DECODER + IDAC R SENSE R PAD IOUT_CH0_2 CONNECT TO VIRTUAL GROUND – SCAN_OUT NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED. Figure 6. Current Output Scan Circuits  2000 Semtech Corp. 14 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Application Information One application for the Edge6420 is to provide necessary DC voltages and currents for 4 channels of pin electronics (driver, receiver, load) and per pin measurement units. For example, using the: • Edge720 Load / Driver / Comparator • Edge4707 PPMU with the following specifications: Edge720 • • • • • • • –1.5 –1.5 –1.5 –1.5 –1.5 0< 0< < driver output high < +7.5V < driver output low < +7.5V < comparator threshold high < +7.5V < comparator threshold low < +7.5V < commutating voltage < 7.5V load source current < 24 mA load sink current < 24 mA Edge 4707 PPMU • • • –2.8 < PPMU (MI) compare high voltage < +2.8V –2.8 < PPMU (MI) compare low voltage < +2.8V –3.0 < PPMU (FV) < +14.0V Other • 0 < flash programming voltage (VHH) < +14V Table 8 demonstrates Edge6420 settings that can be used to fulfill the above requirements. Power Supplies (for this application): 15.25 ≤ AVCC ≤ 15.75V –4.75V ≤ VEE ≤ –4.25V 4.6V ≤ AVDD ≤ 5.25V 4.85 ≤ DVDD ≤ 5.15V AGND = 0, SGND = 0 Resulting Range Output Compliance Power on Reset Suggested (DAC Code) Application VIH VIL VOH VOL VCOM1 PPMU CH PPMU CL PPMU FV VHH VCM_IN ISC_IN ISK_IN RADJ FADJ IBIAS Channel 0 Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 – 31 32 – 47 48 – 63 Group Type # Bits Resolution Offset A V 13 1.10 mV –1.5V –1.5 / +7.5V ±100 µA 1000H (3V) B V 13 0.684 mV –2.8V –2.8 / 2.8V ±100 µA 1000H (0V) C V 13 2.07 mV –3.0V –3.0 / +14.0V ±100 µA 1000H (6V) D V 13 1.10 mV –1.5V –1.5 / +7.5V ±100 µA –.2 / 2.4V (Note 1) –.2 / 2.1V (Note 1) 1000H (3V) E I 13 159 nA N/A 0 to 1.3 mA 0000H (0 mA) F I 6 39 µA N/A 0 to 2.5 mA 1000H (1.0 mA) Same as above for Channel 1. Same as above for Channel 2. Same as above for Channel 3. Note 1: Max compliance depends on maximum current required. See specifications for limits. Table 8. Application Chart – Possible Chip Specification  2000 Semtech Corp. 15 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Application Information (continued) 0V +15.5V +5V –5V 0V +5V 0V + 2.5V – AGND SGND AVCC AVDD VEE AGND DVDD DGND VREF VOUT_CH0_0 VOUT_CH0_1 VOUT_CH0_2 DAC Voltage Outputs . . . . . . Loading Requirement: 10 nF to 100 nF Note: All unused voltage outputs must have an external capacitor attached (between 10 nF and 100 nF). VOUT_CH0_8 Edge6420 VOUT_CH0_9 VOUT_CH0_10 Loading Requirement: 10 nF to 100 nF IOUT_CH0_1 DAC Current Outputs . . . . . . Loading Requirement: 1 nF (see below) IOUT_CH0_4 IREF IREF IREF IREF IREF IREF IREF IREF IREF IREF_E IREF_F Loading Requirement: 1 nF (see below) R_OFFSET_D R_OFFSET_B R_OFFSET_C R_OFFSET_A R_MASTER R_GAIN_D R_GAIN_B R_GAIN_C R_GAIN_A R_GAIN_E AGND For Group A DACs Gain and Offset Control The Selection of R_MASTER Establishes IREF For Group B DACs Gain and Offset Control For Group C DACs Gain and Offset Control For Group D DACs Gain and Offset Control Figure 7. Required External Resistors and Components Loading Requirements Voltage Outputs All voltage outputs (denoted VOUT_CH[0:3]_[0:10]) require a load capacitance between 10 nF and 100 nF for stability. Current Outputs All current outputs require capacitive loading; the amount of loading needed to ensure stability is dependent on the impedance that the current outputs of the 6420 drive. For impedances of 1.3 KΩ to 1.6 KΩ, such as what is seen at the E720 current inputs (ISK, ISRC, IBIAS, RADJ, and FADJ), it is recommended that 1 nF be used.  2000 Semtech Corp. 16 Caution on Exceeding Compliance Limits on Current Output DACs Current output DACs (i.e., Group E and F DACs) can exhibit a “lock-up” condition in situations when the actual voltage seen at the outputs of these DACs exceeds the compliance limits in the specification. Care should be taken in the design of circuits being driven by Group E and F outputs to ensure compliance limits stated in the specifications are not exceeded. R_GAIN_F www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Application Information (continued) Temperature Coefficient Effect on DACs There is a gain and offset temperature coefficient that should be taken into account in the system design that will affect calibration and performance. The equation for voltage drift on output DACs is as follows: ∆VOUT_A,B,C,D = ∆T * TCOFFSET_A,B,C,D CODE * LSB * TCGAIN_A,B,C,D (%/˚C) Current outputs drift follow the following equation: ∆IOUT_E,F = ∆T * TCOFFSET_E,F CODE * LSB * TCGAIN_E,F (%/˚C) Average values for TCOFFSET and TCGAIN can be found in the specifications. Compliance of Current Output DACs (Groups E, F) The compliance of the current output DACs (Groups E and F) is governed by the following two equations: IOUT < 2.5 mA: VCOMPLIANCE = (–250 Ω * IOUT) + AVDD – 1.875V IOUT ≥ 2.5 mA: VCOMPLIANCE = (–600 Ω * IOUT) + AVDD – 1V µA ˚C + µV ˚C + Care should be taken to ensure that devices being driven by Group E and F DACs are designed to be within the compliance specification. 1 mA AVDD Compliance Exceeded 2 mA 3 mA IOUT AVDD – 1 (1.3 mA, AVDD – 2.2V) (2.5 mA, AVDD – 2.5V) AVDD – 2 AVDD – 3 (3.6 mA, AVDD – 3.2V) VCOMPLIANCE Figure 8. Compliance of Current Output DACs (Groups E and F) Caution Regarding Power Dissipation of the 6420 During Parallel Load: The Voltage DAC output amplifiers, for a FAST process, can: • Source up to 10 mA (8 mA @ TJ = 100˚C) • Sink up to 4.5 mA (3.5 mA @ TJ = 100˚C) Caution must be taken during a parallel load, particularly when the voltage DACs are loaded with a large filtering capacitor (10 to 100 nF). In this scenario, a large voltage change can induce a large current peak. For example, the currents calculated below can be induced in the VCC/ VEE supplies: • Source case: 44 DACs * 10 mA / DAC + 40 mA = 480 mA (or 400 mA @ TJ = 100˚C) in the VCC supply • Sink case: 44 DACs * 4.5 mA / DAC + 120 mA = 320 mA (or 280 mA @ TJ = 100˚C) in the VEE supply Therefore, the user must take care of extra power dissipation due to these currents peaks, and should avoid large voltage changes during a parallel load. See Figure 8 for a graphical depiction. Note: IOUT is current sourced from output of DAC.  2000 Semtech Corp. 17 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Package Information (continued) Edge6420BBG Package 0.10 –A– D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G Detail B –B– E2 E (E1) H J K L M N P R (D1) D2 BOTTOM VIEW TOP VIEW Detail A NX f f φ b MCAMBM MC φ0.15 φ0.075 4 e SIDE VIEW DETAIL B // ccc C c // bbb C –C– 6 SEATING PLANE 5 A2 A1 A DETAIL A aaa C DIMENSIONAL REFERENCES NOTE: The inner 9x9 balls are for improved thermal dissipation. They will be at the VEE potential, so board layout should ensure that these inner balls are connected to the VEE plane. REF A A1 A2 D1 MIN 0.96 0.21 0.50 NOM 1.06 0.26 0.55 11.20 BSC MAX 1.16 0.31 0.60 NOTES: 1. All dimensions are in millimeters. 2. ‘e’ represents the basic solder ball grid pitch. 3. “M” represents the basic solder ball matrix size, and symbol “N” is the number of balls after depopulating. 4. ‘b’ is measurable at the maximum solder ball dimaeter after reflow parallel to primary datum –C–. 5. Dimension ‘aaa’ is measured parallel to primary datum –C–. 6. Primary datum –C– and seating plane are defined by the spherical crowns of the solder balls. 7. Package surface shall be matte finish charmilles 24 to 27. 8. Package centering to substrate shall be 0.0780 mm maximum for both X and Y directions respectively. 9. Package warp shall be 0.050 mm maximum. 10. Substrate material base is BT resin. 11. The overall package thickness “A” already considers collapse balls. 12. Dimensioning and tolerancing per ASME Y14.5M 1994.  2000 Semtech Corp. 18 D2 E E1 E2 b c aaa bbb ccc e f M N 12.90 12.90 13.00 13.00 11.20 BSC 13.10 13.10 12.90 0.40 13.00 0.45 0.25 13.10 0.55 0.12 0.20 0.20 0.8 0.80 0.90 15 225 1.00 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Recommended Operating Conditions Parameter Positive Analog Power Supply Positive Analog Power Supply 2 Negative Power Supply Reference Voltage (Note 2) Supply Ground (Note 1) Total Analog Supply 1 Digital Power Supply Digital Ground (Note 1) Thermal Resistance of Package (6420BBG) (measured at top-center of package) Case Temperature (at top of package) Symbol AVCC AVDD VEE VREF SGND AVCC – VEE DVDD – DGND DGND θjc 3.00 –.25 –.25 Min +15.25 +4.6 –5.25 Typ +15.5 +5 –5 2.500 0 20.5 5.0 0 3 +.25 +23 5.50 +.25 Max +15.75 +5.25 –4.3 Units V V V V V V V V ˚C/W TCASE 40 80 ˚C All Power Supply voltages are referred to AGND, the reference signal ground, unless othewise specified. Note 1: Note 2: Not production tested. User should use a precision supply for VREF setting because the offset and gain of all DACs will change proportionately to a deviation from VREF = 2.500V. See Equations 1 and 5 to determine the extent of offset and gain change to deviations in VREF.  2000 Semtech Corp. 19 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Absolute Maximum Ratings Parameter Positive Analog Supply Positive Analog Supply 2 Negative Analog Supply Digital Power Supply Total Power Supply Symbol AVCC AVDD VEE DVDD – DGND AVCC – VEE AVCC – AVDD DGND SGND Min –.35 –.35 –5.5 –.35 –.35 –5.5 –.35 –.35 Max +20 +5.5 +.35 +5.5 +25 +20 +.35 +.35 Units V V V V V V V V Digital Input Voltages CE, CK, UPDATE, RESET*, SDI, TEST_MODE VREF, VMASTER, VOFFSET_[A:D], VGAIN_[E:F] VGAIN_[A:D] DGND – .35 DVDD + .35 V Analog Input Voltages AGND – .35 AVDD + .35 V AVEE – .35 –1 –1 AGND + .35 +1 +1 V mA mA Analog Input Currents Analog Output Voltages Groups A, B, C, D Groups E, F Analog Output Currents Groups A, B, C, D Continuous DC Current Output Voltage Compliance (Groups E, F) (Note 1) Minimum Time Required Between Successive Parallel Loads of all 64 DACs @ CLOAD = 100 nF, Full Scale Steps (Note 2) Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin) IGAIN_[E:F] IMASTER VOUT_[A:D] VOUT_[E:F] AVEE – .35 AGND – .35 AVCC + .35 AVDD + .35 V V IOUT_[A:D] –300 +300 3.3 µA V ms Tmin 2 TS TJ TSOL –65 +150 +125 +260 ˚C ˚C ˚C All Power Supply voltages are referred to AGND, the reference signal ground, unless othewise specified. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Note 1: Exceeding this limit may result in a monostable output state at maximum current. Note 2: Full scale step definition: 11.5V step for Group A, B, D DACs, 20V step for Group C, 3.6 mA steps for Groups E and F.  2000 Semtech Corp. 20 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE DC Characteristics Parameter Digital Inputs (SDI, CE, CK, UPDATE, RESET*, TEST_MODE) Input Low Voltage Input High Voltage Input Current Digital Outputs (SD0, CK_OUT) Output Low Voltage @ IOL = 1.6 mA Output High Voltage @ IOH = –0.4 mA DAC Outputs Groups A, B, D (Voltage Outputs) Resolution Max Output Voltage Range @ R_GAIN / R_MASTER = .4 @ R_GAIN / R_MASTER = 1 @ R_GAIN / R_MASTER = 1.15 Output Offset Range (DATA = 0000H) @ R_OFFSET / R_MASTER = 0.0 @ R_OFFSET / R_MASTER = 0.5 @ R_OFFSET / R_MASTER = 1.0 @ R_OFFSET / R_MASTER = 1.2 Output Current Compliance Headroom of Voltage Outputs (while maintaining current compliance limit) (Note 1) VOUT(max) to VCC VOUT(min) to VEE Integral Linearity Error with 9 Point Calibration (Note 2) Integral Linearity Error with 2 Point Calibration (Note 4) Differential Linearity Error Gain TempCo (Notes 3, 6) Offset TempCo (Notes 3, 6) @ R_OFFSET / R_MASTER = 0.0 @ R_OFFSET / R_MASTER = 0.5 @ R_OFFSET / R_MASTER = 1.0 @ R_OFFSET / R_MASTER = 1.2 TCGAIN_A,B,D TCOFFSET_A,B,D –288 –110 +145 +231 µV/˚C µV/˚C µV/˚C µV/˚C VOUT_RANGE 9.8 4 10 11.5 10.2 V V V 13 Bits Symbol Min Typ Max Units VIL VIH IIL, IIH VOL VOH .8 2.4 –1 1 .4 DVDD V V µA V V 2.4 VOFFSET –2.60 2.5 0 –2.5 –3.5 –2.35 V V V V µA –100 +100 AVCC – VOUT(max) VOUT(min) – VEE 1.25 1.00 –2.5 –15 –1 –.00285 2.5 15 1 V V LSB LSB LSB %/˚C  2000 Semtech Corp. 21 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE DC Characteristics (continued) Parameter Group C (Voltage Outputs) Resolution Max Output Voltage Range (DATA = IFFFH) @ R_GAIN / R_MASTER = .4 @ R_GAIN / R_MASTER = .6 @ R_GAIN / R_MASTER = .85 Output Offset Range (DATA = 0000H) @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER Output Current Compliance Headroom of Voltage Outputs – Group C (while maintaining current compliance limit) (Note 1) VOUT(max) to VCC VOUT(min) to VEE Integral Linearity Error with 9 Point Calibration (Note 2) Integral Linearity Error with 2 Point Calibration (Note 4) Differential Linearity Error Gain TempCo (Notes 3, 6) Offset TempCo (Notes 3, 6) @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER @ R_OFFSET / R_MASTER = = = = 0.0 0.5 1.1 1.2 TCGAIN_C TCOFFSET_C –250 –77 +240 +166 µV/˚C µV/˚C µV/˚C µV/˚C VOUT_RANGE 8 12 17 V V V Symbol Min Typ 13 Max Units Bits 16.75 17.22 VOFFSET = = = = 0.0 0.5 1.1 1.2 2.5 0 –3.0 –3.5 V V V V µA –3.10 –100 –2.9 +100 AVCC – VOUT(max) VOUT(min) – VEE 1.25 1.00 –3 –20 –1 –.0012 3 20 1 V V LSB LSB LSB %/˚C  2000 Semtech Corp. 22 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE DC Characteristics (continued) Parameter Group E (Current Outputs) Resolution Symbol Min Typ 13 Max Units Bits Max Output Current Range @ R_GAIN_E = 55 kΩ @ R_GAIN_E = 62.5 kΩ @ R_GAIN_E = 156 kΩ Output Voltage Compliance (Notes 1, 6) @ 1.3 mA @ 2.5 mA @ 3.2 mA @ 3.6 mA Integral Linearity Error with 9 point Calibration (Note 2) Integral Linearity Error with 2 point Calibration (Note 4) Differential Linearity Error Current Offset Gain TempCo (Notes 3, 6) Offset TempCo (Notes 3, 6) Group F (Current Outputs) Resolution Max Output Current Range @ R_GAIN_F = 55 KΩ @ R_GAIN_F = 62.5 KΩ @ R_GAIN_F = 156 KΩ Output Voltage Compliance (Notes 1, 6) @ 1.3 mA @ 2.5 mA @ 3.15 mA @ 3.6 mA Integral Linearity Error with 2 Point Calibration (Note 5) Differential Linearity Error Current Offset Gain TempCo (Notes 3, 6) Offset TempCo (Notes 3, 6) IOUT 3.09 3.6 3.2 1.28 3.35 mA mA mA –0.20 –0.20 –0.20 –0.20 –2 –15 –1 (–128 * LSB) – 20 TCGAIN_E TCOFFSET_E –128 * LSB –.0021 ±100 6 IOUT 3.09 3.54 3.15 1.26 AVDD AVDD AVDD AVDD – – – – 2 2.20 2.50 2.92 3.20 V V V V LSB LSB LSB µA %/˚C nA/˚C Bits 15 1 (–128 * LSB) + 20 3.35 mA mA mA – 0.20 – 0.20 – 0.20 –0.20 –0.25 –1 –20 TCGAIN_F TCOFFSET_F 0 –.0057 ±23 AVDD AVDD AVDD AVDD – – – – 2.20 2.50 2.89 3.20 V V V V LSB LSB µA %/˚C nA/˚C 0.25 1 20  2000 Semtech Corp. 23 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE DC Characteristics (continued) Power Supplies Parameter Power Supply Consumption Positive Analog Supply 1 (Note 6) Positive Analog Supply 2 (Note 6) Digital Supply (Note 6) Negative Power Supply 1 (Note 6) Reference Supply Power Supply Rejection Ratio (Note 1) 5 MHz 1 MHz 100 KHz Power Supply – DC Sensitivity (Note 1) Symbol ICC IADD IDDD IEE IREF PSRR 65 45 50 ∆VOUT/ ∆AVDD 40 dB dB dB dB Min Typ 20.5 60 2 –73 0.2 Max 41.5 132 10 1.4 Units mA mA mA mA mA –118 All specifications are guaranteed over Recommended Operating Conditions unless otherwise noted. DC Test Conditions (unless otherwise specified): VREF = 2.50V. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Not production tested. Guaranteed by bench characterization. The 9 calibration points recommended are: DATA values of 0000H, 03FFH, 07FFH, 0BFFH, OFFFH, 13FFH, 17FFH, 1BFFH, 1FFFH. Assuming R_MASTER = 100 KΩ, stable VREF, nominal external resistor values, and stable supply voltage values. Calibration points are: Data values of 0000H and 1FFFH. Calibration points are: Data values of OOOOH and OO3FH. See “Applications Information” for further information.  2000 Semtech Corp. 24 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE AC Characteristics Parameter Digital Inputs Set Up Times (Note 1) SDI to Rising CK CE (rising edge) to Rising CK24 UPDATE (rising edge) to Rising CK24 (Notes 2, 3) Hold Times (Note 1) SDI to Rising CK CE (falling edge) to Rising CK24 UPDATE (falling edge) to Rising CK24 (Notes 2, 3) CK Fmax at DVDD = 3.3V ± .30V (Notes 1,5) 30 to 50% Duty Cycle (Note 5) 70% Duty Cycle Fmax at DVDD = 5.0V ± .50 (Notes 4,5) 30 to 50% Duty Cycle 70% Duty Cycle Duty Cycle (Note 1) RESET Pulse Width Output Voltage Settling Time (Note 1) (from CK Ø corresponding to UPDATE) Full Scale Step, 10V (to 0.025% FSR) for Groups A, B, D Load: 10 nF Load: 100 nF Full Scale Step, 17V (to 0.025% FSR) for Group C Load: 10 nF Load: 100 nF Output Current Settling Time Group E (to .025%) Load: 1 nF Load: 10 nF Group F (to .8%) Load: 1 nF Load: 10 nF Fmx a 33 20 Fmx a 55 35 30 2 50 70 MHz MHz MHz MHz % µs Symbol Min Typ Max Units TS _ D US I TS _ E UC TS _ P T UU D 10 10 5 70% of TC K ns ns ns THDS I L _D THDC L _E THDU D L_PT 10 10 5 70% of TC K ns ns ns PWC K PWR S T EE Ts 30 250 70 700 µs µs 50 0.410 150 1 µs ms 53 230 4.4 29 100 500 10 50 µs µs µs µs Test conditions (unless otherwise specified): "Recommended Operating Conditions". Note 1: Note 2: Note 3: Not production tested. Guaranteed by design and characterization. The max spec of 70% of TCK is not production tested. CK24 refers to 24th rising clock edge, which corresponds to a full shift register. Note that a falling CK24 edge is also required for proper operation of circuit. The 6420 is production tested at 55 MHz only, with 50% duty cycle. Duty cycle % shown refers to “high” duration of clock in a period. CE TSU_CE TCK THLD_CE Note: A 24th falling CK edge is required for DAC updating! CK ª CK1 CK24 UPDATE TSU_UPDATE THLD_UPDATE Figure 9. Central and Individual DAC Updating SDI Valid Data A0 TSU_SDI ªª TSU_SDI Note 4: Note 5: Valid Data D15 CK ª THLD_SDI THLD_SDI CK1 CK24 Figure 8. Shift Register Loading Timing Diagram  2000 Semtech Corp. 25 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Ordering Information Model Number E6420BBG Package 225 Ball, 13 mm x 13 mm BGA 6420EVM Edge6420 Evaluation Board Contact Information Semtech Corporation High-Performance Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633  2000 Semtech Corp. 26 www .semtech.com Edge6420 HIGH-PERFORMANCE PRODUCTS – ATE Revision History Current Revision: April 29, 2002 Previous Revision: September 25, 2001 Page # all 1 3, 4, 5 10 17 21 Section Name All Description Pin Descriptions Address Map Package Infromation DC Characteristics Groups A, B, D Integral Linearity Error with 9 Point Calibration Max: ±2 Integral Linearity Error with 2 Point Calibration Max: ±15 Differential Linearity Error Max: