Triple Low Dropout Regulator Controllers
POWER MANAGEMENT Description
The SC1112 was designed for the latest high speed motherboards. It includes three low dropout regulator controllers. The controllers provide the power for the system AGTL bus Termination Voltage, Chipset, and clock circuitry. An adjustable controller with a 1.2V reference is available, while two selectable outputs are provided for the VTT (1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A) and the AGP (1.5V or 3.3V). The SC1112 low dropout regulators are designed to track the 3.3V power supply as the VTTIN supply is cycled On and Off. A latched short circuit protection is also available for the VTT output. Other features include an integrated charge pump that provides adequate gate drives for the external MOSFETs, and a capacitive programable delay for the power good signal.
SC1112
Features
Triple linear controllers Selectable and adjustable output voltages LDOs track input voltage within 200mV (Function of the MOSFETs used) until regulation Integrated charge pump Programmable power good delay signal Latched over current protection (VTT) Pb-free package available, fully WEEE and RoHS compliant
Applications
Pentium® III Motherboards Triple power supplies
Typical Application Circuit
+3.3V VTT 1K R1 C6 330u POWER GOOD Q2 SC1112/A
5VSTBY ADJGATE GND AGPGATE AGPSEN VTTGATE VTTSEN AGPSEL VTTSEL VTTIN
+5V STBY
C1 10u C3 0.1u Q3 C14 330u AGP Q1 C2 C18 330u C16 330u C17 0.1u VTT C19 330u C8 330u C9 0.1u
ADJ RA
0.1u
ADJSEN
C11
CAPCAP+
1u
C10
FC DELAY
C13 0.1u
C12 330u
RB
22n C5
PWRGD
VTT SELECT Signal
AGP SELECT Signal
Revision: August 30, 2006
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SC1112
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter 5VSTBY to GND VTTSEN to GND AGPSEN to GND ADJSEN to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. Thermal Resistance Junction to Ambient SOIC TSSOP Thermal Impedance Junction to Case SOIC TSSOP ESD Rating (Human Body Model)
Symbol
Maximum -0.3 to +7 -0.3 to 5 -0.3 to 5 -0.3 to 5
Units V V V V °C °C °C °C °C/W
TA TJ TSTG TL θJ A
0 to +70 0 to +125 -65 to +150 300 130 115 30 38 2
θJ C ESD
°C/W kV
Electrical Characteristics
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C
Parameter Supply (5VSTBY) Supply Voltage Supply Current VTT Short Circuit Protection VTT Short Circuit Delay Timer Threshold(4) VTT Short Circuit Delay Time(4) VTT Short Circuit Delay Source Current(4) VTT Short Circuit Threshold(4) VTT Pow er Good PWRGD Delay Timer Threshold(5) PWRGD Threashold(5) PWRGD Threashold
(5)
Symbol
Conditions
Min
Typ
Max
Units
5VSTBY I5VSTBY SCTh SCtd ISC VTTSCTh PGDelay_TH PGTH_1.2 PGTH_1.5 PGtd_1.2 PGtd_1.5
(5)
4.75 5VSTBY = 5V 6
5 8 1.5 (Cdelay*SCTH)/ISC
5.25 12
V mA V S
16 650 1.450 1.060 1.330
22 700 1.500 1.085 1.350 (Cdelay*PGTH_1.2)/IPG (Cdelay*PGTH_1.5)/IPG
28 750 1.550 1.110 1.390
µA mV V V V S S
PWRGD Delay Time(5) PWRGD Delay Time Linear Sections VTT Input Supply Threshold Tracking Difference
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PWRGD Source Current
IPG VTTINTH DeltaTRACK VIN = 3.30V, IO = 0A
2
16
22
28
µA
1.45
1.52 200
1.55
V mV
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SC1112
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C
Parameter Linear Sections (Cont.) Output Voltage VTT
Symbol
Conditions
Min
Typ
Max
Units
(SC1112A) VTT1.2 (SC1112) VTT1.25 VTT1.5
IO = 0 to 2A, VTTSEL = LOW IO = 0 to 2A, VTTSEL = LOW IO = 0 to 2A, VTTSEL = HIGH IO = 0 to 2A, AGPSEL = LOW IO = 0 to 2A, AGPSEL = HIGH IO = 0 to 2A
1.176 1.225 1.470 1.470 3.234 -2% 90
1.200 1.250 1.500 1.500 3.300 1.2*(1+RA/RB) 120 1
1.224 1.275 1.530 1.530
V
V V V
Output Voltage AGP
AGP1.5 AGP3.3
Output Voltage ADJ VTTSEN Bias Current (SC1112) VTTSEN Bias Current (SC1112A) AGPSEN Bias Current ADJSEN Bias Current VTT Gate Current
AD J IbiasVTTSEN IbiasVTTSEN IbiasAGPSEN IbiasADJSEN IsourceVTTgate IsinkVTTgate
+2% 140 5 170 5
V µA µA µA µA µA µA µA µA µA µA % % dB
110
150 1
5VSTBY = 4.75V, Vgate = 3.0V
500 500
AGP Gate Current
IsourceAGPgate IsinkAGPgate
5VSTBY = 4.75V, Vgate = 3.0V
500 500
ADJ Gate Current
IsourceADJgate IsinkADJgate
5VSTBY = 4.75V, Vgate = 3.0V
500 500
Load Regulation Line Regulation Gain (AOL)(2)
LOADREG LINEREG GAINLDO
VTTIN = 3.30V, IO = 0 to 2A VTTIN = 3.13V to 3.47V, Io = 2A LDOS Output to GATE
0.3 0.3 50
Notes:
(1) All electrical characteristics are for the application circuit on page 19. (2) Guaranteed by design (3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions. (4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled. (5) PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.2 or PGtd1.5 level. At that time the PWRGD source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground. 2006 Semtech Corp. 3 www.semtech.com
SC1112
POWER MANAGEMENT Timing Diagrams
NORMAL STARTUP CONDITION
VTTIN
VTTIN=1.5V
VTT
The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is above the powergood threshold of 1.08V. Once DELAY reaches 1.5V, the PWRGD signal goes high. VTTGATE initially turns on hard, until VTT reaches regulation. Then VTTGATE drops to its normal regulating level.
DELAY
DELAY=1.5V
PWRGD
VTTGATE
SHORT-CIRCUIT STARTUP
VTTIN
VTTIN=1.5V
VTT
The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is below the short circuit threshold of 0.7V. VTTGATE initially turns on hard and is latched off when DELAY DELAY reaches 1.5V and VTT is below 0.7V
DELAY=1.5V
PWRGD
VTTGATE
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SC1112
POWER MANAGEMENT Timing Diagrams (Cont.)
SHORT-CIRCUIT DURING NORMAL OPERATION
VTTIN
VTT
Once VTT drops out of regulation, VTTGATE turns on harder to try and raise VTT. When VTT drops below 1.08V, the delay capacitor is discharged and PWRGD goes low. When VTT drops below 0.7V, the delay capacitor begins charging. If VTT is still below 0.7V when DELAY reaches 1.5V, VTTGATE is latched off. VTT=1.08V VTT=0.7V
DELAY
DELAY=1.5V
PWRGD
VTTGATE
SHORT-CIRCUIT AND RECOVERY DURING NORMAL OPERATION
VTTIN
Once VTT drops out of regulation, VTTGATE turns on harder to try and raise VTT. When VTT drops below 1.08V, the delay capacitor is discharged and PWRGD goes low. When VTT drops below 0.7V, the delay capacitor begins charging. If VTT recovers above 0.7V before DELAY reaches 1.5V, DELAY is again discharged. If VTT reaches 1.08V the delay capacitor begins charging and normal operation continues.
VTT
VTT=1.08V VTT=0.7V VTT=1.08V
DELAY
DELAY=1.5V
PWRGD
VTTGATE
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SC1112
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number (1)(2) P ackag e Temp Range (TJ)
5VSTBY PWRGD DELAY VTTSEL AGPSEL ADJGATE ADJSEN CAP-
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GND VTTIN VTTGATE VTTSEN AGPGATE AGPSEN FC CAP+
SC1112STR SC1112STRT(3) SC1112ASTR SC1112TSTR SC1112TSTRT(3) SC1112ATSTR SC1112EVB Evaluation Board TSSOP-16 0° to 125°C SO-16 0° to 125°C
(16-Pin SOIC or TSSOP)
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Part Number (SO-16): SC1112STR and SC1112STRT = 1.25V and SC1112ASTR = 1.2V. Part Number (TSSOP-16): SC1112TSTR = 1.25V and SC1112ATSTR = 1.2V. (3) Pb-free product. This product is fully WEEE and RoHS compliant.
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SC1112
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name 5VSTBY PWRGD DELAY VTTSEL AGPSEL ADJGATE A D JS E N C APC AP+ FC AGPSEN AGPGATE VTTSEN VTTGATE VTTIN GND Pin Function 5V Standby input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. Open collector Power Good Flag for VTT output. A capacitor from this pin to GND will program the delay for the Power Good Flag of VTT output and the glitch immunity time. TTL signal that programs the VTT output voltage: VTTSEL = LOW, VTT = 1.2XV VTTSEL = HIGH, VTT = 1.5V TTL signal that programs the AGP output voltage: AGPSEL = LOW, AGP = 1.5V AGPSEL = HIGH, AGP = 3.3V Gate drive output for AGP. Sense input for ADJ. Negative connection to boost capacitor. Positive connection to boost capacitor. Filter capacitor for the internal charge pump should be connected from this pin to GND. Sense input for AGP. Gate drive output for AGP. Sense input for VTT. Gate drive output for VTT. Short circuit sense line connected to the 3.3Vin. Ground.
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1112
POWER MANAGEMENT Block Diagram
5VSTBY VTTSEL
FC 1.5V Bandgap Reference
+ -
1.5V + _ + _ Vref Disable1.5 1.2V + _ Disable1.2 + _
1.35V 1.2V 1.08V 0.7V
VTTGATE VTTSEN
VTTIN
S R
Q
DELAY
_ + + _ Vref + _ 0.7V + _ VTTSEN ChargePump Oscillator Disable3.3 Disable1.5 1.5V 1.5V + _
FC
AGPGATE AGPSEN
FC
PWRGD
+ _ Pwrgd Threshold 1.2V + _
ADJGATE ADJSEN
GND
AGPSEL
CAP+ CAP-
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SC1112
POWER MANAGEMENT Typical Characteristics
VTT(1.5V) Output Voltage @ Io = 0A vs Ta
1.5055
1.5035
VTT(1.5V) Output Voltage @ Io = 2A vs Ta
1.5030
1.5050
1.5045
1.5025
1.5040 VTT1.5(V)
VTT 1.5 (V)
1.5020
1.5035
1.5015
1.5030
1.5010
1.5025
1.5020
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.5005
5V S tby = 5.25V 5V S tby = 5.00V 5V S tby = 4.75V
1.5000
1.5015 0 10 20 30 40 50 60 70
1.4995 0 10 20 30 40 50 60 70
Ta (°C.)
T a (°C .)
VTT(1.25V) Output Voltage @ Io = 0A vs Ta
1.2485 1.2465
VTT(1.5V) Output Voltage @ Io = 2A vs Ta
1.2460
1.2480
1.2475
1.2455
1.2470 VTT 1.2(V) VTT1.2(V)
1.2450
1.2465
1.2445
1.2460
1.2440
1.2455
1.2450
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.2435
1.2430
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.2445 0 10 20 30 40 50 60 70
1.2425 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
VTT Input Supply Threshold vs Ta
1.498 116
VTT Sense Bias current vs Ta
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.497
114
1.496 112 1.495
Ibias VTTSEN (uA)
5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 0 10 20 30 40 50 60 70
VTTINTH(V)
110
1.494
108 1.493
1.492
106
1.491
104 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Characteristics (Cont.)
VTT Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta
800 Source current 750 Sink current 23.40 23.60
VTT Short circuit Delay source current vs Ta
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
23.20 700 23.00 650 IVTT_Gate(uA) ISC(uA) 0 10 20 30 40 50 60 70
22.80
600
22.60
550
22.40
22.20 500 22.00 450
21.80
400
21.60 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
VTT Short circuit Delay Time (Cdelay = 0.1uF) vs Ta
8.40 8.30
8.20
SCtd(mS)
8.10
8.00
7.90
5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V
7.80
7.70 0 10 20 30 40 50 60 70
Ta (°C.)
VTT Short circuit Delay Timer Threshold vs Ta
1.515 1.510
1.505 1.500
1.495 SCth(V)
1.490
1.485
1.480
1.475
1.470
5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V
1.465 0 10 20 30 40 50 60 70
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Characteristics (Cont.)
VTT (1.25V) Power Good Threshold vs Ta
1.098 8.40 1.096 8.30 1.094 8.20 1.092
VTT (1.25V) Power Good Delay Time vs Ta
PG TH_1.25(V)
1.090
1.088
PG td_1.25(mS)
8.10
8.00
1.086 7.90 1.084
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V
1.082
7.80
1.080 0 10 20 30 40 50 60 70
7.70 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
VTT (1.5V) Power Good Threshold vs Ta
1.361 1.360 8.30 1.359 1.358 1.357 1.356 1.355 1.354 1.353 1.352 1.351 1.350 0 10 20 30 40 50 60 70 7.90 PGtd_1.5(mS) PGTH_1.5 (V) 8.10 8.40
VTT (1.5V) Power Good Delay Time vs Ta
8.20
8.00
5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
7.80
7.70 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
VTT Power Good Source current vs Ta
23.60 23.40 23.20 23.00 22.80 22.60 22.40 22.20 22.00 21.80 21.60 21.40 0 10 20 30 40 50 60 70 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
IPG(uA)
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Characteristics (Cont.)
AGP (1.5V) Output Voltage @ Io = 0A vs Ta
1.5055
AGP (1.5V) Output Voltage @ Io = 2A vs Ta
1.5035 1.5030 1.5025 1.5020 1.5015 AGP1.5(V) 1.5010 1.5005 1.5000 1.4995 1.4990 1.4985
1.5050
1.5045 1.5040
1.5035 AGP1.5 (V)
1.5030
1.5025
1.5020 1.5015
1.5010
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.5005 0 10 20 30 40 50 60 70
0
10
20
30
40
50
60
70
Ta (°C.)
Ta (°C.)
AGP (3.3V) Output Voltage @ Io = 0A vs Ta
3.2900
AGP (3.3V) Output Voltage @ Io = 2A vs Ta
3.2900
3.2890
3.2890
3.2880
3.2880
3.2870 AGP3.3 (V)
3.2870 AGP3.3(V)
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
3.2860
3.2860
3.2850
3.2850
3.2840
3.2840
3.2830
3.2830
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
3.2820 0 10 20 30 40 50 60 70
3.2820 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
AGP Sense Bias current vs Ta
142 5V Stby = 5.25V 5V Stby = 5.00V 140 5V Stby = 4.75V
AGP Gate Current @ Vgate = 3V, 5V Stby = 4.75 vs Ta
900 Sink current Source current 850
138 800
IbiasAGPSEN (uA)
IAGP_Gate(uA) 0 10 20 30 40 50 60 70
136
750
134
700 132
130
650
128
600 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Characteristics (Cont.)
ADJ (1.2V) Output Voltage @ Io = 0A vs Ta
1.2020 1.1955 1.1950
ADJ (1.2V) Output Voltage @ Io = 2A vs Ta
1.2010
1.2000
1.1945
1.1940 ADJ1.2(V) 1.1990 ADJ1.2(V) 5V Stby = 5.25V 5V Stby = 5.00V 1.1960 5V Stby = 4.75V 1.1920 1.1935
1.1980
1.1930 1.1970
1.1925
5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.1950 0 10 20 30 40 50 60 70
1.1915 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
ADJ Sense Bias current vs Ta
350 330 310 290 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V
ADJ Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta
900 Sink current Source current 850
800
IbiasADJSEN (uA)
270 250 230 210 190 650 170 150 0 10 20 30 40 50 60 70 700 IADJ_Gate(uA)
750
600 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Characteristics (Cont.)
I 5V Stby vs Ta
7.50 7.30 7.10 1.50 6.90 Output Select Threshold (V) 6.70 6.50 6.30 6.10 5.90 5.70 5.50 0 10 20 30 40 50 60 70 1.45 1.60 VTTSEL 1.55 AGPSEL
Output Select Threshold vs Ta
I5vstby (mA)
1.40
1.35
1.30 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V
1.25
1.20 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
Line Regulation VTTIN = 3.13V to 3.47V Io = 2A vs Ta
160.0E-3
Load Regulation VTTIN = 3.3V Io = 0 to 2A vs Ta
180.0E-3
140.0E-3
170.0E-3
120.0E-3
160.0E-3
Line Regulation(%)
Load Regulation(%)
100.0E-3
150.0E-3
80.0E-3
140.0E-3
60.0E-3
130.0E-3
40.0E-3
120.0E-3 VTT 1.25V AGP 1.25V 110.0E-3
VTT 1.25V AGP 1.25V
20.0E-3
000.0E+0 0 10 20 30 40 50 60 70
100.0E-3 0 10 20 30 40 50 60 70
Ta (°C.)
Ta (°C.)
Charge Pump Output Voltage vs Ta
9.32 V Charge Pump 9.31 9.30 9.29 Charge Pump Frequency (kHz) 365 9.28 9.27 9.26 9.25 9.24 9.23 9.22 9.21 0 10 20 30 40 50 60 70 345 0 10 350 370 375
Charge Pump Frequency vs Ta
Charge Pump Frequency
V Charge Pump(V)
360
355
20
30
40
50
60
70
Ta (°C.)
Ta (°C.)
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SC1112
POWER MANAGEMENT Typical Gain & Phase Margin
SC1112 Gain / Phase VTT = 1.25V @ 2A
60 Gain Phase (deg) 200 180 160 140 30 Phase (deg) 60 Gain Phase (deg)
SC1112 Gain / Phase VTT = 1.5V @ 2A
200 180 160 140 120 100 10 80 0 60 40 20 0 1000000
50
50
40
Gain
40
Gain
30
Gain (dB)
100 10 80 0 60 40 20 0 1000000
-10
Gain (dB)
20
20
-10
-20
-20
-30 10 100 1000 Freq (Hz) 10000 100000
-30 10 100 1000 Freq (Hz) 10000 100000
SC1112 Gain / Phase ADJ = 1.2V @ 2A
50 Gain Phase (deg) 40 200 180 40 160 140 20 Gain (dB) 120 100 80 60 -10 40 -20 20 0 1000000 -10 30 50
SC1112 Gain / Phase AGP = 1.5V @ 2A
200 Gain Phase (deg) 180 160 140 120 100 10 80 60 40 20 -20 10 100 1000 Freq (Hz) 10000 100000 0 1000000
Gain
Gain
30
Phase (deg)
10
0
0
-30 10 100 1000 Freq (Hz) 10000 100000
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Phase (deg)
Gain (dB)
Phase
20
Phase
Phase (deg)
Phase
120
Phase
SC1112
POWER MANAGEMENT Applications Infomation
Theory Of Operation The SC1112 was designed for the latest high speed mother boards requiring a controlled power up sequencing of the Outputs, and a programmable delay for the Power good signal. Three Linear controllers have been incorporated into the SC1112. The VTT output can be programmed to either a 1.250V or a 1.500V by applying a LOW or a HIGH control signal to the VTTSEL pin. AGP output can also be programmed via AGPSEL pin to a 1.50V or a 3.30V. The SC1112 also provides an Adjustable output which utilizes a resistive voltage divider. The +5VSTBY supply will power the internal Reference, Charge Pump, Oscillator, and the Fet controllers. After the +5VSTBY has been established, LDO outputs will track the VTTIN (3.30V) supply as it is applied. An external capacitor connected to the Delay pin will program the VTT short circuit delay time (SCtd), and the PWRGD delay time (PGtd). During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled. PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.25 or PGtd1.5 level. At that time the PWRGD source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground. A detailed timing diagram is shown on pages 4 to 5. Also included is an overcurrent protection circuit that monitors the VTT voltage. If the output voltage drops below 700mV, as would occur during an overcurrent or short condition, the device will pull the drive pin low and latch off the output. Fixed Output Voltage Options (VTT, AGP) Please refer to the Application Circuit on Page 1. The VTT and the AGP fixed output voltage can be programed from a Control logic signal. Table below shows the possible voltages:
VTTSEL 0 0 1 1 AGPSEL 0 1 0 1 VTT 1.25V 1.25V 1.50V 1.50V AGP 1.50V 3.30V 1.50V 3.30V
Once the VTTSEL or the AGPSEL signal is established, an internal resistive divider is used to compare the bandgap reference voltage with the feedback output voltage. The drive pin voltage is then adjusted to maintain the output voltage set by the internal resistor divider. Referring to the block diagram on page 8. It is possible to adjust the output voltage of the VTT or AGP, by applying an external resistor divider to the sense pin (please refer to Figure 1 on Page 17). Since the sense pin sinks a nominal 100µA, the resistor values should be selected to allow 10mA to flow through the divider. This will ensure that variations in this current do not adversely affect output voltage regulation. Thus a target value for R2 (maximum) can be calculated:
R2 ≤ V OUT ( FIXED ) 10 mA Ω
The output voltage can only be adjusted upwards from the fixed output voltage, and can be calculated using the following equation:
VOUT ( ADJUSTED
)
R1 = VOUT ( FIXED ) • 1 + + R1 • 100 µ A R2
Volts
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SC1112
POWER MANAGEMENT Applications Infomation (Cont.)
+3.3V +5V STBY
C1 10u SC1112
5VSTBY ADJGATE ADJSEN CAPCAP+ FC DELAY PWRGD GND AGPGATE AGPSEN VTTGATE VTTSEN AGPSEL VTTSEL VTTIN
C3 0.1u Q3 C14 330u AGP Q1 C2 C18 330u C16 330u C17 0.1u VTT C19 330u C8 330u C9 0.1u R1
VTT SELECT Signal
AGP SELECT Signal R2
Figure 1: Adjusting The Output Voltage of VTT or AGP Adjustable Output Voltage Option The adjustable output voltage option does not have an internal resistor divider. The adjust pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistors (please refer to Figure 2). In this case, the adjust pin sources a nominal 0.5µA, so the resistor values should be selected to allow 50µA to flow through the divider. Again, a target value for RB (maximum) can be calculated:
1 .200 V RB ≤ 50 µ A Ω
C6 330u Q2
VTT 1K R1 POWER GOOD
5VSTBY ADJGATE
SC11
The output voltage can be calculated as follows:
VOUT RA = 1 .200 • 1 + − 0.5µA • RA RB
C13 0.1u C12 330u
0.1u RA 1u
ADJSEN
C11
CAPCAP+
C10
FC DELAY
RB
22n
C5
PWRGD
The maximum output voltage that can be obtained from the adjustable option is determined by the input supply voltage and the RDS(ON) and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and a worst-case drive voltage of 9V, VOUT(MAX) is given by:
Figure 2
VOUT(MAX) = VTTIN(MIN) − IOUT(MAX) • RDS(ON)(MAX )
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SC1112
POWER MANAGEMENT Applications Infomation (Cont.)
Short Circuit Protection The VTT short circuit protection feature of the SC1112 is implemented by using the RDS(ON) of the MOSFET. As the output current increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, as the RDS(ON) limit is reached, the MOSFET will be unable to turn on any further, and the output voltage will start to fall. When the VTT output voltage falls to approximately 700mV, the LDO controller is latched off, setting output voltage to 0V. Power must be cycled to reset the latch. To prevent false latching due to capacitor inrush currents or low supply rails, the current limit latch is initially disabled. It is enabled once the short circuit delay time has elapsed. Timing diagram on pages 4 to 5 will show a detailed operation of the Short Circuit protection circuitry. To be most effective, the MOSFET RDS(ON) should not be selected artificially low. The MOSFET should be chosen so that at maximum required current, it is almost fully turned on. If, for example, a supply of 1.5V at 4A is required from a 3.3V ± 5% rail, the maximum allowable RDS(ON) would be:
R DS ( ON )( MAX ) =
Layout Guidelines One of the advantages of using the SC1112 to drive an external MOSFET is that the bandgap reference and control circuitry do not need to be located right next to the power device, thus a very accurate output voltage can be obtained since heating effects will be minimal. The 0.1µF bypass capacitor should be located close to the +5VSTBY supply pin, and connected directly to the ground plane. The ground pin of the device should also be connected directly to the ground plane. The sense or adjust pin does not need to be close to the output voltage plane, but should be routed to avoid noisy traces if at all possible. Power dissipation within the device is practically negligible, requiring no special consideration during layout.
(0 . 95 • 3 . 3 − 1 . 5 • 1 . 025 ) ≈
4
400 m Ω
To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown. Capacitor Selection Output Capacitors: Low ESR aluminum electrolytic or tantalum capacitors are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: P lacement of low ESR aluminum electrolytic or tantalum capacitors at the input to the MOSFET (VTTIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. The +5VSTBY supply should be bypassed with a 10µF ceramic capacitor.
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SC1112
POWER MANAGEMENT Evaluation Board Gerbers
Board Layout Assembly Top
Board Layout Assembly Bottom
Board Layout Top
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Board Layout Bottom
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+5VSTBY J1 +5VSTBY C1 10uF J2 +3.3V J3 J4 J5 J7 16 15 14 13 12 11 10 9 1uF C10 C9 0.1uF + C8 330uF + C19 330uF Q1 IRFR120N VTT C3 0.1uF C4 0.1uF + C2 + C18 330uF 330uF GND +3.3V +3.3V GND GND VTT POWER GOOD J6 1 5VSTBY PWRGD DELAY VTTSEL AGPSEL ADJGATE ADJSEN CAPCAP+ FC AGPSEN AGPGATE VTTSEN VTTGATE VTTIN GND 2 C5 3 4 5 6 7
**
POWER MANAGEMENT Evaluation Board Schematic
R1 1k U1 SC1112CS
22nF
C6 + 330uF R2 100k Q2 IRFR120N R3 100k
C7 0.1uF
J8 J9
VTT VTT J10 GND J12 GND
ADJ 8 VTT SELECT Signal J14 AGP SELECT Signal J15
**
J11
ADJ
20
RA C13 0.1uF C11 0.1uF RB
*
ADJ
J13
C12 + ** ADJ = 1.2*(1+RA/RB) 330uF
C15 0.1uF Q3 IRFR120N
+ C14 330uF
GND JP1
* JP1 = OPEN, VTT = 1.5 V * JP1 = SHORT, VTT = 1.25 V * JP2 = OPEN, AGP = 3.3 V * JP2 = SHORT, AGP = 1.5 V
J16 11 JP2
*
GND 22
J17
AGP C17 0.1uF + C16 330uF
J18 J19
AGP AGP J20 GND J21 GND
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SC1112
SC1112
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Qty. 1 8 8 1 1 2 1 9 2 1 2 2 1 1 2 3 3 2 1 Reference C1 C2,C6,C8,C12,C14,C16,C18,C19 C3,C4,C7,C9,C11,C13,C15,C17 C5 C 10 JP1,JP2 J1 J2,J5,J7,J10,J12,J16,J17,J20,J21 J3,J4 J6 J8,J9 J11,J12 J1 4 J1 5 J18,J19 Q1,Q2,Q3 R1,RA,RB R2,R3 U1 10uF 330uF 0.1uF 22nF 1uF TP2 +5VSTBY GND +3.3V Power Good VTT AD J VTT SELECT Signal AGP SELECT Signal AGP IRFR120N 1k 100k SC1112STRT Part 1206 CPCYL/D.2.75/LS.100/.031 0805 0805 0805 VIA/2P E D 5052 E D 5052 E D 5052 E D 5052 E D 5052 E D 5052 E D 5052 E D 5052 E D 5052 DPAKFET 0805 0805 SO-16 Foot Print
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SC1112
POWER MANAGEMENT Outline Drawing - TSSOP-16
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 E D
DIMENSIONS MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc .047 .002 .006 .031 .042 .007 .012 .003 .007 .192 .196 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 16 0° 8° .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 16 0° 8° 0.10 0.10 0.20
e/2 B D A2 A
aaa C SEATING PLANE
C bxN
A1 bbb C A-B D GAGE PLANE 0.25
H c L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB.
Land Pattern - TSSOP-16
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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SC1112
POWER MANAGEMENT Outline Drawing - SO-16
A N 2X E/2 E1 E e D
DIM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .010 .004 .065 .049 .020 .012 .007 .010 .386 .390 .394 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 16 0° 8° .004 .010 .008
ccc C
2X N/2 TIPS
1
2
3 e/2 B D
1.75 1.35 0.25 0.10 1.65 1.25 0.31 0.51 0.25 0.17 9.80 9.90 10.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 16 0° 8° 0.10 0.25 0.20
aaa C A2 A SEATING PLANE C bxN bbb A1 C A-B D GAGE PLANE 0.25 SIDE VIEW
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AC.
h h
H
c
SEE DETAIL
A
L (L1) DETAIL
01
A
Minimum Land Pattern - SO-16
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 304A.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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