SC1155

PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 DESCRIPTION The SC1155 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC1155 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium® llI and Athlon®, in both single and multiple processor configurations. Inhibit, under-voltage lockout and soft-start functions are included for controlled power-up. SC1155 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.1V to 1.85V in 25mV increments. The SC1155 high side driver can be configured as either a grounded reference or as a floating bootstrap driver. The high and low side MOSFET drivers have a peak current rating of 2 amps. FEATURES •= Programmable hysteresis •= 5 bit DAC programmable output (1.1V-1.85V) •= On-chip power good and OVP functions •= Designed to meet latest Intel specifications •= Up to 95% efficiency •= +1% voltage tolerance over temperature APPLICATIONS •= Server Systems and Workstations •= Intel Pentium® III Core Supplies •= AMD Athlon® Core Supplies •= Multiple Microprocessor Supplies •= Voltage Regulator Modules ORDERING INFORMATION DEVICE (1) PACKAGE SO-28 TEMP. RANGE (TJ) 0 - 125°C SC1155CSW.TR SC1155EVB Evaluation Board TYPICAL APPLICATION CIRCUIT Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. U1 SC1155CSW 1 R1 2k R3 2.7k 2 3 R2 1k C2 0.01 R4 1k C3 0.01 R5 100 C4 0.01 R6 20k C6 0.1 4 5 6 7 C5 0.001 8 C7 0.1 C8 0.01 +5V 9 10 11 12 13 14 IOUT DROOP OCP VHYST VREFB VSENSE AGND SOFTST N/C LODRV LOHIB DRVGND LOWDR DRV PWRGD VID0 VID1 VID2 VID3 VID4 INHIBIT IOUTLO LOSENSE HISENSE BOOTLO HIGHDR BOOT VIN12V 28 27 26 25 24 23 22 21 20 19 18 17 16 +12V 15 Q2 R12 IRL2203S 3.9 C9 2.2uF GND R7 150 C21-C26 150uF/4V C27 0.1 Q1 R11 IRL3103S 2.2 C13 0.33 L2 1.5uH Vout C12 0.33 GND C16 0.1 L1 1uH Vin C17-C19 150uF/16V C20 0.1 R10 10k INHIB R9 10k +5V PWRGD Vin +5 to +12V R8 10k Vout = 1.1 to 1.85V C8 2.2uF Athlon is a registered trademark of AMD Corporation Pentium is a registered trademark of Intel Corporation 1 © 2000 SEMTECH CORP. TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 ABSOLUTE MAXIMUM RATINGS Parameter VIN12V BOOT to DRVGND BOOT to BOOTLO Digital Inputs AGND to DRVGND LOHIB to AGND LOSENSE to AGND IOUTLO to AGND HISENSE to AGND VSENSE to AGND Continuous Power Dissipation, TA = 25°C Continuous Power Dissipation, TC = 25°C Operating Junction Temperature Lead Temperature (Soldering) 10 seconds Storage Temperature PD PD TJ TL TSTG Symbol VINMAX Maximum 14 25 15 -0.3 to +7.3 +0.5V 14 14 14 14 5 1.2 6.25 0 to +125 300 -65 to 150 Units V V V V V V V V V V W W °C °C °C PIN CONFIGURATION Top View SIMPLIFIED BLOCK DIAGRAM (28-Pin SOIC) 2 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name Pin Function IOUT DROOP OCP VHYST VREFB Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD. Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a function of load current. The voltage is set by a resistor divider between IOUT and AGND. Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. Buffered Reference Voltage (from VID circuitry). VSENSE Output Voltage Sense. AGND SOFTST NC LODRV LOHIB Small Signal Analog and Digital Ground. Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. Not connected Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. Low Side Inhibit. This pin is used to eliminate shoot-thru current. DRVGND Power Ground. Insure output capacitor ground is connected to this pin. LOWDR DRV VIN12V BOOT HIGHDR Low Side Driver Output. Connect to gate of low side MOSFET. Drive Regulator for the MOSFET Drivers. 12V Supply. Connect to 12V power rail. Bootstrap. This pin is used to generate a floating drive for the high side FET driver. High Side Driver Output. Connect to gate of high side MOSFET. BOOTLO Bootstrap Low. In desktop applications, this pin connects to DRVGND. HISENSE High Current Sense. Connected to the drain of the high side FET, or the input side of a current sense resistor between the input and the high side FET. LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. IOUTLO INHIBIT VID4(1) VID3 VID2 VID1 VID0 (1) (1) (1) (1) (1) This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. Programming Input (MSB). Programming Input. Programming Input. Programming Input. Programming Input (LSB). Power Good. This open collector logic output is high if the output voltage is within 5% of the set point. 3 PWRGD © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 ELECTRICAL CHARACTERISTICS Unless specified: 0 < TJ < 125°C, VIN = 12V PARAMETER Supply Voltage Range Supply Current (Quiescent) SYMBO L VIN12V IINq INH = 5V, VID not 11111, VIN above UVLO threshold during start-up, fSW = 200kHz, BOOTLO = 0V, CDH = CDL = 50pF INH = 0V or VID = 11111 or VIN below UVLO threshold during start-up, BOOT = 13V, BOOTLO = 0V INH = 5V, VID not 11111, VIN above UVLO threshold during start-up, fSW = 200kHz, BOOT = 13V, BOOTLO = 0V, CDH = 50pF REFERENCE/VOLTAGE IDENTIFICATION Reference Voltage Accuracy VID0 - VID4 High Threshold Voltage VID0 - VID4 Low Threshold Voltage POWER GOOD Undervoltage Threshold Output Saturation Voltage Hysteresis VTH(PWRGD) VSAT VHYS(PWRG D) CONDITIONS MIN 11.4 TYP MAX UNITS 12 15 13 V mA High Side Driver Supply Current (Quiescent) IBOOTq 10 µA 5 mA VREF VTH(H) VTH(L) 11.4V < VIN12V < 12.6V, over full VID range (see Output Voltage Table) -1 2.25 1 % V 1 V 90 IO = 5mA 0.5 10 95 % VREF V mV OVER VOLTAGE PROTECTION OVP Trip Point Hysteresis (1) VOVP VHYS(OVP) ICHG VSS = 0.5V, resistance from VREFB pin to AGND = 20kΩ, VREFB = 1.3V Note: ICHG = (IVREFB / 5) V(S/S) = 1V 38 42 10 46 %VOUT mV SOFT START Charge Current 10.4 13 15.6 µA Discharge Current INHIBIT COMPARATOR Start Threshold VIN12V UVLO Start Threshold Hysteresis Idischg 1 mA VstartINH VstartUVLO VhysUVLO 1 2.0 2.4 V 9.25 1.8 10 2 10.75 2.2 V V 4 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125°C, VIN = 12V PARAMETER HYSTERETIC COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Accuracy Hysteresis Setting DROOP COMPENSATION Initial Accuracy OVERCURRENT PROTECTION OCP Trip Point Input Bias Current HIGH-SIDE VDS SENSING Gain Initial Accuracy IOUT Source IOUT Sink Current IOUT Voltage Swing VIOUT Voltage Swing VIOUT Voltage Swing LOSENSE High Level Input Voltage LOSENSE Low Level Input Voltage Sample/Hold Resistance BUFFERED REFERENCE VREFB Load Regulation DEADTIME CIRCUIT LOHIB High Level Voltage LOHIB Low Level Input Voltage LOWDR High Level Input Voltage LOWDR Low Level Input Voltage VihLOHIB VilLOHIB VihLOWDR VilLOWDR (Note 1) (Note 1) 2 1.0 2 1.0 V V V V VldregREFB 10µA < IREFB < 500µA 2 mV VIOUT_ACC VHISENSE = 12V, VIOUTLO = 11.9V 500 40 0 0 0 2.85 1.8 50 65 80 50 3.75 2.0 1.0 2 6 V/V mV µA µA V V V V V Ω VOCP IbiasOCP 0.09 0.1 0.11 100 V nA VDROOP_ACC VDROOP = 50mV 5 mV VosHYSCMP IbiasHYSCMP VHYS_ACC VHYS_SET VDROOP pin grounded 5 1 7 60 mV µA mV mV SYMBOL CONDITIONS MIN TYP MAX UNITS IsourceIOUT VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V IsinkIOUT VIOUT (IN) VIOUT(4,5V) VIOUT(3V) VihLOSENSE VilLOSENSE RS/H VIOUT = 0.05V, VHISENSE = 12V, VIOUTLO = 12V VHISENSE = 11V, RIOUT = 10k0hm VHISENSE = 4.5V, RIOUT = 10kOhm VHISENSE = 3V, RIOUT = 10kOhm VHISENSE = 4.5V (Note 1) VHISENSE = 4.5V (Note 1) 4.5V ≤ = 13V 5 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125°C, VIN12V = 12V PARAMETER DRIVE REGULATOR DRV Voltage Load Regulation Short Circuit Current HIGH-SIDE OUTPUT DRIVER Peak Output Current IsrcHIGHDR’ duty cycle < 2%, tpw < 100us, 2 A VDRV VldregDRV IshortDRV 11.4 < VIN12V < 12.6V, IDRV = 50mA 1mA < IDRV < 50mA 100 7 100 9 V mV mA SYMBOL CONDITIONS MIN TYP MAX UNITS IsinkHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src), or VHIGHDR = 5V (sink) (Note 1) Output Resistance RsrcHIGHDR’ TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V RsinkHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V LOW-SIDE OUTPUT DRIVER Peak Output Current IsrcLOWDR’ IsinkLOWDR duty cycle < 2%, tpw < 100us, TJ = 125°C VDRV = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (sink) (Note 1) 2 45 Ω 5 A Output Resistance RsrcLOWDR’ TJ = 125°C VDRV = 6.5V, VLOWDR = 6V RsinkLOWDR TJ = 125°C VDRV = 6.5V, VLOWDR = 0.5V 45 Ω 5 6 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 DYNAMIC ELECTRICAL CHARACTERISTICS Unless specified: 0 < TJ < 125°C, VIN12V = 12V PARAMETER SYMBOL (1) CONDITIONS MIN TYP MAX UNITS HYSTERETIC COMPARATORS Propagation Delay Time from VSENSE to HIGHDR or LOWDR (excluding deadtime) OUTPUT DRIVERS (2) tHCPROP 10mV overdrive, 1.3V < Vref < 3.5V 150 250 ns HIGHDR rise/fall time trHIGHDR ,tfHIGHDR trLOWDR , tfLOWDR (1) Cl = 9nF, VBOOT = 6.5v, VBOOTLO = grounded, TJ = 125 °C Cl = 9nF, VDRV = 6.5v, TJ = 125 °C 1 2 60 ns LOWDR rise/fall time 60 ns OVERCURRENT PROTECTION Comparator Propagation Delay Time Deglitch Time (Includes comparator propagation delay time) OVERVOLTAGE PROTECTION Comparator Propagation Delay Time Deglitch Time (Includes comparator propagation delay time) HIGH-SIDE Vds SENSING Response Time (1) tOCPROP tOCDGL µs 5 µs (1) tOVPROP tOVDGL 2 1 5 µs µs tVDSRESP VHISENSE = 12v, VIOUTLO pulsed from 12v to 11.9v, 100ns rise and fall times VHISENSE = 4.5v, VIOUTLO pulsed from 4.5v to 4.4v, 100ns rise and fall times VHISENSE = 3v, VIOUTLO pulsed from 3.0v to 2.9v, 100ns rise and fall times 2 µs 3 µs 3 µs Short Circuit Protection Rising Edge Delay Sample/Hold Switch turnon/turn-off Delay tVDSRED tSWXDLY LOSENSE grounded 3v < VHISENSE < 11v VLOSENSE = VHISENSE 300 30 500 100 ns ns 7 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 DYNAMIC ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125° C, VIN12V = 12V PARAMETER (1) SYMBOL (1) CONDITIONS MIN TYP MAX UNITS HIGH-SIDE Vds SENSING (Cont.) POWER GOOD Comparator Propagation Delay SOFTSTART (1) tPWRGD 1 µs Comparator Propagation Delay DEADTIME (2) tSLST overdrive = 10mv 560 900 ns Driver Nonoverlap Time LODRV (1) tNOL CLOWDR = 9nF, 10% threshold on LOWDR 30 100 ns Propagation Delay tLODRVDLY 400 ns Notes (1) Guaranteed, but not tested. (2) Test circuit and timing diagram. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. TEST CIRCUIT TIMING DIAGRAM 8 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 TYPICAL PERFORMANCE CURVES 5V Efficiency SC1155 Effiency, 5Vin 95% 93% 91% 89% Effiency 87% 85% 83% 81% 79% 77% 75% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout 5V Regulation SC1155 Voltage Regulation, 5Vin 3% 2% 1% 0% -1% -2% -3% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout Regulation 9 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 TYPICAL PERFORMANCE CURVES (Cont.) 12V Efficiency SC1155 Effiency, 12Vin 95% 93% 91% 89% Effiency 87% 85% 83% 81% 79% 77% 75% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout 12V Regulation SC1155 Voltage Regulation, 12Vin 3% 2% 1% 0% -1% -2% -3% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout Regulation 10 © 2000 SEMTECH CORP. BLOCK DIAGRAM © 2000 SEMTECH CORP. IOUT HISENSE IOUTLO LOSENSE SOFTST + + PRELIMINARY - August 7, 2000 PWRGD 50uA G=2 ANALOG BIAS PREREG I(VREFB) / 5 FAULT BANDGAP RISING EDGE DELAY Vcc VIN12V DRIVE REGULATOR R Q + - + DRV S SHUTDOWN 1.15VREF 0.93VREF HIGHDR LOWDR FILTER 0.93VREF BOOT DEGLITCH UVLO INH + + - DEGLITCH - + HIGHDR - + - + BOOTLO 10V VID DAC + FILTER Vcc VREF FILTER + + 1.15VREF + LOWDR - VSENSE DRVGND 2V - - + VREF + 11111 DECODE PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE 100mV OCP AGND INHIBIT VID0 VID2 VID4 VID1 VID3 DROOP VSENSE VHYST VREFB LOHIB LODRV SC1155 11 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 OUTPUT VOLTAGE TABLE 0 = VSS; 1 = OPEN VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDC (V) Output Off 1.1 1.125 1.15 1.175 1.2 1.225 1.250 1.275 1.3 1.325 1.35 1.375 1.4 1.425 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 1.775 1.8 1.825 1.85 NOTE: (1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, turning both MOSFETs off, and the controller will be set to a low-Iq state. 12 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 FUNCTIONAL DESCRIPTION Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +5V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 1.1V to 1.85V in 25mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VREF is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the REFB pin. The voltage on this pin will be within 3mV of VREF. It is not recommended to drive loads with REFB other than setting the hysteresis of the hysteretic comparator, because the current drawn from REFB sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis of the comparator will be equal to twice the voltage difference between REFB and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low RDS(ON) N-channel MOSFET, and is rated for 2 amps source and sink current. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) N-channel MOSFET, and is rated for 2 amps source and sink current. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the FET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 2 volts. The low side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit. This controls the high-side driver by filtering out the noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side FET while it is turned on. The sampling network consists of an internal 50Ω switch and an external 0.1µF hold capacitor. Internal logic controls the turn-on and turn-off of the sample/ hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF (equal to VREF x (1+R5/R6)) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on the DROOP pin from VREF. The voltage on the IO pin is divided down with an external 13 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 FUNCTIONAL DESCRIPTION (cont.) resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INH goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INH, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. VIN The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SS and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current proportional to VREF, the power-up time for VOUT will be independent of VREF. Thus, CSS can remain the same value for all VID settings. The soft start charging current is determined by the following equation: ISS = IREFB/5. Where IREFB is the current flowing out of the REFB pin. It is recommended that no additional loads be connected to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by REFB is 500µA. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 7% (nominal) below VREF, then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VREF, than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side FET. The overcurrent threshold is adjustable with an external resistor divider between IO and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side FET against a short-to-ground fault on the terminal common to both power FETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA. 14 © 2000 SEMTECH CORP. +5V U1 SC1155 R9 10k PWRGD +12V +12V PWRGD C11 0.01 27 INHIB +5V +5V C9 0.1 3 OCP S1 VID1 26 +5V 28 1 IOUT © 2000 SEMTECH CORP. +12V 2 DROOP VID0 APPLICATION CIRCUIT R1 2k R3 2.7k PRELIMINARY - August 7, 2000 +5V R2 1k 4 VHYST VID2 25 R10 10k R4 1k C3 0.01 C2 0.01 5 VREFB VID3 C6 0.1 6 VSENSE L1 7 AGND 1uH 8 SOFTST C12 0.1 9 +5V 10 LODRV Ra* 0 R11 2.2 Rb* C13 13 LOWDR +12V 14 DRV R12 3.9 Q2 IRL2203S C21 150uF/4V D1 MBRD1035 C22 150uF/4V C23 150uF/4V C24 150uF/4V C25 150uF/4V VIN12V 15 BOOT C14 0.33 16 0.33 0 L2 1.5uH Q1 IRL3103S HISENSE 19 N/C LOSENSE 20 IOUTLO 21 C16 0.1 C17 150uF 16V C18 150uF 16V C19 150uF 16V C20 0.1 INHIBIT 22 VID4 23 24 R5 100 1 2 3 4 5 10 9 8 7 6 C4 0.01 R6 20k C5 J1 0.001 + 1 2 3 4 _ Vin +5 to +12V C7 0.1 C8 0.01 pin18 11 LOHIB BOOTLO 18 Vout Dopt. MBR0530 12 DRVGND HIGHDR 17 GND J2 + C26 150uF/4V C27 0.1 Vout PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE C8 2.2uF 16V C9 2.2uF 16V 1 2 3 4 5 6 _ R8 10k R7 150 * Only one resistor/jumper to be installed, either Ra or Rb. SC1155 15 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 MATERIALS LIST Quantity 1 6 3 7 2 6 2 1 1 1 1 1 2 1 2 1 1 1 1 3 1 1 1 C5 C1-C4, C8, C11 C17-C19 C6,C7,C9,C12,C16,C20, C27 C13,C14 C21-C26 C10,C15 D1 L1 L2 Q1 Q2 RA,RB R1 R2,R4 R3 R5 R6 R7 R8,R9,R10 R11 R12 U1 Reference 0.001µF 0.01µF 150µF, 16V (TPS) 0.1µF 0.33µF 150µF, 4V, (PosCap) 2.2µF, 16V MBRD1035 1µH, DO5022P-102 1.5µH, DO5022P-152HC IRL3103NS, D2PAK IRL2203NS, D2PAK 0Ω 2K 1K 2.7K 100 20K 150 10K 2.2 3.9 SC1155, SO-28 SEMTECH MOT Coilcraft Coilcraft Int. Rect. Int. Rect. Sanyo AVX Part/Description Vendor SC1155 Notes Layout guidelines 1. Locate R8 and C5 close to pins 6 and 7. 2. Locate C6 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin. 9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. 10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND. 16 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 EVALUATION BOARD ARTWORK TOP LAYER BOTTOM LAYER 17 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 EVALUATION BOARD LAYOUT TOP VIEW BOTTOM VIEW 18 © 2000 SEMTECH CORP. PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER WITH VRM 9.0 VID RANGE PRELIMINARY - August 7, 2000 SC1155 OUTLINE - SO-28 ECN00-1229 19 © 2000 SEMTECH CORP.