SC1183CSW

PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1182/3 combines a synchronous voltage mode controller with two low-dropout linear regulators providing most of the circuitry necessary to implement three DC/DC converters for powering advanced ® microprocessors such as Pentium II (Klamath) or Deschutes. The SC1182/3 switching section features an integrated 5 bit D/A converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. The SC1182/3 switching section operates at a fixed frequency of 200kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. The SC1182/3 linear sections are low dropout regulators. The SC1182 supplies 1.5V for GTL bus and 2.5V for non-GTL I/O. For the SC1183 both LDO’s are adjustable. FEATURES • • • • • • • • • • Synchronous design, enables no heatsink solution 95% efficiency (switching section) 5 bit DAC for output programmability On chip power good function ® Designed for Intel Pentium ll VRM8.1 requirements 1.5V, 2.5V or Adj. @ 1% for linear section APPLICATIONS Pentium ll or Deschutes microprocessor supplies Flexible motherboards 1.3V to 3.5V microprocessor supplies Programmable triple power supplies ® ORDERING INFORMATION Part Number (1) Package Linear Voltage Temp. Range (T J) SC1182CSW SC1183CSW SO-24 SO-24 1.5V/2.5V 0° to 125°C Adj. 0° to 125°C Note: (1) Add suffix ‘TR’ for tape and reel. PIN CONFIGURATION BLOCK DIAGRAM REF. Top View AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL (24 Pin SOIC) FET CONTROLLER 2.5V/ADJ. 1.265V REF. FET CONTROLLER 1.5V/ADJ. LDOV Pentium is a registered trademark of Intel Corporation 1 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 ABSOLUTE MAXIMUM RATINGS Parameter VCC to GND PGND to GND BST to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case Symbol VIN Maximum -0.3 to +7 ±1 -0.3 to +15 0 to +70 0 to +125 -65 to +150 300 80 25 Units V V V °C °C °C °C °C/W °C/W TA TJ TSTG TL θJA θJC ELECTRICAL CHARACTERISTICS Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; LDOV = 11.4V to 12.6V; TA = 25°C PARAMETER Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Minimum operating voltage Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink/Source Current Peak DL Sink/Source Current Output Voltage Tempco Gain (AOL) OVP threshold voltage OVP source current Power good threshold voltage Dead time Linear Sections Quiescent current Output Voltage (LDO1 SC1182) Output Voltage (LDO2 SC1182) Reference Voltage (SC1183) Feedback Pin Bias Current (SC1183) Gain (AOL) Load Regulation Line Regulation Output Impedance Notes: (1) See Output Voltage table. (2) In application circuit. © 1998 SEMTECH CORP. CONDITIONS IO = 2A VCC VCC = 5.0 IO = 0.8A to 15A MIN TYP MAX UNITS BSTH-DH = 4.5V, DH-PGNDH = 2V BSTL-DL = 4.5V, DL-PGNDL = 2V VOSENSE to VO VOVP = 3.0V See Note 1. 4.2 7 8 15 1 0.5 4.2 60 70 80 180 200 220 90 95 1 1 30 100 35 120 10 88 112 50 100 5 2.475 2.500 2.525 1.485 1.500 1.515 1.252 1.265 1.278 10 90 0.3 0.3 200 V mA % % V mV kHz % A A o ppm/ C dB % mA % ns mA V V V uA dB % % Ω 2 LDOV = 12V LDOS (1,2) to GATE (1,2) (2) IO = 0 to 8A 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AGND GATE1 LDOS1 LDOS2 VCC OVP (1) PWRGOOD CSCS+ PGNDH DH PGNDL DL BSTL BSTH (1) EN VOSENSE (1) VID4 (1) VID3 (1) VID2 (1) VID1 (1) VID0 LDOV GATE2 Pin Function Small Signal Analog and Digital Ground Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage High Signal out if VO>setpoint +20% Open collector logic output, high if VO within 10% of setpoint Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter; High or open for normal operation. Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) +12V for LDO section Gate Drive Output LDO2 Top View AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL (24 Pin SOIC) Note: (1) All logic level inputs and outputs are open collector TTL compatible. 3 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 OUTPUT VOLTAGE Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; T A = 25°C PARAMETER Output Voltage CONDITIONS IO = 2A in Application circuit VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 MIN 1.287 1.336 1.386 1.435 1.485 1.534 1.584 1.633 1.683 1.732 1.782 1.831 1.881 1.930 1.980 2.029 1.980 2.079 2.178 2.277 2.376 2.475 2.574 2.673 2.772 2.871 2.970 3.069 3.168 3.267 3.366 3.465 TYP 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 MAX 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 1.869 1.919 1.970 2.020 2.071 2.020 2.121 2.222 2.323 2.424 2.525 2.626 2.727 2.828 2.929 3.030 3.131 3.232 3.333 3.434 3.535 UNITS V 4 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 August 25, 1998 12V 5V + R1 10 0.1uF U1 5 VCC CS+ CSVO SENSE PWRGOOD VID4 OVP VID0 VID1 VID2 + R16 10k C13 1.00k 2.32k R6 R5 © 1998 SEMTECH CORP. APPLICATION CIRCUIT C1 0.1uF C2 1500uF C3 1500uF 9 8 17 7 18 4uH 15 11 10 13 14 23 3 * R13 C14 1500uF C16 1500uF Q2 BUK556 L1 R4 5mOhm C15 1500uF C17 1500uF Q1 BUK556 6 22 21 20 19 VID3 EN AGND PGNDL GATE2 GATE1 LDOS2 LDOS1 LDOV BSTL DL PGNDH DH BSTH VCC_CORE EN 16 C5 0.1uF 12 24 2 4 1 + + + + C18 0.1uF GND OVP VID0 VID1 VID2 VID3 VID4 SC1182/3CSW R12 * VLIN1 Q3 BUK556 PWRGD + + * R15 R17 100K C11 330uF C12 330uF VLIN2 5V 5V + R14 * + C22 Q4 BUK556 C9 330uF + + PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER C21 330uF C10 330uF NOTE: FOR SC1182, R12,R13,R14 AND R15 ARE NOT REQUIRED. CONNECT LDOS1 (PIN3) AND LDOS2 (PIN4) TO VLIN1 AND VLIN2 RESPECTIVELY TO DIRECTLY GENERATE 2.5V AND 1.5V OUTPUTS. * SEE "SETTING LDO OUTPUT VOLTAGE" TABLE R18 100K 330uF SC1182/3 5 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 MATERIALS LIST Qty. Reference 4 6 6 1 4 1 1 1 1 1 1 1 1 2 1 C1,C5,C13, C18 C2,C3,C14C17 C9-C12, C21, C22 L1 Q1,Q2,Q3, Q4 R4 R5 R6 R1 R12 R13 R14 R15 R17, R18 U1 Part/Description 0.1µF Ceramic 1500µF/6.3V 330µF/6.3V 4µH See notes 5mΩ 2.32kΩ, 1%, 1/8W 1kΩ, 1%, 1/8W 10Ω, 5%, 1/8W 1%, 1/8W 1%, 1/8W 1%, 1/8W 1%, 1/8W 100K, 5%, 1/8W SC1182/3CSW See notes IRC Various Various Various Various Various Various Various Various SEMTECH See Table Below (Not required for SC1182) See Table Below (Not required for SC1182) See Table Below (Not required for SC1182) See Table Below (Not required for SC1182) Vendor Various SANYO Various 8 Turns 16AWG on MICROMETALS T50-52D core FET selection requires trade-off between efficiency and cost. Absolute maximum RDS(ON) = 22 mΩ f or Q1,Q2 OAR-1 Series MV-GX or equiv. Low ESR Notes SETTING LDO OUTPUT VOLTAGE RB VOUT LDO1 (LDO2) 3.45V 3.30V 3.10V 2.90V 2.80V 2.50V 1.50V R12 (R14) 105Ω 105Ω 102Ω 100Ω 100Ω 100Ω 100Ω RA R13 (R15) 182Ω 169Ω 147Ω 130Ω 121Ω 97.6Ω 18.7Ω VOUT = 1.265 ⋅ (R A + R B ) + (IFB ⋅ R A ) RB Where : IFB = Feedback pin bias current R A = Top feedback resistor R B = Bottom feedback resistor See layout diagram for clarification R A and R B must be low enough so that the (IFB ⋅ R A ) term does not cause significan t error 6 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 95% 95% SC1182/3 90% 90% Efficiency Efficiency 85% 85% 80% 3.5V Std 3.5V Sync 3.5V Sync Lo Rds 80% 2.8V Std 2.8V Sync 2.8V Sync Lo Rds 75% 75% 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 Typical Efficiency at Vo=3.5V 95% Typical Efficiency at Vo=2.8V 95% 90% 90% Efficiency Efficiency 85% 85% 80% 2.5V Std 2.5V Sync 2.5V Sync Lo Rds 80% 2.0V Std 2.0V Sync 2.0V Sync Lo Rds 75% 75% 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 Typical Efficiency at Vo=2.5V Typical Efficiency at Vo=2.0V Typical Ripple, Vo=2.8V, Io=10A Transient Response Vo=2.8V, Io=300mA to 10A 7 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1182/3 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. 12V IN 5V 10 1 2 3 4 0.1uF 5 6 0.1uF 7 8 9 10 11 12 AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL GATE2 LDVO VID0 VID1 VID2 VID3 VID4 VO SENSE EN BSTH BSTL DL 24 23 22 Cin 21 20 19 18 17 16 15 14 13 Q2 Cout 4uH + Q1 + 1.00k 5mOhm Vout 2.32k SC1182/3 RA1 Heavy lines indicate 5V Q3 + Cin Lin RB1 Cout Lin1 + Vo Lin1 high current paths. For SC1182, RA1, RA2, RB1 and RB2 are not required. LDOS1 connects to Vo Lin1, LDOS2 connects to Vo Lin2 Vo Lin2 RA2 Q4 RB2 Cout Lin2 + Layout diagram for the SC1182/3 8 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1182/3 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1182/3 should be supplied from the SC1182/3 5V supply through a 10Ω resistor, the Vcc pin should be decoupled directly to AGND by a 0.1µF ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1182/3 should run parallel and close to each other. The 0.1µF capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s). 5V + Vout + Currents in various parts of the power section 9 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence enSWITCHING SECTION suring a good recovery from transient with no additional OUTPUT CAPACITORS - Selection begins with the excursions. most critical component. Because of fast transient load We must also be concerned with ripple current in the current requirements in modern microprocessor core output inductor and a general rule of thumb has been to supplies, the output capacitors must supply all transient allow 10% of maximum output current as ripple current. load current requirements until the current in the output Note that most of the output voltage ripple is produced inductor ramps up to the new level. Output capacitor by the inductor ripple current flowing in the output caESR is therefore one of the most important criteria. The pacitor ESR. Ripple current can be calculated from: maximum ESR can be simply calculated from: COMPONENT SELECTION R ESR V ≤t It ILRIPPLE= VIN 4⋅L⋅ fOSC Where Vt = Maximum transient voltage excursion I t = Transient current step For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. Each Capacitor Technology Low ESR Tantalum OS-CON Low ESR Aluminum C (µF) 330 330 1500 ESR (m Ω) 60 25 44 Qty. Rqd. 6 3 5 Total C (µF) 2000 990 7500 ESR (m Ω) 10 8.3 8.8 Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as: PCOND = I2 ⋅ R DS( on ) ⋅ δ O where δ = duty cycle ≈ VO VIN b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then: The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from: PSW = I O ⋅ V IN ⋅ 10 − 2 or more generally, PSW = I O ⋅ VIN ⋅ ( t r + t f ) ⋅ f OSC 4 L≤ R ESR C (VIN − VO ) It c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: PRR = Q RR ⋅ V IN ⋅ f OSC To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp 10 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 FET type RDS(on) (mΩ) PD (W) 2.48 0.79 1.53 Package TO220 D PAK SO-8 2 SC1182/3 BUK556H 22 IRL2203 Si4410 7.0 13.5 BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by: PCOND = I2 ⋅ R DS ( on ) ⋅ (1 − δ ) O INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. For the example above: FET type RDS(on) (mΩ) PD (W) 1.95 0.62 1.20 7.0 13.5 Package TO220 D PAK SO-8 2 BUK556H 22 IRL2203 Si4410 Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of o 2 o 40 C/W for the D PAK and 80 C/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: Temperature rise ( C) FET type IRL2203 Si4410 o o Top FET (1) Bottom FET 39.0 96 (1) BUK556H 49.6 31.6 122.4 24.8 (1) With 20 C/W Heatsink It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. 11 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER August 25, 1998 SC1182/3 OUTLINE DRAWING JEDEC MS-013AD B17104B 12 © 1998 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320