SC122

SC122 Low Voltage Synchronous Boost Converter POWER MANAGEMENT Features Input voltage — 0.7V to 1.6V Minimum start-up voltage — 0.85V Output voltage fixed at 3.3V Peak input current limit — 350mA typically Output current 95mA at VIN = 1.6V, 50mA at VIN = 0.9V Efficiency up to 80% Internal synchronous rectifier Switching frequency — 1.2MHz Power save (voltage hysteretic) control Anti-ringing circuit Operating supply current (measured at OUT) — 40μA No forward conduction path during shutdown MLPD-UT-6 1.5 × 2.0 × 0.6 (mm) package Lead-free and halogen-free WEEE and RoHS compliant Description The SC122 is a high efficiency, low noise, synchronous step-up DC-DC converter. It produces a fixed 3.3V output from a single cell alkaline or NiMH battery. It features an internal 1.2A switch and synchronous rectifier to achieve high efficiency and to eliminate the need for an external Schottky diode. The SC122 operates exclusively in voltage-hysteretic power save mode (PSAVE) for high efficiency under light load conditions. It features anti-ringing circuitry for reduced EMI in noise sensitive applications. While disabled, the output remains in a high impedance state to preserve the charge on the output capacitor. This permits ultra-low idle quiescent currents in applications in which the SC122 can be periodically enabled by an external controller to recharge the output capacitor. Low quiescent current is obtained despite a high 1.2MHz operating frequency. Small external components and the space saving MLPD-UT-6, 1.5×2.0×0.6 (mm) package, make this device an excellent choice for small handheld applications that require the longest possible battery life. Applications Electric toothbrushes Personal medical products Single-cell alkaline, NiCd, or NiMH applications Typical Application Circuit L1 IN Single Cell (1.2V) CIN EN GND LX OUT GND COUT 3.3V SC122 February 1, 2010 © 2010 Semtech Corporation 1 SC122 Pin Configuration Ordering Information Device SC122ULTRT(1)(2) SC122EVB LX GND IN 1 TOP VIEW 6 Package MLPD-UT-6 1.5×2 Evaluation Board OUT GND EN 2 5 3 T Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and compliant and halogen-free. 4 MLPD-UT; 1.5×2, 6 LEAD θJA = 84°C/W Marking Information 122 yw MLPD-UT; 1.5×2, 6 LEAD yw = date code 2 SC122 Absolute Maximum Ratings IN, OUT, LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 EN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 (1) Recommended Operating Conditions Ambient Temperature Range (°C) . . . . . . . . . . . . . . 0 to +70 VIN ( V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 to 1.6 VOUT ( V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Thermal Information Thermal Resistance Junction-Ambient(2) (°C/W) . . . . . . . 84 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150 Storage Temperature Range (°C) . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted VIN = 1.2V, CIN = COUT = 22μF, L1 = 4.7μH, TA = 0 to +70°C. Typical values are at TA = 25°C. Parameter Input Voltage Range Output Voltage Output Accuracy Minimum Startup Voltage Operating Supply Current (1) Disabled OUT Leakage Current Disabled IN Quiescent Current Shutdown Current Internal Oscillator Frequency Startup Time Minimum VIN for Restart (2) P-Channel ON Resistance N-Channel ON Resistance P-Channel Startup Current Limit Symbol VIN VOUT VOUT-tol VIN-SU IOUT-Q IOUT-DIS IIN-DIS IIN-SHDN fOSC tSU VIN-Restart RDS(ON)P RDS(ON)N ILIM(P)-SU Conditions Min 0.7 Typ Max 1.6 Units V V 3.3 VEN = VIN IOUT < 1mA VEN = VIN, IOUT = 0mA, VOUT = 3.3V VEN = 0, VOUT = 3.3V (externally forced) VEN = 0, VIN = 1.6, VOUT = 3.3V (externally forced) VEN = 0V, VIN = 1.6V, VOUT = 0V while bursting From VEN low-to-high transition Lowest VIN to ensure re-enable within 300μs, VOUT = 3.1V (externally forced) ILX = 50mA ILX = 50mA, VIN=1.6V VIN = 1.2V, VEN > VIH 0.6 0.5 100 -3 0.85 40 2 4 8.5 1.2 1 1.0 3 % V μA μA μA μA MHz ms V Ω Ω mA 3 SC122 Electrical Characteristics (continued) Parameter N-Channel Current Limit LX Leakage Current PMOS LX Leakage Current NMOS Logic Input High Logic Input Low Logic Input Current High Logic Input Current Low Symbol ILIM(N) ILXPLK ILXNLK VIH VIL IIH IIL Conditions VIN = 1.2V TA = 25°C, VLX = 0V, VOUT = 3.3V TA = 25°C, VLX = 3.3V, VOUT = 3.3V VIN = 1.2V VIN = 1.2V VEN = VIN = 1.2V VEN = 0V Min Typ 350 Max Units mA 1 1 0.4 0.1 1 -0.2 μA μA V V μA μA NOTES: (1) Quiescent operating current is drawn from the OUT pin while in regulation. The quiescent operating current projected to the IN pin is approximately IQ × ( VOUT/VIN). (2) Restart occurs when the EN pin transitions from low to high while the output voltage is at or near the regulation value (3.3V). See the application section “The Enable Pin” for details. 4 SC122 Typical Characteristics — VOUT = 3.3V Efficiency vs. IOUT 100 90 80 70 VIN = 1.6V Efficiency vs. IOUT 100 90 80 70 TA = 25°C TA = 0°C L = 4.7μH, TA = 25 C ο L = 4.7μH, VIN = 1.2V Efficiency (%) Efficiency (%) 60 50 40 30 20 10 0 0.1 0.2 0.5 1 2 5 10 20 50 100 VIN = 0.9V VIN = 1.2V 60 50 40 30 20 10 0 0.1 0.2 0.5 1 2 5 10 20 50 100 TA = 70°C IOUT (mA) IOUT (mA) Load Regulation 3.31 3.3 3.29 L = 4.7μH, TA = 25 C ο Load Regulation 3.31 3.3 3.29 L = 4.7μH, VIN = 1.2V VOUT (V) 3.28 VIN = 0.9V VOUT (V) VIN = 1.6V TA = 70°C 3.28 3.27 TA = 0°C 3.27 3.26 3.25 0 VIN = 1.2V 3.26 TA = 25°C 10 20 30 40 50 60 70 80 90 100 3.25 0 10 20 30 40 50 60 70 80 90 100 IOUT (mA) IOUT (mA) Line Regulation — Low Load 3.31 3.3 3.29 L = 4.7μH, IOUT = 1mA 3.31 3.3 3.29 Line Regulation — High Load L = 4.7μH, IOUT = 45mA VOUT (V) 3.28 3.27 3.26 3.25 0.7 VOUT (V) TA = 0°C, 25°C, 70°C TA = 0°C, 25°C, 70°C 3.28 3.27 3.26 3.25 0.7 1 1.3 1.6 1 1.3 1.6 VIN (V) VIN (V) 5 SC122 Typical Characteristics — VOUT = 3.3V (continued) Temperature Regulation — Low Load 3.31 3.3 L = 4.7μH, IOUT = 1mA VIN = 1.6V Temperature Regulation — High Load 3.31 3.3 VIN = 1.2V L = 4.7μH, IOUT = 45mA 3.29 3.29 VOUT (V) 3.28 VIN = 1.2V VOUT (V) VIN = 0.9V VIN = 1.6V 3.28 3.27 3.26 3.27 3.26 VIN = 0.9V 3.25 0 10 20 30 40 o 50 60 70 3.25 0 10 20 30 40 o 50 60 70 Junction Temperature ( C) Junction Temperature ( C) Startup Max. Load Current vs. VIN L = 4.7μH 50 160 140 40 Startup Min. Load Resistance vs. VIN L = 4.7μH TA = 25°C Equivalent R (Ω ) LOAD 120 100 TA = 0°C IOUT (mA) 30 TA = 25°C TA = 70°C TA = 0°C 80 60 TA = 70°C 20 40 20 10 0 0.7 1 1.3 1.6 0 0.7 1 1.3 1.6 VIN (V) VIN (V) Maximum IOUT vs. VIN 120 100 Startup Voltage (V) Minimum Start-up Voltage vs. Temperature 0.9 VOUT = 3.3V, IOUT = 1mA L = 4.7μH 0.85 80 0.8 IOUT (mA) TA = 70°C 60 TA = 0°C TA = 25°C 0.75 40 20 0 0.7 0.65 0.6 0.7 1 1.3 1.6 0 10 20 VIN (V) 30 40 Temperature (°C) 50 60 70 6 SC122 Pin Descriptions MLPD Pin # 1 2, 5 3 4 6 Pin Name LX GND IN EN OUT Thermal Pad Pin Function Switching node — connect an inductor from the input supply to this pin. Signal and power ground connections. Battery input and damping switch connection. Enable digital control input — active high. Output voltage supply pin — requires an external 10μF bypass capacitance (effective under VOUT bias) for normal operation. Thermal Pad is for heat sinking purposes — connect to ground using multiple vias, not connected internally. T 7 SC122 Block Diagram IN 3 VOUT Comp. + + 1.7 V + 6 OUT EN 4 Start-up Oscillator PLIM Amp. Oscillator Gate Drive and Logic Control Bulk Bias 1 LX + NLIM Amplifier - GND 5 + Error Amp. + VREF - 1.2 V 2 GND 8 SC122 Applications Information Detailed Description The SC122 is a synchronous step-up hysteretic DC-DC converter utilizing a 1.2MHz fixed frequency switching architecture. It provides a fixed 3.3V output from an input voltage as low as 0.7V, with an unloaded startup input voltage of 0.85V. The SC122 operates exclusively in PSAVE regulation mode (bursts of switching boost cycles, alternating with periods of an output-high-impedance state). It has quiescent current consumption as little as 40μA into the OUT pin. It features anti-ringing circuitry for reduced EMI in noise sensitive applications. The boost cycles can be disabled with an active-high enable input. While disabled, the output remains in a high impedance state to preserve the charge on the output capacitor. This permits ultra-low idle quiescent currents in applications in which the SC122 can be periodically enabled by an external controller to recharge the output capacitor. The regulator control circuitry is shown in the Block Diagram. It is comprised of a feedback controller, an internal 1.2MHz oscillator, an n-channel Field Effect Transistor (FET) between the LX and GND pins, and a p-channel FET between the LX and OUT pins. The current flowing through both FETs is monitored and limited as required for startup and PSAVE regulator operation. An external inductor must be connected between the IN pin and the LX pin. During the burst phase of PSAVE operation, the controller alternates between the on-state and the off-state. During the on-state the n-channel FET is turned on, grounding the inductor at the LX pin. This causes the current flowing from the input supply through the inductor to ground to ramp up. The on-state continues until the first of two limits is reached, either the n-channel current limit ILIM(N), or the ontime limit TON-MAX = 0.9 × 1/fOSC. Then during the off-state, the n-channel FET is turned off and the p-channel FET is turned on, connecting the inductor between IN and OUT. The (now decreasing) inductor current flows from the input to the output, transferring the inductor energy to the output and boosting the output voltage above the input voltage for the remainder of the cycle period T = 1/fOSC. The cycle then repeats to re-energize the inductor. The burst phase continues until VOUT reaches an upper voltage threshold, at which point both FETs are turned off. This begins the high-impedance phase. The output capacitor then discharges into the load until VOUT reaches a lower voltage threshold, which initiates a new burst phase. The upper and lower voltage thresholds differ by approximately 50mV, and were chosen to provide an average output voltage of 3.3V. The time between bursts is determined by the discharge rate of the output capacitor, which depends on the value of output capacitance and the magnitude of the applied load. Figure 1 illustrates PSAVE regulation. VIN = 1.5V, IOUT = 20mA VOUT ripple (50mV/div) IL (100mA/div) VLX (5V/div) Time = (10μs/div) Figure 1 — PSAVE Regulation Waveforms The Enable Pin The EN pin is a high impedance logical input that can be used to enable or disable the SC122 under processor control. VEN > 0.4V will enable the output. The startup sequence from the EN pin is identical to the startup sequence from the application of input power. VEN < 0.1V will disable regulation and set the LX pin in a high-impedance state (turn off both FET switches). The OUT pin is also left in a high-impedance state when disabled. The SC122 can be disabled while maintaining the output voltage on the output capacitor, for the lowest possible quiescent current, while supporting a low application idle state load. The SC122 can then be periodically re-enabled for a brief time to refresh the charge held on the output capacitor, then disabled for an extended time as determined by the discharge rate of the output capacitor while supplying the idle-state load current. For VIN > VIN-Restart, and over the full specified temperature range, regulation will be fully enabled within 300μs of a high voltage on the EN pin with VOUT discharged to as low as 2.5V. 9 SC122 Applications Information (continued) A suggested very low duty cycle refresh oscillator circuit is included on the SC122 EVB-RM, the SC122 Evaluation Board with Refresh Modulation. limits will be invoked in reverse order as the output voltage falls through its various startup voltage thresholds. How far the output voltage drops depends on the load voltage vs. current characteristic. A reduction in input voltage, such as a discharging battery, will lower the load current at which overload occurs. At the overload threshold, the energy stored in the inductor at the end of each on-time is the same for all VIN. But since the voltage increase above the input voltage is greater, the available output current, IOUT = P/(VOUT - VIN), must decrease. When an overload has occurred, the load must be decreased to permit recovery. The conditions required for overload recovery are identical to those required for successful initial startup. Regulator Startup, Short Circuit Protection, and Current Limits The SC122 permits power up at input voltages from 0.85V to 1.6V. Startup current limiting of the internal switching n-channel and p-channel FET power devices protects them from damage in the event of a short between OUT and GND. This protection prevents startup into an excessive load. At the beginning of the cycle, the p-channel FET between the LX and OUT pins turns on with its current limited to approximately 100mA, the short-circuit output current. When VOUT approaches VIN (still below 1.7V), the n-channel current limit is set to 350mA (the p-channel limit is disabled), an internal oscillator turns on (approximately 200kHz), and a fixed 75% duty cycle PWM-type operation begins. When the output voltage exceeds 1.7V, fixed frequency PSAVE operation begins, with the duty cycle determined by an n-channel FET peak current limit of 350mA. Note that startup with a regulated active load is not the same as startup with a resistive load. The resistive load output current increases proportionately as the output voltage rises until it reaches VOUT/RLOAD, while a regulated active load presents a constant load as the output voltage rises from 0V to VOUT. Note also that if the load applied to the output exceeds the startup current limit, the criterion to advance to the next startup stage may not be achieved. In this situation startup may pause at a reduced output voltage until the load is reduced further. Anti-ringing Circuitry When both FET switches are simultaneously turned off, an internal switch between the IN and LX pins is closed. This provides a moderate resistance path across the inductor to dampen the oscillations at the LX pin. This effectively reduces EMI that can develop from the resonant circuit formed by the inductor and the drain capacitance at LX. The anti-ringing circuitry is disabled between PSAVE bursts. Inductor Selection The inductance value primarily affects the amplitude of inductor current ripple (ΔIL). The inductor peak current IL-max = IL-avg + ΔIL/2, where IL-avg is the inductor current averaged over a full on/off cycle, is subject to the n-channel FET peak current limit ILIM(N). The inductor average current is equal to the output load current. Increasing inductance reduces ΔIL and therefore increases the maximum supportable output current. The performance plots of this datasheet were obtained with L = 4.7μH. Larger values of inductance can provide higher maximum output currents. Any chosen inductor should have low DCR, compared to the RDS-ON of the FET switches, to maintain efficiency. For DCR