SC1401

HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1401 is a synchronous buck regulator designed to power the latest generation microprocessors in battery operated systems. The SC1401 may be used to provide both the I/O and core voltages utilizing synchronous rectification for the core supply voltage and an LDO N-Channel MOSFET controller for the I/O supply voltage. A 1.25 volt reference allows lower output voltages required by today’s portable microprocessors. The synchronous buck regulator is capable of achieving efficiencies up to 95%. The gate drive circuitry can deliver 2.0A peak currents, allowing the use of N-channel MOSFETs for lower switching and conduction losses. A digital soft start is provided to ensure orderly start up of the power supply without the need for external components. At light load in power save mode, the controller changes mode of operation by missing gate drive cycles, thus reducing gate drive current and improving efficiency. A logic high on PSAVE disables the power saving mode thus reducing noise. The SC1401 is fabricated in a high performance BiCMOS process. This process reduces the power dissipation in low current and shutdown operation modes and improves efficiency. The LDO controller is a high performance positive voltage regulator designed to provide a low noise power source to the microprocessor peripherals by driving a low cost external N-Channel MOSFET. VIN C1 C2 C3 C4 C5 FEATURES • • • • • • • • • >90% Efficiency (SMPS) 6.0V to 30V Input range 1.25V to 5.5V Adjustable output (SMPS) PWM and LDO regulator outputs High output gate drive of 2 Amps (SMPS) Power save mode for light load operation 200kHz/300kHz fixed-frequency PWM operation 2mA Typical quiescent current 2µA Typical shutdown current APPLICATIONS • • • Notebook and palmtop computers LCD monitors Internet appliances ORDERING INFORMATION DEVICE SC1401ISS PACKAGE SSOP-20 TEMP. (TA) -40°C - +85°C Notes (1) Add suffix “TR” for tape and reel. TYPICAL APPLICATION CIRCUIT ENABLE_IO RESET PSAVE U1 SYNC 1 SYNC SC1401ISS PSAVE 20 Q1 SHDN 2 SHDN RESET 19 D1 VO_LINEAR C6 VDD2 3 FB ENABLEIO 18 R1 C7 C8 4 VDD1 IOS 17 R2 +5V 5 R3 6 GND GATEIO 16 CSL VDD2 15 D2 Q2 7 CSH BST 14 C9 L1 R4 VO_SMPS C12 R5 C13 C14 +5V C10 C11 8 V5V DH 13 9 DL PHASE 12 D4 C15 D3 10 PGND PGND 11 Q3 R6 R7 C16 1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 PIN DESCRIPTION Pin # 1 Pin Name SYNC Pin Function Oscillator control/synchronization input. Connect to V5V for 300kHz. Connect to GND for 200kHz. For external clock synchronization in the 240kHz to 350kHz range. A high-to-low transition causes a new cycle start. Logic Low shuts down the switching regulator. Feedback input for the SMPS. FB selects fixed 1.25V output voltage setting when tied to VOUT. Connect FB to a resistor divider for adjustable output mode. R 8  Refer to page 9.  V O (SMPS) = 1.25 •  1 +  R9   Supply input from battery (6V to 30V). Low noise analog ground and feedback reference point. Inverting input to current sense amplifier. Also serves as the feedback input in fixed output mode. Non-Inverting input to current sense amplifier. Current limit level is 120mV referenced to CSL. 5 volt external supply used to power the gate drives, internal control and reference of the SC1401. Gate drive output for low side synchronous rectifier MOSFET. Device power ground. Device power ground. Inductor switching node connected to the source of high side MOSFET and drain of low side MOSFET. Gate drive output for high side N-Channel MOSFET. DH is a floating driver output driven from the floating voltage across BST to PHASE. Boost capacitor connection for the high side driver. Supply voltage input for the linear FET controller. Gate drive output for the linear FET controller. Sense input voltage for the adjustable voltage linear FET controller. R 5  Refer to page 9.  V O (Linear) = 1.25 •  1 +  R6   Logic low shuts down the linear FET controller. Active-Low reset output. A logic low enables power saving mode. 2 3 SHDN FB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VDD1 GND CSL CSH V5V DL PGND PGND PHASE DH BST VDD2 GATEIO IOS 18 19 20 ENABLEIO RESET PSAVE Note: All logic level inputs and outputs are open collector TTL compatible. 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 ABSOLUTE MAXIMUM RATINGS PARAMETER VDD1 to GND PGND to GND V5V, FB, CSH, CSL, IOS to GND SYNC, SHDN, PSAVE, ENABLEIO to GND BST to GND BST to PHASE VDD2 to GND GATEIO to GND Junction operating temperature (TJ) Thermal resistance junction to ambient (θJA) Storage temperature Lead soldering temperature MAXIMUM -0.3 to +36 - 0.3 to 0.3 -0.3 to +6 -0.3 to +6 -0.3 to +36 -0.3 to 6 -0.3 to +36 9 -40 to +125 50 -65 to +150 +300, 10 seconds UNITS V V V V V V V V °C °C/W °C °C ELECTRICAL CHARACTERISTICS Unless specified: VDD1 = 12V, VDD2 = 12V V5V = 5V, SHDN = PSAVE = 5V, TA = -40 °C to +85 °C . Typical values are at TA = +25°C. PARAMETER SMPS CONTROLLER VDD1 Input Voltage Range VOUT SMPS Internal BandGap Voltage, VREF Load Regulation Line Regulation Overcurrent-Limit Threshold PSAVE Mode Threshold Soft-Start Ramp Time Oscillator Frequency Maximum Duty Factor CONDITIONS MIN TYP MAX UNITS 6.0 VREF Measured at the Feedback pin 0mV < CSH - CSL < 100mV 6V < VDD1 < 30V CSH - CSL CSH - CSL, PSAVE = 0 V From enable to 95% full current limit with respect to fOSC SYNC = V5V SYNC = 0V SYNC = V5V SYNC = 0V 265 165 85 90 100 1.225 1.250 2 0.03 130 30 512 300 200 87 93 30.0 5.5 1.275 V V V % %/V 160 mV mV clks 335 235 kHz % Note 1: This device is ESD sensitive. Use of standard ESD handling precautions is required. 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 ELECTRICAL CHARACTERISTICS (continued) Unless specified: VDD1 = 12V, V5V = 5V, VDD2 = 12V SHDN = PSAVE = 5V, TA = -40 °C to +85 °C. Typical values are at TA = +25°C. LINE PARAMETER Gate Driver Sink/Source Gate Driver On-Resistance SYNC Input High Pulse1 SYNC Input Low Pulse Width SYNC Rise/Fall Time1 SYNC Input Frequency Range Current-Sense Input Leakage FB Input Leakage Current LINEAR REGULATOR VDD2 Input Voltage Range VOUT Linear GATEIO Source current IOS Input Leakage Current Line Regulation Load Regulation SUPPLY CURRENTS VDD1 Operating Supply Shutdown Supply Current V5V Operating Supply Current VDD2 Supply Current 1 CONDITIONS DL, DH, forced to 2V High or low MIN TYP 2.0 1.0 M AX UNITS A Ω 200 200 200 240 CSL = CSH = 5.5V FB = 1.25V 350 20 1 kHz µA µA ns 5.0 VREF VDD2=12V, GATEIO=0V IOS = 1.25V ILOAD=0.5A Vin=12V, ILOAD = 0.1A to 1A 0.03 0.85 2.6 30.0 5.5 1 V V mA µA %/V % 5 VDD1 = 6V to 30V, V5V = 5V, SHDN = 0V V5V = 5V, no load on DH/DL, PSAVE = 0V VDD2 = 12V 15 1.5 50 25 4 5 µA µA mA mA Note 1: Not tested. 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 ELECTRICAL CHARACTERISTICS (continued) PARAMETER FAULT DETECTION Thermal Shutdown Threshold VDD1 Undervoltage Reset Threshold V5V Undervoltage Reset Threshold FB Overvoltage Reset Threshold FB Undervoltage Reset Threshold RESET Propagation Delay IOS Undervoltage Reset Threshold RESET Delay Time LOGICAL INPUTS AND OUTPUTS Logic Input High Logic Input Low Input Leakage Current Logic Output Low Voltage Unless specified: VDD1 = 12V, VDD2 = 12V V5V = 5V, SHDN = PSAVE = 5V, TA = -40 °C to +85 °C. Typical values are at TA = +25°C. CONDITIONS Typical hysteresis = +10°V Falling edge of VDD1, hysteresis = 1% Falling edge of V5V, hysteresis = 1% W ith respect to unloaded output voltage, typ. Hysteresis = 1% W ith respect to unloaded output voltage, typ. Hysteresis = 1% FB Over/Under Voltage condition W ith respect to unloaded linear output voltage W ith respect to fOSC SHDN,ENABLEIO PSAVE,SYNC SHDN,ENABLEIO, PSAVE, SYNC RESET, ISINK = 4mA MIN TYP 150 M AX UNITS °C 4.2 3.75 4.5 4.0 10 -10 1.5 -10 4.8 4.25 V V % % µs % clks 27,000 32,000 37,000 1.8 1.6 -1.0 1.0 0.4 V µA V 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 LINE REGULATION (SMPS) Io = 7.0A, Vo = 2.2V OUTPUT VOLTAGE (V) 2.27 2.26 2.25 2.24 2.23 2.22 2.21 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 INPUT VOLTAGE (V) LOAD REGULATION, Vo = 2.2V (SMPS), Vin = 12V OUTPUT VOLTAGE (V) 2.250 2.245 2.240 2.235 2.230 2.225 2.220 2.215 0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) EFFICIENCY vs LOAD CURRENT 100.00% 95.00% EFFICIENCY (%) 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 0.1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) VIN = 6V VIN = 10V VIN = 14V VIN = 18V VIN = 22V 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 LOAD TRANSIENT: Vin = 16V, Vo = 2.0V, I = 1A to 7A RIPPLE VOLTAGE: 200KHZ RIPPLE VOLTAGE: 300KHZ 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 PIN CONFIGURATION (Top View) (20-Pin SSOP) VO (SMPS) VO (Linear) R7 (current sense resistor) R10 5Ω  R8  VO = 1.25 • 1 +   R9   R5  VO = 1.25 • 1 +   R6  R7 = Table 1 120mV I MAX 8 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 November 21, 2000 VDD1 = 6.0V to 30.0V C3 22uF,35V 22uF,35V 0.22uF C4 C12 C1 C2 5 6 7 6 CSL U2 IRF7805 D1 BAT42W R10 7 4 3 2 5.6 V5V DH 0.1uF 8 13 C11 1 CSH BST 14 VDD2 15 8 5 6 7 8 5 6 7 8 4 3 2 1 4 3 2 1 © 2000 SEMTECH CORP. VDD2 22uF,35V 22uF,35V +5V V5V C5 C6 R1 10uF 0.1uF 4.7K VDD2 C8 47uF C7 0.1uF RESET U1 SC1401CSS PSAVE Q1 MTD20N03HDL 19 Vo(lin) 20 1 SYNC ENABLEIO 2 SHDN D4 MTZ9.1B, 9.1V 500mW C9 C10 RESET To uP I/O 3.3V, 1.0A PSAVE 3 FB ENABLEIO 10uF 0.1uF 18 R5 41.2K SYNC VDD1 R6 24.9K V5V IOS 4 17 5 GND GATEIO 16 SHDN L1 R7A Vo(smps) 3.9uH 0.02, 1W R7B D2 0.02, 1W U4 IRF7805 R8 19.1K C13 330uF,6.3V C14 330uF,6.3V C15 330uF, 6.3V To uP core 2.2V, 8.5A C16 D3 0.1uF MBRS340T3 9 DL PHASE 12 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER TYPICAL NOTEBOOK CPU APPLICATION CIRCUIT FOR VCORE = 2.2V & VI/O = 3.3V 652 MITCHELL ROAD 10 PGND PGND 11 U3 IRF7805 MBRS340T3 R9 24.9K 9 NEWBURY PARK CA 91320 SC1401 VDD1 = 6.0V to 30.0V C3 C4 C12 GND C1 C2 22uF,35V 22uF,35V 22uF,35V 22uF, 35V 0.1uF Vlinear_Ext B1 3 R15 6.2K 1 1 1 2 V5V_onboard November 21, 2000 B2 JP4 Q2 MMBT2222 1 B3 Vlinear_ext JP3 V5V_Ext 2 1 V5V 2 1 C7 0.22uF 1 U1 SC1401CSS_RTP1 1 SYNC PSAVE Q1 MTD20N03HDL 2 19 D5 MA8062 3 FB ENABLEIO C9 4 VDD1 IOS R6 10K V5V 5 6 7 6 CSL VDD2 R10 7 3 2 1 CSH BST SEL 0.1uF V5V V5V DH SEL 10uF DL 5 6 7 PHASE 1M R4 10 PGND PGND 11 0.1uF 9 12 8 5 6 7 8 C5 C6 8 13 C11 R14 14 D1 Q3 IRF7805 15 R7B 8 17 10uF 0.1uF C10 47uF 18 R5 2K 1 C8 VO(lin) JP1 Vlinear_onboard 20 Vlinear_Ext JP2 R1 J1 1 J2 EVALUATION BOARD SCHEMATIC 1 2 SHDN RESET 5 GND GATEIO 16 2 V5V BAT42W 4 4 3 2 1 4 3 2 1 © 2000 SEMTECH CORP. VDD2 = 30V max V5V_onboard D4 MA8062 B5 0.02, 1W L1 R7A VO(lin) 1 B6 1 B4 4.7K S1 1 2 3 4 8 7 6 5 VO(smps) 0.02, 1W 3.9uH D2 MBRS340T3 18 C 0.1uF C13 C14 C15 C16 330uF,6.3V 330uF,6.3V 330uF, 6.3V 0.1uF R8 6.04K D3 MBRS340T3 1 B7 1 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER 652 MITCHELL ROAD Q5 IRF7805 Q4 IRF7805 R16 301K R11 SEL R13 SEL SW DIP-4 1M R12 1M R2 1M R3 C17 R9 10K 100pF NEWBURY PARK CA 91320 SC1401 10 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 Figure 1: SC1401 Block Diagram V5V SC1401 GND UVLO VDD1 VDD2 VBG GATEIO IOS BG REF BST PSAVE OCS SYNC DIGITAL CONTROLLER DH SHDN PHASE COUNTER DL PGND ENABLEIO DAC CSH CSL RESET POWER GOOD BG REF FB PGND VGB Figure 2: Main PWM Modulator Control Block 11 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com reached. Active shoot-through protection delays the turn-on of the low-side power device until the PHASE node drops below 1.25V. The low-side devices remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the low-side power device is low before the high-side device is turned on. When PSAVE is enabled (low) and the output current drops below 25% of its peak level, the PWM logic will automatically enter PSAVE mode to improve efficiency. When the controller enters power save, it increases the regulation point by 0.8%, typically issuing one more high side pulse as the converter enters PSAVE. The PWM control then disables switching cycles until the FB falls below the reference. At light loads the effective switching frequency will drop dramatically and efficiency will increase because of the reduced gate charge current required to switch the power stage. Boosting the regulation point when entering PSAVE gives the output improved dynamic regulation because the output voltage is not allowed to droop below the nominal regulation point. Load current steps, that cause the converter to come out of PSAVE, will not cause as large a negative dip in the output voltage. The PSAVE threshold is a function of the load and peak-to-peak inductor current. It can be calculated by the following equations: Detailed Description The SC1401 is a high performance, high efficiency, PWM synchronous buck controller, designed to power the latest generation microprocessors in battery operated systems. Two high-current gate drive outputs are supplied to control both MOSFETs in the synchronous rectified buck converter. This power supply can be programmed to operate at either fixed (1.25V) or adjustable output voltages. The power save feature enables high efficiency over a wide range of load current. The control and fault monitoring circuitry associated with the PWM controller includes digital softstart, turn-on sequencing, frequency compensation, power save, overcurrent and over and under voltage fault protection. An LDO NMOS linear regulator is also generated by the SC1401. A block diagram of the SC1401 is shown in Figure 1. PWM Control Block The SC1401 employs peak-current-mode control with slope compensation to provide fast output response to load and line transients. The PWM control block consists of an analog PWM modulator followed by PWM logic control. The analog modulator combines the current output, slope compensation signal and error voltage to generate a PWM pulse train. The PWM logic uses the pulse train from the modulator and other control signals to generate the output states for the high and low side gate driver outputs. A block diagram of the PWM control block is shown in Figure 2. An error amplifier generates the difference signal between the reference voltage and the feedback voltage to generate the control voltage for the peak current mode comparator. A nominal gain of 8 is used in the error amplifier to further increase the system loop-gain and reduce the load regulation error typically seen with low loop-gain current mode controllers. The increased gain in the voltage loop is compensated by pole-zero-pole response of the voltage error amplifier. The current feedback signal is summed with the slope compensation signal and compared to the control voltage by the PWM comparator. When the power supply is operating in continuous conduction mode with current > 25% of its peak value, the high side MOSFET is turned on at the beginning of each switching cycle. The high-side MOSFET is turned off when the desired duty cycle is V THPSAVE   =O   I-  ∆I L   • RS  2 ∆I L = (V IN - V O ) • D L f !IL = peak-to-peak inductor current IO = Load Current VIN = Input Voltage VO = Output Voltage D = Duty Cycle f = Frequency L = Inductance 12 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 Gate Drive and Control The gate drivers on the SC1401 are designed to switch large MOSFETs at up to 350kHz. The highside gate drivers are required to drive the gates of the high-side MOSFETs above the V5V input. The supply for these gate drivers is generated by charging a bootstrap capacitor from a supply when the low side driver is on. Monitoring circuits ensure that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low side driver outputs that control the synchronous rectifier in the power stage is on when the high side driver is off. Under light load conditions the ripple current will approach the point where it reverses polarity. This is detected by the low side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. value, the SMPS is latched off and synchronous NMOS FET is turned on. To prevent the output from ringing below ground a signal level Schottky diode should be placed across the output with its anode at ground. The same results apply if VDD1 or V5V fall below their respective under-voltage thresholds. If the SMPS or LDO outputs fall 10% below its nominal, the RESET output is pulled low. Shutdown Mode Holding the SHDN pin low disables the SC1401, reducing the total supply input current to 10.4 Amps, and for the FET choose a continuous conduction current rating Ic > 10.4 Amps. 15 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 and to handle any possible short circuit condition. These are 30V, 9A FET’s. Based on 85°C ambient temperature, 150°C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 150oC TA = 85oC !JA = 50oC/W PSU = 0.065W SC1401 Crss is the reverse transfer capacitance of the FET; in this case it equals 215pF for the IRF7805. Where Ig is the gate driver current. This is equal to 2A for the SC1401. So the total FET losses equate to: PFETS = 0.09 + 0.225 + 0.065 = 0.38W. Note that as Vin increases, the power dissipation from switching losses will also increase. This is especially important if the input to the supply is from an AC adapter. Therefore, it is necessary to check the calculations with your maximum input voltage specification. In addition, the distribution of power in the upper and lower FET will change as input voltage increases. Other losses to consider are gate charge losses, inductor switching and copper losses, and losses in the input and output capacitors. All these items will decrease efficiency and need to be carefully analyzed to obtain the highest efficiency possible, especially if running off battery power. PT = TJ − TA 150 − 85 = = 1.3W θ JA 50 Each FET must not exceed 1.3W of power dissipation. The conduction losses for the upper & lower FET can be determined. For the calculations below, a nominal input voltage of 12V, for Vout = 2.0V, Iout = 7A and f = 300kHz. The Rdson value for the upper & lower FET is 11milliohms. We will calculate the conduction losses and switching losses for each FET. From the calculations below we are well within the 1.3 watt dissipation limit as calculated above. Conduction Losses Upper FET: PCU = R DS • D • I2 PCU = 0.011 • PCU = 0.090W 2 • 72 12 Conduction Losses Lower FET: PCU = R DS • (1 − D ) • I2 PCL = 0.0055 • (1 − PCL = 0.225W 2 ) • 72 12 Switching Losses Upper FET: Note: switching losses exist on the upper FET only because the clamp diode across the lower FET will turn on prior to the lower FET turning on. PSU = C RSS • VIN • F • IO IG 2 = 215 • 10 −12 • 12 2 • 300000 •7 1 16 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER November 21, 2000 SC1401 OUTLINE DRAWING - SSOP-20 Jedec MO-150AE 17 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320