SC1403_04

Mobile Multi-Output PWM Controller with Lossless Current Sense POWER MANAGEMENT Description The SC1403 is a multiple-output power supply controller designed to power battery operated systems. The SC1403 provides synchronous buck converter control for two (3.3V and 5V) power supplies. An efficiency of 95% can be achieved for the two supplies. The SC1403 uses Semtech’s proprietary Virtual Current Sense™ technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. Lossless current sensing can be used to eliminate current sense resistors and reduce cost. The SC1403 also provides a 5V linear regulator for system housekeeping. The 5V linear regulator is derived from the battery; for improved efficiency, the output is switched to the 5V output when available. Control functions include power-up sequencing, soft start, power-good signaling, and frequency synchronization. Line and load regulation is to +/-1%. The internal oscillator can be set to 200kHz, 300kHz, or synchronized to an external clock. The mosfet drivers provide >1A peak drive current for fast mosfet switching. The SC1403 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. SC1403 Features 3.3V and 5V dual synchronous outputs, resistor programmable to 2.5V Fixed frequency or PSAVE operation for maximum efficiency over wide load range 5V / 50mA linear regulator Virtual Current Sense™ for enhanced stability Lossless current limiting Out of phase switching reduces input capacitance External compensation supports wide range of output filter components Programmable power-up sequence Power Good output Output overvoltage and overcurrent protection with output undervoltage shutdown 6µA typical shutdown current 6mW typical quiescent power Applications Notebook and subnotebook computers Tablet PCs Embedded applications Typical Application Circuit Revision 5, April 2004 1 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Absolute Maximum Ratings PAR AMETER VD D , V+, PHASE3, PHASE5 to GND PHASE3, PHASE5 to GND BST3, BST5, D H3, D H5 to GND PGND to GND VL to GND BST3 to PHASE3; D H3 to PHASE3; BST5 to PHASE5; D H5 to PHASE5 D ESC R IPTION Supply and Phase Voltages Phase Voltages Boost voltages Power Ground to Si gnal Ground Logi c Supply Hi gh-si de Gate D ri ve Supply Hi gh-si de Gate D ri ve Outputs Low-si de Gate D ri ve Outputs and C urrent Sense i nputs Logi c i nputs/outputs MAXIMU M -0.3 to +30 -2.0 (transi ent - 100 nsec) -0.3 to +36 ± 0.3 -0.3 to +6 -0.3 to +6 -0.3 to (+BSTx + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(V+ + 0.3V) C onti nuous +5 +50 Juncti on Temperature Range juncti on to ambi ent Storage Temperature Range Lead Temperature +150 76 -65 to +200 +300 °C , 10 second max. mA mA °C °C /Watt °C °C PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. U N ITS V V V V V V V V V V D L3, D L5 to GND C SL5, C SH5, C SL3, C SH3 to GND REF, SYNC , SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, C OMP3, C OMP5 to GND ON3, SHD N# to GND VL, REF Short to GND REF C urrent VL C urrent TJ Package Thermal Resi stance TS TL Electrical Characteristics Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit Parameter MAIN SMPS C ON TR OLLER S Input Voltage Range FB3, FB5 range - Adjustable Mode 3.3V Output - Fi xed Mode 5V Output - Fi xed Mode Output Voltage Adjust Range Adjustable Mode Threshold Load Regulati on Li ne Regulati on  2004 Semtech Corp. C onditions Min Typ Max U nits 6.0 V+ = 6.0 to 30V, C SLx = FBx, Output Load = 0A to current li mi t V+ = 6.0 to 30V, FB3 = 0V, 3V Load = 0A to current li mi t V+ = 6.0 to 30V, FB5 = 0V, 5V Load = 0A to current li mi t Ei ther SMPS Measured at FB3/FB5 Ei ther SMPS, 0A to current li mi t Ei ther SMPS, 6.0V < V+ 9.6 V 9.6V > Vin > 6.7V 6.7 > Vin P h ase l ead f r om 3V t o 5V r i si n g ed g e 41% of switching period. N o switching overlap between 3V and 5V. 59% of switching period. Small overlap to prevent simultaneous 3V/5V switching. 64% of switching period. Small overlap to prevent simultaneous 3V/5V switching. D3 D5 Iin I5in average 0 Icap 0  2004 Semtech Corp. 20 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) Input ripple current calculations: The following equations provide quick approximations for input ripple current: and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation: IF _ AVG = ILOAD ⋅ D3 = 3.3V / VIN = 3V duty cycle D5 = 5 V / VIN = 5V duty cycle 100n = 0.2A TS I3 = 3V DC load current I5 = 5V DC load current DOVL = overlapping duty cycle of the 3V and 5V pulses (varies according to input voltage) where 100nsec is the estimated time between the mosfet turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design. External Feedback Design In order to optimize the ripple voltage during Power Save mode, it is strongly recommended to use external voltage dividers (R10 and R9 for 5V power train; R8 and R11 for 3.3V power train) to achieve the required output voltages. In addition a 56pF (C22 for 5V and C21 for 3.3V) cap is recommended connecting from the output to both feedback pins (pin # 3 and #12). The signal-tonoise ratio is therefore increased due to the added zeros. DOVL = 0 for 9.6V ≤ VIN DOVL = (D5 - 0.41) for 6.7V ≤ VIN < 9.6V DOVL = (D5 - 0.36) for VIN < 6.7 IIN = Average DC input current IIN = I3 ⋅ D3 + I5 ⋅ D5 ISW _ RMS = RMS current drawn from VIN ISW _ RMS 2 = D3 ⋅ I32 + D5 ⋅ I52 + 2 ⋅ DOVL ⋅ I3 ⋅ I5 I RMS_CAP = I SW_RMS 2 + I IN_AVE 2 The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2A. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2A. Choosing Synchronous mosfet and Schottky Diode Since this is a buck topology, the voltage and current ratings of the synchronous mosfet are the same as the main switching mosfet. It makes sense cost- and volume-wise to use the same mosfet for the main switch as for the synchronous mosfet. Therefore, IRF7413 is used again in the design for synchronous mosfet. To improve overall efficiency, an external Schottky diode is used in parallel to the synchronous mosfet. The freewheeling current is going into the Schottky diode instead of the body diode of the synchronous mosfet, which usually has very high forward drop and slow transient behavior. It is really important when laying out the board to place both the synchronous mosfet and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the mosfet  2004 Semtech Corp. 21 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) Operation Below 6V input The SC1403 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1403, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. 2 - Minimize the resistance in the power train. Select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, mosfets and diodes, inductor, current sense resistor, and output capacitor. 4 - Minimize the resistance between the SC1403 circuit and the power source (battery, battery charger, AC adaptor). 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. PRELIMINARY Overvoltage Test Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous mosfets can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this enable the SC1403 PSAVE# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5, ON3 both enabled DVMs monitoring ON5 and the output under test Oscilloscope probe connected to Phase Node of the output under test (not strictly required) Set lab supply 2 to provide 10V at the SC1403 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. Slowly increase lab supply 1 until the output under test rises slightly above it’s normal DC level. As the input lab supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. Increase lab supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output. D1 e.g. 1N4004 Vin Output under test VL to DVM D2 D1 e.g. 1N4004 R1 75 1/2W 1K Lab Supply 1 Lab Supply 2 R2 470 1/2W SC1403 SC1403 Evaluation Board ON5 to DVM  2004 Semtech Corp. 22 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics 5V Line Regulation 5.03 5.02 5V@0A 5V@3A 5V@6A 5.01 Vout (V) 5.00 4.99 10 12 14 16 Vin (V) 18 20 22 24 3.3V Line Regulation 3.34 3.33 3.3V@ 0A 3.3V@ 3A 3.3V@ 6A 3.32 Vout (V) 3.31 10 12 14 16 Vin (V) 18 20 22 24  2004 Semtech Corp. 23 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 5V Load Regulation @Vin =19V 5.05 5.04 5.03 5.02 Vout (V) 5.01 5.00 4.99 4.98 4.97 4.96 0 1 2 3 Iout (A) 4 5 6 5V @25degC 5V @ 125degC 5V@ -45degC PRELIMINARY 5V Load Regulation @ Vin =10V 5.03 5.02 5.01 5.00 Vout (V) 5.0V@ 25degC 4.99 4.98 4.97 4.96 4.95 0 1 2 3 Iout (A)  2004 Semtech Corp. 24 United States Patent No. 6,377,032 www.semtech.com 5.0V@ 125degC 5.0V@ -45degC 4 5 6 SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 3.3V Load Regulation @ Vin = 19V 3.35 3.34 3.33 Vout (V) 3.3V@ 25degC 3.32 3.3V@ 125degC 3.3V@ -45degC 3.31 3.30 3.29 0 1 2 3 Iout (A) 4 5 6 3.3V Load Regulation @ Vin =10V 3.34 3.33 3.32 Vout (V) 3.3V@ 25degC 3.31 3.3V@ 125degC 3.3V@ -45degC 3.30 3.29 3.28 0 1 2 3 Iout (A) 4 5 6  2004 Semtech Corp. 25 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 5V Efficiency 97% PRELIMINARY 95% 93% Efficiency (%) 5V@ 19Vin 5V@ 10Vin 91% 89% 87% 85% 0.01 0.1 Iout (A) 1 10 3.3V Efficiency 95% 90% Efficiency (%) 85% 3.3V@ 19Vin 3.3V@ 10Vin 80% 75% 70% 0.01 0.1 Iout (A) 1 10  2004 Semtech Corp. 26 United States Patent No. 6,377,032 www.semtech.com VIN C2 C3 R1 10 BAT54A V+ VL D1 0.22uF C4 C1 10uF/25V 0.22uF 10uF/25V 10uF/25V C5 C6 10uF/25V C9 C10 8 7 6 5 D 5 6 7 8 3 2 1 1 2 3 5 6 7 8 30BQ015 IRF7413 D2 Q3 4 27 23 16 26 24 28 22 25 21 19 20 18 17 15 4 D 180uF/4V D 8 7 6 5 V+ VL 1 2 3 DL3 DL5 DH3 DH5 BST3 SHDN PGND PHASE3 PHASE5 RUN/ON3 3 2 1 C39 R23 NO_POP BST5 R19 1.3K SEQ CSH3 CSL3 FB3 COMP3 COMP5 SYNC TIME/ON5 GND REF PSAVE RESET FB5 CSL5 CSH5 1 2 3 4 5 6 7 8 9 10 11 12 13 C29 1uF 14 CMP3RC C14 zero_ohm CMP5RC T-ON5 VIN 0.01uF 5 6 7 8 C27 VIN 4 3 2 1  2004 Semtech Corp. Q2 0.1uF 4.7uF/35V 0.1uF C11 C12 Q1 4.7uF/16V 4 IRF7413 4 C15 R4 0 R5 0 0.22uF C16 D R6 L1 6.8uH 0.22uF IRF7413 L2 6.8uH POWER MANAGEMENT Evaluation Board Schematic 3_3V IRF7413 0.005 R20 1.3K R22 NO_POP C17 Q4 0.005 R7 NO_POP C18 D3 140T3 150uF/6.3V C19 D5 140T3 NO_POP C20 D4 30BQ015 1uF U1 SC1403 R8 1.58K C35 0.1uF C36 NO_POP C21 27 COMP3 R13 PSV# 100k R14 R15 R16 1k S1 VL R17 2M ON3 R12 2M 2M 2M COMP5 REF C25 1uF/16V C26 0.1uF RESET# COMP5 C37 0.01uF SHDN# R3 NO_POP 100pF C8 56pF R18 1.3K R21 1.3K C34 NO_POP C22 56pF C28 1uF C33 0.1uF FB5 R9 4.9 REF R11 R10 4.99K 4.99K VL COMP3 PSV# RESET# C7 100pF R2 NO_POP C13 zero_ohm Title Size B Date: SC1403 Evaluation Bo Document Number SC1403 United States Patent No. 6,377,032 www.semtech.com Monday, March 29, 2004 Sheet 1 SC1403 POWER MANAGEMENT Evaluation Board Bill of Materials PRELIMINARY Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 Quanity 4 4 2 2 1 1 1 1 2 2 2 4 1 2 2 2 1 Designation C1,C2,C5,C6 C3,C4,C15,C16 C7,C8 C9, C11 C 25, C 28, C 29 C 17 C 19 D1 D 3, D 5 D 2, D 4 L1, L2 Q1, Q2, Q3, Q4 R1 R4, R5 R6, R7 (resistive sensing only) R16 U1 Part Number GRM230Y5V106Z025 Description 10uF, 25V 0.22uF 100pF 4.7uF 1uF ceramic Manufacturer Murata C ase 1210 0806 0603 EEF-UE0G181R EEF-UE0J151R BAT54A MBRS140T3 30BQ015 DR127-6R8 IRF7413 180uF, 4V 150uF, 6.3V 30V, 200ma, dual anode 40V, 1A Schottky 15V, 3A Schottky SMT Inductor 6.8uH 30V N-channel MOSFET 10 ohm 0 ohm Panasonic Panasonic Zetex Motorola International Rectifier Coiltronics International Rectifier D _ C a se _ 7 3 4 3 D _ C a se _ 7 3 4 3 SOT-23 SMB SO8 603 603 WSL2512R005FB43 5mohm 1Kohm Vishay Dale 2512 603 SC463ITS Mobile PWM Controller with VCS Semtech TSSOP28  2004 Semtech Corp. 28 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Evaluation Board Layout Top Assembly Bottom Assembly  2004 Semtech Corp. 29 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Layout Guidelines As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting PCB layout, a careful layout strategy is strongly recommended. See the PCB layout in the SC1403 Evaluation Kit manual for example. In most applications, use FR4 with 4 or more layers and at least 2 ounce copper (for output current up to 6A). Use at least one inner layer for ground connection. It is always a good practice to tie signal-ground and power-ground at one single point so that the signal-ground is not easily contaminated. High current paths should have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following layout strategy should be used in order to fully utilize the potential of SC1403. A. Power train arrangement. Place power train components first. The following figure shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source of the upper switching FET and the drain of the synchronous rectifier meets, switches at very high rate of speed, and is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, therefore reducing the efficiency loss due to the current ramp-up and down time. This becomes extremely important when the converter needs to handle high di/ dt requirement. Vias between power components should be used only when necessary: if vias are required, use multiple vias to reduce the inter-component impedance, and keep the traces between vias and power components as short and wide as possible. L VOUT C OUT PRELIMINARY CSL R1 R2 C S C 1403 CSH With resistive sensing: minimize the length of current sense signal traces. Keep them less than 15mm. Use Kelvin connections as shown below; keep the traces parallel to each other and as close together as possible. L CSH S C 1403 CSL R sn s Q1 D1 Q2 L1 C. Gate Drive. The SC1403 has built-in gate drivers capable of sinking/sourcing 1A pk-pk. Upper gate drive signals are noisier than the lower ones, so place them away from sensitive analog circuits. Make sure the lower gate traces are as close as possible to the SC1403 pins, and make both upper and lower gate traces as wide as possible. D. PWM placement (pins) and signal ground island. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1403’s GND pin. This includes REF, FB3, FB5, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#. E. Ground plane arrangement. There are several ways to tie the different grounds together (analog ground, input power ground, and output power ground). With a buck topology, the output is quiet compared to the input side. The output is the best place to tie the analog ground to the power ground, often through a 0Ω resistor. The input power ground and the output power ground can be tied together using internal planes. 30 United States Patent No. 6,377,032 www.semtech.com B. Current Sense. With DCR sensing: The connections from the RC network to the inductor should be Kelvin connections directly at the inductor solder pads. Place the capacitor close to the CSH/CSL pins on the SC1403, and connect to the capacitor using short direct traces.  2004 Semtech Corp. SC1403 POWER MANAGEMENT Outline Drawing - TSSOP-28 Land Pattern - TSSOP-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2004 Semtech Corp. 31 United States Patent No. 6,377,032 www.semtech.com