SC1404ITSTR

Mobile Multi-Output PWM Controller with Virtual Current SenseTM POWER MANAGEMENT Description The SC1404 is a multiple-output power supply controller designed to power battery operated systems. The SC1404 provides synchronous rectified buck converter control for two power supplies. An efficiency of 95% can be achieved. The SC1404 uses Semtech’s proprietary Virtual Current SenseTM technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. The SC1404 also provides two linear regulators for system housekeeping. The 5V linear regulator takes its input from the battery; for efficiency, the output is switched to the 5V output when available. The 12V linear regulator output is generated from a coupled inductor off the 5V switching regulator. Control functions include: power up sequencing, soft start, powergood signaling, and frequency synchronization. Line and load regulation is to +/-1% of the output voltage. The internal oscillator can be adjusted to 200 kHz or 300 kHz or synchronized to an external clock. The MOSFET drivers provide >1A peak drive current for fast MOSFET switching. The SC1404 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. SC1404 Features 6 to 30V input range (operation possible below 6V) 3.3V and 5V dual synchronous outputs Fixed-frequency or PSAVE for maximum efficiency over wide load current range 5V/50mA linear regulator 12V/200mA linear regulator TM Virtual Current Sense for enhanced stability Accurate low-loss current limiting Out-of-phase switching reduces input capacitance External compensation supports wide range of output filter components for reduced cost Programmable power-up sequence Power Good output Output overvoltage & overcurrent protection with output undervoltage shutdown 4µA typical shutdown current 6mW typical quiescent power Applications Notebook and Subnotebook Computers Automotive Electronics Desktop DC-DC Converters Typical Application Circuit I P U T + 6V to + 30V N + 5V A LW A Y S O N 0.1uF U4 22 0.22uF V+ 6 21 + S C 1404 O N /O F F 10 4.7uF SYNC VL + 12V O U TP U T 12OUT VDD 4 5 + 4.7uF S C 1404 O N /O F F 23 3 C7 25 0.1uF SHDN COMP3 COMP5 12 C11 18 0.1uF + 2.2uF BST3 SC1404 BST5 0.1uF 27 26 + 3V O U TP U T L1 DH3 PHASE3 DH5 PHASE5 16 17 0.1uF T1 + 5V O U TP U T 24 + DL3 DL5 PGND 19 + 20 14 13 15 9 11 + 0.1uF 1 2 CSH3 CSL3 CSH5 CSL5 SEQ + 2.5V R E F 3V O N /O F F 5V O N /O F F 28 7 ON5 PSAVE RUN/ON3 GND REF RESET PO W ER G O O D Revision 4, July 2003 1 10 8 www.semtech.com SC1404 POWER MANAGEMENT Absolute Maximum Ratings PAR AMETER VD D , V+, PHASE3, PHASE5 to GND PHASE3, PHASE5 to GND BST3, BST5, D H3, D H5 to GND PGND to GND VL to GND BST3 to PHASE3; D H3 to PHASE3; BST5 to PHASE5; D H5 to PHASE5 D ESC R IPTION Supply and Phase Voltages Phase Voltages Boost voltages Power Ground to Si gnal Ground Logi c Supply Hi gh-si de Gate D ri ve Supply Hi gh-si de Gate D ri ve Outputs Low-si de Gate D ri ve Outputs and C urrent Sense i nputs Logi c i nputs/outputs MAXIMU M -0.3 to +30 -2.0 (transi ent - 100 nsec) -0.3 to +36 ± 0.3 -0.3 to +6 -0.3 to +6 -0.3 to (+BSTx + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(V+ + 0.3V) C onti nuous +5 +50 -0.3 to (+VD D + 0.3) C onti nuous 12V output current Juncti on Temperature Range juncti on to ambi ent Storage Temperature Range Lead Temperature +200 +150 76 -65 to +200 +300 °C , 10 second max. mA °C °C /Watt °C °C mA mA V PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. U N ITS V V V V V V V V V V D L3, D L5 to GND C SL5, C SH5, C SL3, C SH3 to GND REF, SYNC , SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, C OMP3, C OMP5 to GND ON3, SHD N# to GND VL, REF Short to GND REF C urrent VL C urrent 12OUT to GND 12OUT Short to GND 12OUT C urrent TJ Package Thermal Resi stance TS TL Electrical Characteristics Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit PAR AMETER CODE CONDITIONS MAIN SMPS CONTR OLLER S MI N T YP MAX UNITS Inp ut Voltage Range 3V Outp ut Voltage 5V Outp ut Voltage Load Regulation Line Regulation  2003 Semtech Corp. V IN V3OUT V5OUT V3LDRG V5LDRG V3LIRG V5LIRG V+ = 6.0 to 30V, 3V load = 0A to current limit V+ = 6.0 to 30V, 5V load = 0A to current limit Either SMPS, 0A to current limit, PSAVE# = VL Either SMPS, 6.0 < V+ < 30V, PSAVE# = VL 2 6 3.23 4.9 3.3 5.0 -0.4 0.05 30.0 3.37 5.1 V V V % % /V www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit PAR AMETER Current-Limit Thresholds (N ote 2) CODE I3LIMP I5LIMP I3LIMN I5LIMN ZC3 ZC5 CONDITIONS CSHX - CSLX (positive current) CSHX - CSLX (negative current) CSHX - CSLX PSAVE# = 0V, not tested From enable to 95% full current limit, with respect to fOSC MI N 40 T YP 55 -50 5 512 MAX 70 UNITS mV Zero Crossing Threshold Soft-Star t Ramp Time Oscillator Frequency Maximum Duty Factor SYN C Input High Pulse SYN C Input Low Pulse Width SYN C Rise/Fall Time SYN C Input Frequency Range Current-Sense Input Leakage Current mV clks 380 230 kHz % ns FOSCHI FOSCLO DF3MAX DF5MAX SYN C = VL SYN C = 0V SYN C = VL SYN C = 0V N ot tested N ot tested N ot tested 220 170 92 94 300 200 94 96 300 300 200 240 350 SYN CRG ICSH3 ICSH5 CSH3 = 3.3V, CSH5 = 5.0V ER R OR AMP kHz 10 µA 3 DC Loop Gain Gain Bandwidth Product Output Resistance DCG3, DCG5 From internal feedback node to COMP3/COMP5 18 8 V/V MHz Kohms RC3, RC5 COMP3, COMP5 INTER NAL R EGULATOR AND R EFER ENCE 25 VL Output Voltage VL Undervoltage Lockout Fault Threshold VL Switchover Lockout REF Output Voltage REF Load Regulation VLOUT V LU V VLSW REFOUT REFLD1 REFLD2 SHDN # = V+; 6V < V+ 9.6 V 9.6V > Vin > 6.7V 6.7 > Vin Phase lead from 3V conver ter rising edge to 5V conver ter rising edge 41% of switching p eriod 59% of switching p eriod 64% of switching p eriod The next figure shows out-of-phase switching. Since the 3.3V and 5V converters are spaced apart, there is no resulting overlap. This results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. The third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. The RMS value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced RMS current ratings. Out-of-phase Switching I3in Vin > 9.6V: 3.3V turn-on leads 5V turn-on by 41% of the switching period. With Vin > 9.6V it is always possible to achieve no overlap, which minimizes the input ripple current. At Vin = 9.6V there is no overlap, but the 3.3V turn-on is nearing the 5V turn-off. 6.7 < Vin < 9.6V: 3.3V turn-on leads 5V turn-on by 59% of the period. To prevent the 3V turn-on from coinciding with the 5V turn-off (which could adversely affect either output), the 5V pulse is delayed in time slightly such that the 3V turn-on occurs before the 5V turn-off. This creates a small overlap between the 3V turn-on and the 5V turn-off, with a resulting slight increase in RMS input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. Note that at Vin = 6.7, the 3V turn-off is nearing the 5V turn-on. 16 www.semtech.com I5in average Iin 0 Icap 0  2003 Semtech Corp. SC1404 POWER MANAGEMENT Typical Characteristics Vin < 6.7 volts: 3.3V turn-on leads 5V turn-on by 64% of the period. The 5V turn-on is delayed slightly more to add separation between the 3V turn-off and 5V turn-on. This leads to more overlap, but at this point overlap is unavoidable. Input ripple current calculations: The following equations provide quick approximations for input ripple current: D3 = 3.3V duty cycle = 3.3/Vin D5 = 5V duty cycle = 5/Vin I3 = 3.3V load current I5 = 5V load current Dovl = overlapping duty cycle of the 3V and 5V pulses, which varies according to input voltage: Vin > 9.6V: Dovl = 0 9.6V > Vin > 6.7V: Dovl = D5 - 0.41 6.7V > Vin Dovl = D5 - 0.36 Iin = D3 . I3 + D5 . I5 (average current drawn from Vin) Isw_rms = rms current flowing into 3V and 5V SMPS (Isw_rms)2 = Dovl . (I3 + I5)2 + (D3 - Dovl) . I32 + (D5 -Dovl) . I52 Irms_cap = Isw_rms + Iin 2 2 IF _ AVG = ILOAD ⋅ 100n = 0.2A TS where 100nsec is the estimated time between the MOSFET turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design. Operation below 6V input The SC1404 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1404, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. 2 - Minimize the resistance in the power train. Select MOSFETs, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, MOSFETS and diodes, inductor, current sense resistor, and output capacitor. 4 - Minimize the resistance between the SC1404 circuit and the power source (battery, battery charger, AC adaptor). 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2 amps. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2 Amps, allowing for derating at higher temperatures. Choosing Synchronous MOSFET and Schottky diode Since this is a buck topology, the voltage and current ratings of the synchronous MOSFET are similar to the high-side MOSFET. It makes sense cost-volume-wise to use the same MOSFET for both the main switch and synchronous MOSFET. Therefore, STS12NF30L is used again in the design for synchronous MOSFET. To improve overall efficiency, an external schottky diode is used in parallel to the synchronous MOSFET. The freewheeling current goes into the schottky diode instead of the body diode of the synchronous MOSFET, which usually has very high forward drop and slow transient behavior. It is important when laying out the board to place both the synchronous MOSFET and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the MOSFET and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation.  2003 Semtech Corp. 17 www.semtech.com SC1404 POWER MANAGEMENT 5V Start-up with slow Vin ramp. Proper startup of the 5V output can be hampered by slow dV/dt on the input. The SC1404 will power up and attempt to generate an output when the input voltage exceeds 4.5 volts. If the input has a slow dV/dt, the input voltage will not rise significantly during the start-up sequence, leading to two conditions. First, the VL supply can be hundreds of mV below 5V, since the input may not yet be above 5V. Second, the duty cycle will be at maximum, leading to very small off-times. These two conditions tend to reduce the BOOST voltage; if continued indefinitely, the BOOST capacitor may be unable to recharge fully, and eventually the high-side driver loses its BOOST bias. To avoid this the following steps should be taken: The following guidelines for 12V loading apply to the typical circuit, page 22. PRELIMINARY Vin range >10V 7V - 10V 12V load conditions 12V load < 1/2 * 5V load 12V load = 200mA max 12V load < 1/2 * 5V load Linearly derate 12V load: 200mA at 10V 100mA at 7V 12V load < 1/2 * 5V load Linearly derate 12V load: 100mA at 10V 25mA at 7V 6V - 7V 1. If possible the dV/dt of the input supply should exceed .02V/ usec. This dV/dt condition only applies when the input passes between 4 and 6 volts, the point at which the SC1404 begins a startup sequence. An alternative is to make sure the input voltage reaches 6 volts within 100 usec of SC1404 startup at approximately 4.2 volts. This is sufficiently fast to allow VL and duty cycle to achieve normal levels and will prevents the BOOST voltage from falling. 2. If the dV/dt of the input cannot meet condition 1, the startup of the SC1404 should be delayed until the input voltage reaches 6V. This can be done using either the SHDN# or ON5 pin. If the dV/dt is moderate (slews from 4 to 6 volts in several msecs), an RC delay on either the SHDN# or ON5 pin should be enough to delay turn-on until the input reaches 6V. 3. For slow dV/dt on the input (10’s of msec), the SC1404 should be held off until the input reaches 6V. This can be done using a comparator or external logic to hold the SHDN# or ON5 pin low until the input reaches 6V. 12V Load Limitations The 12V regulator derives input power from a secondary winding on the 5V inductor. During the 5V off-time, the inductor transfers energy from the 5V winding to the secondary winding, thereby providing a crudely regulated 15V that feeds the 12V regulator. Note that duty cycle increases at low input voltages, and therefore the on-time decreases. At low input voltages, the duty cycle increases to maintain the 5V output. The off-time consequently decreases, which has two detrimental effects. It allows less time to recharge the raw 15V capacitor, and it also raises the peak 15V current required to maintain the average 12V load. The 15V winding needs higher peak current, delivered in less time. But the stray (leakage) inductance of the inductor resists rapid changes in winding current, and ultimately limits how much current can be drawn from 15V before the voltage falls. PSAVE operation The SC1404 enters power-save operation if the load is sufficiently light, and if PSAVE is tied low. In PSAVE operation, the switching frequency is no longer fixed, and the converter operates as a hysteretic converter. This reduces gate drive losses and other switching losses to improve efficiency. Each converter willl enter or exit PSAVE operation independently, based on load current. The hysteresis (output ripple) on the 5V output is typically 70mV, and the 3V hysteresis is typically 35mV.  2003 Semtech Corp. 18 www.semtech.com SC1404 POWER MANAGEMENT Overvoltage Test Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous MOSFETS can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this, enable the SC1404 PSAVE# feature, which effectively disables the low side MOSFET drive so that little energy, if any, is transferred back to the input. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5 enabled ON3 enabled DVMs monitoring ON5 and the output under test. Oscilloscope probe connected to Phase Node of the output under test (not strictly required). Set Lab Supply 2 to provide 10V at the SC1404 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. Slowly increase Lab Supply 1 until the output under test rises slightly above it’s normal DC level. As Lab Supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. Increase Lab Supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output. to DVM D1 e.g. 1N4004 R1 75 1/2W 1K Lab Supply 1 D1 e.g. 1N4004 Vin Output under test VL Lab Supply 2 R2 470 1/2W SC1404 Evaluation Board ON5 to DVM  2003 Semtech Corp. 19 www.semtech.com SC1404 POWER MANAGEMENT Layout Guidelines As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting to layout the PCB, a careful layout strategy is strongly recommended. See the PCB layout in the SC1404 Evaluation Kit manual for example. In most applications, we recommend to use FR4 with 4 or more layers and at least 2 oz copper (for output current up to 6A). Use at least one inner layer for ground connection. And it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contaminated. Also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following step by step layout strategy should be used in order to fully utilize the potential of SC1404. Step #1. Power train components placement. a. Power train arrangement. Place power train components first. The figure below shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source c. Gate Drive. SC1404 has built-in gate drivers capable of sinking/sourcing 1A peaks. Upper gate drive signals are noisier than the lower ones. Therefore, place them away from sensitive analog circuitries. Make sure the lower gate traces are as close as possible to the IC pins and both upper and lower gate traces as wide as possible. Step #2: PWM controller placement (pins) and signal ground island. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1404’s GND pin. This includes REF, COMP3, COMP5, SYNC, RUN/ON3, ON5, PSV# and RESET#. of the upper switching FET and the drain of the synchronous rectifier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, to reduce the efficiency loss due to the current rampup and down time. This becomes extremely important when the converter needs to handle high di/dt requirements. Step #3: Ground plane arrangement. There are several ways to tie the different grounds together. Since this is a buck topology converter, the output ground is relatively quieter than the input ground. Therefore connect analog ground to power ground at the output side. Often it is useful to use a separate ground symbol for the two grounds, and tie the two grounds together at a single point through a 0Ω resistor. The power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes. 20 www.semtech.com PRELIMINARY b. Current Sense. Minimize the length of current sense signal trace. Keep it less than 15mm. Kelvin connections should be used; try to keep the traces parallel to each other and route them close to each other as much as possible. Even though SC1404 implements Virtual Current Sense scheme, the current sense signal is sampled by the SC1404 to determine the PSAVE threshold. See the following figure for a Kelvin connection of the current sense signal. L1 SC1404 CSH CSL Rcs Q1 D1 Q2 L1  2003 Semtech Corp. SC1404 POWER MANAGEMENT Typical Characteristics 3.3V Efficiency 100 Efficiency (%) 90 80 70 60 50 0.01 0.1 1 10 Load Current (A) 6V 10V 19V 5V Efficiency 100 Efficiency (%) 95 90 85 80 0.01 0.1 6V 10V 19V 1 10 Load Current (A)  2003 Semtech Corp. 21 www.semtech.com NEG J24 R1 2 10 2 1 BAT54A JP4 1 VL 8 7 6 5 C13 100pF C14 100pF V+ J27 V+ D1 1 1 COMP3 COMP5 C3 0.22uF 1 C4 0.22uF 2 2 2 1 1 1 GND GND GND 1 5 6 7 8 7 1 3 2 1 1 C15 1 2 3 2 LX3 2 DL3 T/L2 TTI8215 8 7 6 5 DL5 D J6 2 5 6 7 8 LX5 0 0.22uF 1 10 6 5 0.22uF R5 C16 B_JACK_PAIR LX3 R4 0 1 BST5 J23 LX5 POS D 1 3_3V R6 R7 0.005 1 L1 4 3_3V J22 4 DH3 1 NEG 2 IRF7413 BST3R BST5R 30BQ015 A C C C C 23 22 28 26 21 20 25 24 27 19 18 17 16 15 D3 140T3 4 SEQ A R22 0 Ohm V+ VL 1 2 3 DL3 DL5 DH3 DH5 BST3 SHDN PGND R19 NO_POP A BST5 SEQ PHASE3 PHASE5 RUN/ON3 3 2 1 C39 1uF R23 0 ohm D5 140T3 J19 1 VL CSH5 2 A NO_POP C20 D4 30BQ015 J20 R21 NO_POP 1 CSL5 U1 2 JP1 1 1 CSL5 CSH5 1 JP2 2 JP3 CSL3 COMP3 12OUT VDD SYNC TIME/ON5 GND REF PSAVE RESET COMP5 J17 1 2 3 4 5 6 7 8 12 13 10 11 14 1 9 CSH3 CSH3 COMP3 RESET# REF SY NC ON3 1 2 R13 2M 1 1 1 R16 1k R17 5 4 3 2 1 S1 DIP_SW5_PTH VIN 6 7 8 9 10 VL C27 0.01uF VIN 2 T-ON5 2M 1 2 R15 2M 2 SHDN# 1 R14 2M 2 R12 2M 2 VDD PSV# C25 1uF/16V C26 0.1uF COMP5 CSH5 J21 1 CSL3 C29 NO_POP C35 0.1uF C36 0.1uF CSH3 22 SC1404ITS C34 0.1uF C43 NO_POP C37 0.01uF C38 1uF R18 NO_POP C28 NO_POP C33 0.1uF +12V J25 1 +12V 2 1 1 NEG  2003 Semtech Corp. VDD VIN B_JACK_PAIR J1 C5 10uF/25V C6 10uF/25V POS 1 VIN 2 2 1 VIN C1 10uF/25V 1 1 C2 10uF/25V J2 J3 J4 J5 GND C9 4.7uF/35V 4.7uF/16V C10 0.1uF POWER MANAGEMENT Evaluation Board Schematic C11 D C12 0.1uF Q1 IRF7413 DH5 4 D6 MBRS1100T3 Q2 IRF7413 BST3 4.7uF/25V C41 NO_POP D J16 C42 3_3V 1 0.005 6.8uH J18 1 5V 5V J7 B_JACK_PAIR 5V 180uF/4V Q3 4 NO_POP C17 IRF7413 Q4 R20 D2 NO_POP C18 150uF/6.3V 1 POS C19 RESET# J12 RESET# J8 REF REF J10 1 GND J26 C22 1 4.7uF/16V C40 0.1uF PSV# SYNC J9 1 ON3 1 J11 T-ON5 1 J13 1 VL VL J14 SHDN# 1 J15 SC1404 EVB Schematic PRELIMINARY SC1404 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Bill of Materials ITEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 2 1 QT Y 4 1 DESIGNATION C1,C2,C5,C6 C3, C4, C15, C16 C9 C10,C12,C26,C33,C34,C35,C36,C40 C11,C22 C14,C13 C17 C19 C25 C37,C27 C39,C38 C42 D1 D2, D4 D3, D5 D6 BAT54A 30BQ015 MBRS140T3 MBRS1100T3 40V, 1A Schottky Y475M250N ECJ1VC1H101K EEF-UE0G181R EEF-UE0J151R ECJ3FB1C105 ECJ1VB1C104K PAR T NUMBER GRM230Y5V106Z025 DESCR IPTION 10uF, 25V 0.22uF, 50V, Y5V 4.7uF, 35V 0.1uF,50V, X7R 4.7uF, 16V 100pF, 50V 180uF, 4V 150uF, 6.3V 1uF, 16V 0.01uF, 50V 1uF 4.7uF, 25V 30V, 200ma, dual C_Anode Zetex I. R . Motorola Motorola SOT-23 SMC SMB SMB Panasonic N ovacap Panasonic Panasonic Panasonic Panasonic Panasonic MANUFACTUR ER Murata Panasonic FOR M FACTOR 1210 805 B_case 0603 1812 0603 D_Case_7343 D_Case_7343 1206 0603 0603  2003 Semtech Corp. 23 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Bill of Materials Cont. ITEM 17 18 19 20 21 22 23 24 25 26 27 28 29 QT Y 4 3 24 1 4 1 4 2 5 1 1 DESIGNATION JP1, JP2, JP3, JP4 J1, J6, J7 J2-J5, J8-J27 L1 Q1, Q2, Q3, Q4 R1 R4, R5, R22, R23 R6, R7 R12, R13, R14, R15, R17 R16 SW1 T/L2 U1 TTI-8215 SC1404ITS DR127-6R8 IRF7413 Any Any WSL2512R005FB43 Any Any PART NUMBER DESCRIPTION 2 Pin Berg Connector Banana Jack Pair Test Points SMT Inductor 6.8uH 30V N-channel MOSFET 10ohm 0ohm 5mohm 2Megohm 1Kohm 5-position Dipswitch Coiltronics International Rectifier A ny A ny Vishay Dale A ny A ny Any Transpower Technologies Semtech SO8 0603 0603 2512 0603 0603 PRELIMINARY MANUFACTURER FORM FACTOR Berg 1 1  2003 Semtech Corp. 24 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Gerber Plots To p Inner2 Inner1 Bottom  2003 Semtech Corp. 25 www.semtech.com SC1404 POWER MANAGEMENT Outline Drawing - SSOP-28 PRELIMINARY  2003 Semtech Corp. 26 www.semtech.com SC1404 POWER MANAGEMENT Outline Drawing - TSSOP-28 Land Pattern - TSSOP-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2003 Semtech Corp. 27 www.semtech.com