SC1405TS.TR

HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1405 is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through from VIN to GND in the main switching and synchronous MOSFET’s. Each driver is capable of driving a 3000pF load in 20ns rise/fall time and has ULTRAFAST propagation delay from input transition to the gate of the power FET’s. The Overlap Protection circuit ensures that the second FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning to high is externally programmable via a capacitor for optimal reduction of switching losses at the operating frequency. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET’s gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output OverVoltage protection circuitry, independent of the PWM feedback loop. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low when the 5V logic level is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in stand-by mode thereby reducing supply current to less than 10µA. SC1405 is offered in a high pitch (.025” lead spacing) TSSOP package. FEATURES •= Fast rise and fall times (20ns typical with 3000pf •= •= •= •= •= •= •= •= •= load) 20ns max. Propagation delay (BG going low) Adaptive/programmable shoot-through protection Wide input voltage range (4.5-25V) Programmable delay between MOSFET’s Power saving asynchronous mode control Output overvoltage protection/overtemp shutdown Under-Voltage lock-out and power ready signal Less than 10µA stand-by current (EN=low) Power ready output signal APPLICATIONS •= High Density/Fast transient power supplies •= Motor Drives/Class-D amps •= High frequency (to 1.2 MHz) operation allows use •= of small inductors and low cost caps in place of electrolytics Portable computers ORDERING INFORMATION DEVICE (1) PACKAGE TSSOP-14 TEMP. RANGE (TJ) 0 - 125°C SC1405TS.TR Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. PIN CONFIGURATION BLOCK DIAGRAM Top View (14-Pin TSSOP) 1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 ABSOLUTE MAXIMUM RATINGS Parameter VCC Supply Voltage BST to PGND BST to DRN DRN to PGND OVP_S to PGND Input pin Continuous Power Dissipation Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 sec NOTE: (1) Specification refers to application circuit in Figure 1. Symbol VMAX5V VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXOVP_S-PGND CO Pd θJC θJA TJ TSTG TLEAD Conditions Maximum 7 30 7 25 10 -0.3 to 7.3 0.66 2.56 40 150 0 to +125 -65 to +150 300 Units V V V V V V W °C/W °C/W °C °C °C Tamb = 25°C, TJ = 125°C Tcase = 25°C, TJ = 125°C ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V PARAMETER POWER SUPPLY Supply Voltage Quiescent Current Quiescent Current, operating PRDY High Level Output Voltage Low Level Output Voltage DSPS_DR High Level Output Voltage Low Level Output Voltage UNDER-VOLTAGE LOCKOUT Start Threshold Hysteresis Logic Active Threshold VSTART VhysUVLO VACT EN is low 4.2 4.4 0.05 1.5 4.6 V V V VOH VOL VCC = 4.6V, Cload = 100pF VCC = 4.6V, Cload = 100pF 4.15 0.05 V V VOH VOL VCC = 4.6V, lload = 10mA VCC < UVLO threshold, lload = 10µA 4.5 4.55 0.1 0.2 V V VCC Iq_stby Iq_op VCC EN = 0V VCC = 5V,CO=0V 1 4.15 5 6.0 10 V µA ma SYMBOL CONDITIONS MIN TYP MAX UNITS 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont. PARAMETER OVERVOLTAGE PROTECTION Trip Threshold Hysteresis S_MOD High Level Input Voltage Low Level Input Voltage ENABLE High Level Input Voltage Low Level Input Voltage CO High Level Input Voltage Low Level Input Voltage THERMAL SHUTDOWN Over Temperature Trip Point Hysteresis HIGH-SIDE DRIVER Peak Output Current Output Resistance IPKH RsrcTG RsinkTG LOW-SIDE DRIVER Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100µs, TJ = 125°C VV_5 = 4.6V, VBG = 4V (src), or VLOWDR = 0.5V (sink) 2 2 2 A Ω Ω duty cycle < 2%, tpw < 100µs, TJ = 125°C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN 1.5 1.4 A Ω Ω TOTP THYST 165 10 °C °C VIH VIL 2.0 0.8 V V VIH VIL 2.0 0.8 V V VIH VIL 2.0 0.8 V V VTRIP VhysOVP 1.145 1.2 0.8 1.255 V V SYMBOL CONDITIONS MIN TYP MAX UNITS 1.4 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC OPERATING SPECIFICATIONS HIGH-SIDE DRIVER rise time fall time propagation delay time, TG going high propagation delay time, TG going low LOW-SIDE DRIVER rise time fall time propagation delay time BG going high progagation delay time BG going low UNDER-VOLTAGE LOCKOUT V_5 ramping up V_5 ramping down PRDY EN is transitioning from low to high EN is transitioning from high to low DSPS_DR rise/fall time propagation delay, DSPS_DR going high propagation delay DSPS_DR goes low OVERVOLTAGE PROTECTION propagation delay OVP_S going high tpdhOVP_S V_5 = 4.6V, TJ = 125°C, OVP_S > 1.2V to BG > 90% of V_5 1 µs trDSPS_DR, tfDSPS_DR tpdhDSPS_DR tpdlDSPS_DR CI = 100pf, V_5 = 4.6V, S_MOD goes high and BG goes high or S_MOD goes low S_MOD goes high and BG goes low 20 10 10 ns ns ns tpdhPRDY V_5 > UVLO threshold, Delay measured from EN > 2.0V to PRDY > 3.5V V_5 > UVLO threshold. Delay measured from EN < 0.8V tp PRDY < 10% of V_5 10 µs tpdhUVLO tpdlUVLO EN is High EN is High 10 10 us us trBG trBG tpdhBGHI tpdlBG CI = 3nF, VV_5 = 4.6V, CI = 3nF, VV_5 = 4.6V, CI = 3nF, VV_5 = 4.6V, DRN < 1V CI = 3nF, VV_5 = 4.6V, 20 18 45 12 32 29 72 20 ns ns ns ns trTG, tfTG tpdhTG tpdlTG CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 CI = 3nF, VBST - VDRN = 4.6V, 16 17 35 25 25 27 56 40 ns ns ns ns tpdhUVLO 500 µs Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. © 2000 SEMTECH CORP. 4 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 PIN DESCRIPTION Pin # 1 2 Pin Name OVP_S EN Pin Function Overvoltage protection sense. External scaling resistors required to set protection threshold. When high, this pin enables the internal circuitry of the device. When low, TG, BG and PRDY are forced low and the supply current (5V) is less than 10µA. Logic GND. TTL-level input signal to the MOSFET drivers. When low, this signal forces BG to be low. When high, BG is not a function of this signal. Sets the additional propagation delay for BG going low to TG going high. Total propagation delay= 20ns + 1ns/pF. This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this output is driven low. When 5V is greater than or equals to 4.4V(typ) this output is driven to 5V level. This output has a 10mA drive capability and 10µA sink capability. +5V supply. A .22-1µF ceramic capacitor should be connected from 5V to PGND very close to this pin. Output drive for the synchronous MOSFET. Power ground. Connect to the synchronous FET power ground. Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD is high, this pin follows the BG driver pin voltage. This pin connects to the junction of the switching and synchronous MOSFET’s. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1µF and 1µF (ceramic). 3 4 5 6 7 GND CO S_MOD DELAY_C PRDY 8 9 10 11 12 VCC BG PGND DSPS_DR DRN 13 14 TG BST NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. PIN CONFIGURATION 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER August 31, 2000 SC1405 APPLICATION CIRCUIT Typical Distributed Power Supply INPUT POWER + D1 +5V 10uF,6.3V + .1uF 8 3 > P_READY PWM IN (20KHz-1MHz) 47pF 5 7 2 4 6 1 1N5819 .22uF Vcc GND BST 14 13 12 9 11 10 2.2 2.2 MTB75N03 75A,30V + + + + + MTB75N03 75A,30V TG PRDY EN DRN CO DELAY_C BG OVP_S DSPS_DR S_MOD PGND SC1405