SC1406A

PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1406A is a High Speed, High performance Hysteretic Mode controller. It is part of a two chip solution, with the SC1405 Smart Driver, providing power to advanced micro-processors. It uses a Dynamic Set Point switching technique along with an ultra-fast comparator to provide the control signal to an external high speed Mosfet driver. A 5-bit DAC sets the output voltage, thus providing a voltage resolution of 25mV. SC1406A has two on-chip linear regulators which drive external PNP transistors with output voltage settings of 1.5V and 2.5Vdc. The linear regulator drivers have a separate soft start. A PWRGD TTL level signal is asserted when all voltages are within specifications. The part features Low Battery Detect and Undervoltage Lock-Out for the main Hysteretic controller to assure V-DC is within acceptable limits. An Over-Current comparator disables the main controller during an overcurrent condition using an externally programmable threshold. FEATURES • • • • High Speed Hysteretic controller provides high efficiency over a wide operating load range Inherently stable Complete power solution with two LDO drivers ® Programmable output voltage for Pentium II & III Processors APPLICATIONS • • • Laptop and Notebook computers High performance Microprocessor based systems High efficiency distributed power supplies ORDERING INFORMATION DEVICE SC1406ACTS PACKAGE TSSOP-28 TEMP. (T J) 0 - 125°C BLOCK DIAGRAM PIN CONFIGURATION Top View TSSOP-28 Pentium is a registered trademark of Intel Corporation 1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name Pin Function HYS CLSET VCOUT VCIN VCBYP VID4 VID3 VID2 VID1 VID0 BASE25 FB25 BASE15 FB15 EN Core comparator hysteresis settling. Current limit setting pin. Voltage clamp output. Voltage clamp input. Voltage clamp bypass pin. Needs to have a 1500pF cap from this pin to ground to ensure proper operation. VID most significant bit main controller voltage programming DAC input. VID input VID input VID input VID least significant bit main controller voltage programming DAC input. 2.5V Linear regulator drive. 2.5V Linear regulator output feedback. 1.5V Linear regulator drive. 1.5V Linear regulator output feedback. Enable. SC1406A is enabled when this signal is High. This is capable of accepting 5.0V signal level. When used with the SC1405 driver, this pin can be connected to the PWRDY pin of the SC1405 to include UVLO feature on the V_5 (Intel Smart Driver’s VCC). Power Good. When the main converter output approaches and stays within ±12% of the VID DAC setting, and both soft-start circuits periods for the main core controller and linear regulator controllers have been terminated, this signal is driven high to VCC level. During UVLO, this signal is undefined. Low battery input. This pin is used to set the minimum voltage to the converter through an external resistor divider. When the input to this pin is less than 1.225V, typical, Tamky is held in an Under-Voltage-Lock-Out mode regardless of the status of EN. Linear regulators soft start. During power-up with EN high and not in UVLO, the external soft start capacitor (1200pF, typ) is charged by an internal 1µA current source to set the ramp up time of the linear regulator outputs, 1.5V and 2.5V. This ramp up time is typically 2ms, 6ms max. This is discharged through an internal switch when BIASEN is low, EN low or enter UVLO region. Enabling internal bias and soft start requires the pin voltage to drop below a threshold of 150mV typical (200mV max). Linear regulator soft start current tolerance tracks the core soft start current within 10%. 16 PWRGD 17 LBIN 18 SSLR 19 SSCORE Main controller CORE output soft start. During power-up with EN high and not in UVLO, the external soft start capacitor (1800pF, typ) is charged by an internal 1µA current source to set the ramp up time of the main converter output. This ramp up time is typically 3ms, 6ms max. This is discharged by an internal switch when BIASEN is low, EN pin is low or in UVLO. Enabling internal bias and soft start requires the pin voltage to drop below a threshold of 150mV typical (200mV max). Core soft start current tolerance tracks the LDO soft start current to within 10%. Pentium is a registered trademark of Intel Corporation 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A PIN DESCRIPTION (Cont.) Pin Pin Name Pin Function 20 21 22 23 24 25 26 27 28 CORE DAC GND CO VCC CMP CL CLREF Main CORE converter output feedback. Main controller digital to analog output. Ground Comparator output. Main regulator controller output used to drive the input of the SC1405 driver IC. Input power. Supply voltage input. This input is capable of accepting 3.3V or 5.0V supply voltage. Core comparator input pin. Current limit input pin. Current limit reference input pin. CMPREF Core comparator reference input pin. Pentium is a registered trademark of Intel Corporation 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A ABSOLUTE MAXIMUM RATINGS PARAMETER VCC Supply Voltage Low Battery Input Input & Output Pins Enable Operating Junction Temperature Lead Temperature (Soldering) 10 seconds Storage Temperature EN TJ TL TSTG SYMBOL VmaxVCC LBIN MAXIMUM 7 7 VCC + 0.3 GND - 0.3 7 0 to +125 300 -65 to 150 UNITS V V V V °C °C °C ELECTRICAL CHARACTERISTICS Unless specified: 0 < TA < 100°C; VCC = 3.3V (See Note 1) PARAMETER SYMBOL CONDITIONS SUPPLY, BIAS, UVLO, VDC MONITOR AND POWERGOOD Supply (VCC, GND) VCC Supply Voltage VCCMAX Range VCC Quiescent Current ICCQ EN is low, 3.0V < VCC < 3.6V EN is high and in UVLO VCC Operating Current ICC EN is high Under Voltage Lock Out Circuit Threshold VHCC Hysteresis Enable Input Input High Input Low Low Battery Monitor Threshold Input Bias Current VTHDC IBDC VLCC VHYSTCC Vih Vil 3.0 < VCC < 5V MIN TYP MAX UNITS 3.0 3.3 6.0 10 350 15 2.95 V µA mA V mV V 10.0 2.7 20 0.7*VCC 0.8 1.175 VLB_IN > VTHDC VLB_IN < VTHDC 0.6 1.08*VCC 1.0 1.225 1.275 ±0.3 10.5 1.12*VCC 0.92*VCC V V µA VCORE Power Good Generator Input Threshold VHCORE Output Voltage Note that during the latency time of any VID code change, the PWRGD output signal is not valid VLCORE VHPWRGD (Active Hi) VLPWRGD (Active low) VPWRGD VOUT VDAC = 0.9V - 1.675V V V V V V 0.88*VCC IPWRGD = 10µa (source) EN is high 0.95* VCC IPWRGD = 10µA (sink), EN is high IPWRGD = 10µA (sink), UVLO During the latency time (50µs) of any VID code change 0.4 0.8 Note 1: Specification refers to application circuit (Figure 1.). Pentium is a registered trademark of Intel Corporation 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A ELECTRICAL CHARACTERISTICS (CONT.) Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit) PARAMETER Core Converter Soft Start Current Core Converter Soft Start Current SYMBOL CONDITIONS CORE CONVERTER CONTROLLER ISSCORE VSSTERM VSSDIS VVID_IH VVID_IL IVID VDAC_ERR tpdVID_DAC 3.0V < VCC < 3.6V VID (0-4) = 00000...11111 IDAC = 0, VID(0-4) = 00000...11111 Charge (Source) current Discharge (Sink) current MIN TYP MAX UNITS 0.6 0.30 1.53 1 1 1.70 150 1.45 µA mA VSSCORE Soft Start Termination Threshold VSSCORE Discharge Threshold VID DAC VID Input Threshold VID Input-Pull-up Current,VID (0-4) Output Voltage Accuracy Settling Time* 1.87 400 V mV V 0.7*VCC 0.8 6 -0.85 40 +0.85 35 µA % µs CDAC = 1000pF VID is set to change VCORE from 1.30V to 1.45V or 1.45V to 1.30V CORE Comparator (CMP, CMPREF, HYS, CO) Input Bias Current IBCMP VCPMVCPMREF VCMP = VCMPREF = 1.3V VCMPREF = 1.3V RHYS = open ±1.5 ±2 ±3 +2 ±85 ±7 2.5 0.4 +100 +115 +10 +13 µA mV Input Offset Voltage Hysteresis Setting Current ICMPREF Output Voltage VHCO CMPCMPREF Propagation Delay Time** Measured at device pins, from the trip point to 50% of CO transition. Tpd CMP-CO 20 30 ns 20 30 7 10 ns 7 10 Output Rise/Fall Times** Measured between 30% and 70% points of CO transition TR TF Pentium is a registered trademark of Intel Corporation 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A ELECTRICAL CHARACTERISTICS (CONT.) Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Limit Comparator (CL, CLREF, CLSET) Input Bias Current Current Limit Setting Current *The Tamky device is required to meet the CL setting current requirements for RCLSET of “17kΩ and 170kΩ or “42.5kΩ and 20kΩ”. Supplier production testing will use the 17kΩ /170kΩ combination or the 42.5kΩ /20kΩ combination. +ICL |+ICLREF| VCS = 1.3V RCLSET = open VCLREF-VCL = 10mV VCLRER-VCL = -10mV VCLREF-VCL 262.5 = 10mV VCLREF-VCL 175 = -10mV VCLREF-VCL 19.5 = 10mV VCLREF-VCL 13 = -10mV VCLRER-VCL 100.5 = 10mV VCLRER-VCL 67 = -10mV VCLREF-VCL = 10mV VCLRER-VCL = -10mV 222 148 5 7.5 µA 5.0 300 200 30 20 120 80 255 170 ±4 337.5 225 40.5 27 139.5 93 288 192 ±6 mV µA µA µA µA µA RCLSET = 17kΩ∗ RCLSET = 170kΩ∗ RCLSET = 42.5kΩ∗ RCLSET = 20kΩ∗ Input Offset Voltage Propagation Delay Time** Measured at the device pins, from the trip point to 50% of CO transition VCL VCLREF Tpd_CL-CO VCLREF = 1.3V VCMPREF = 1.3V, ∆ VCMP = +50mV step with +20mV overdrive, TA = 25°C, TA = f ull range VCMPREF = 1.3V, ∆ VCMP = -50mV step with -20mV overdrive, TA = 25°C, TA = f ull range 100 150 ns 100 150 Pentium is a registered trademark of Intel Corporation 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A ELECTRICAL CHARACTERISTICS (CONT.) Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit) PARAMETER 1.5V Linear Regulator Controller Input Bias Current Output Voltage CO_1.5 = 56µF, 20mΩ ESR max or 150µF, 45mΩ ESR max Capacitance tolerance = 20% Base Drive Output Current 2.5V Linear Regulator Controller Input Bias Current Output Voltage CO_2.5 = 1µFceramic ESR range = 1mΩ − 30mΩ Capacitance tolerance = 20% Base Drive Output Current SYMBOL CONDITIONS MIN TYP MAX UNIT LINEAR REGULATOR CONTROLLERS ILR15 VO_1.5, Imin = 0.1mA IBASE_1.5 ILR25 VFB_15 = 1.5V IO = 500mA, pnp BJT with BMIN > 50 @ 1.47 1.50 IC = 500mA 1 1.54 mA V @ 25°C VFB_25 = 2.5V IO = Imax, pnp BJT with BMIN > 50 @ IC = 100mA 10 120 1 mA mA V VO_2.5, Imin = 0A Imax=0.1A 2.45 2.50 2.55 IBASE_2.5 ILRSS Charge Current, VLRSS = 0V Discharge Current, VLRSS = 1.50V, EN is low or in UVLO 2.5 -0.6 0.3 -1 1 150 1.53 1.70 20 mA µA mA Linear Regulator Soft Start (LRSS) Linear Reg Soft-Start Current Enable Threshold Soft Start Termination Threshold VSSLR_EN VTH_LRSS 400 1.87 mV V Voltage Clamp (VCIN, VCOUT, VCBYP) Input Voltage Output Voltage Imin = 10µA VH_VCIN VH_VCOUT RVCOUT = 150Ω tied to VS = 2.5V IVCIN = -10µA 0.93 VCIN is open 0.8VS 1.5 1.60 VS V V VL_VCOUT Progagation Delay** Tpd VCIN_VCOUT VVCIN = 0.175V RVCOUT = 150Ω tied to VS = 2.5V CVCBYP = 1500pF, VCIN steps from 0.175V to 1.50V and back. Measured from 50% of VCIN step to 50% of VCOUT transient 0.375 10 ns * Guaranteed by design. **Guaranteed by characterization. Pentium is a registered trademark of Intel Corporation 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A VID vs. VDAC VOLTAGE VID 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MIN 1% < VO 1.658 1.633 1.609 1.584 1.560 1.534 1.510 1.485 1.460 1.435 1.411 1.386 1.361 1.336 1.312 1.287 1.262 1.237 1.213 1.188 1.163 1.138 1.114 1.089 1.064 1.039 1.015 0.99 0.965 0.940 0.916 0.891 TYP VO 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.00 0.975 0.950 0.925 0.900 MAX 1% > VO 1.692 1.666 1.641 1.616 1.591 1.565 1.540 1.515 1.490 1.464 1.439 1.414 1.389 1.363 1.338 1.313 1.288 1.262 1.237 1.212 1.187 1.161 1.136 1.111 1.086 1.060 1.035 1.01 0.984 0.959 0.934 0.909 8 Pentium is a registered trademark of Intel Corporation © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 ® SC1406A FUNCTIONAL DESCRIPTION SUPPLY The chip is optimized to operate from a 3.3V + 5% rail but is also designed to work up to 6V maximum supply voltage. If VCC is out of the 3.3V + 5% voltage range, the quiescent current will increase somewhat and slight degradation of line regulation is expected. UNDER VOLTAGE LOCK-OUT CIRCUIT The under voltage lockout circuit consists of two comparators, the low battery and low VCC (low supply voltage) comparators. The output of the comparator gated with the Enable signal turns on or off the internal bias, enables or disables the CO output, and initiates or resets the soft start timers. POWER GOOD GENERATOR If the chip is enabled but not in UVLO condition, and the core voltage gets within +10% of the VID programmed value, then a high level Power Good signal is generated on the PWRGD pin to trigger the CPU power up sequence. If the chip is either disabled or enabled in UVLO condition, then PWRGD stays low. This condition is satisfied by the presence of an internal 200kΩ pull-down resistor connected from PWRGD to ground. During soft start, PWRGD stays low independently from the status of Vcore voltage. During this time, PWRGD status is “don’t care”. BAND GAP REFERENCE A better than +1% precision band gap reference acts as the internal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. All references to VREF in the equations to follow will assume VREF = 1.7V. CORE CONVERTER CONTROLLER Precision VID DAC Reference The 5-bit digital to analog converter (DAC) serves as the programmable reference source of the core comparator. Programming is accomplished by CMOS logic level VID code applied to the DAC inputs. The VID code vs. the DAC output is shown in the Output Voltage Table. The accuracy of the VID DAC is maintained on the same level as the band gap reference. There is a 10µA pull-up current on each DAC input while EN is high. Core Comparator This is an ultra-fast hysteretic comparator with a typical propagation delay of approximately 20ns at a 20mV overdrive. Its hysteresis is determined by the resistance ratio of two external resistors, RHYS and ROH, and the high accuracy internal reference voltage, VREF. VHYS = R OH • VREF R HYS This chip can be used in standard hysteretic mode controller configuration and in DSPS (Dynamic Set Point Switching) hysteretic controller scheme. In standard hysteretic controller configuration, the core comparator compares the output voltage of the core converter, VCORE to the VID code programmed DAC voltage, VDAC. VCORE(t) = VDAC + VHYST(t) The core voltage ramps up and down between the two thresholds determined by the hysteresis of the comparator: VHCORE = VDAC + VHYST VLCORE = VDAC - VHYST In DSPS hysteretic controller configuration, the core comparator compares the core voltage, VCORE, not to the DAC voltage, VDAC directly but rather to a voltage less than the DAC voltage by a DSPS voltage, VDSPS. VCORE(t) = VDAC - VDSPS(t) + VHYST(t) The DSPS voltage is a function of the load current. It is generated from the current sense voltage, VCS , developed across a sense resistor, RCS, which is inserted in series with the main buck inductor and also used for current sensing for the cycle-by-cycle current limiting. The sense voltage is scaled up by the DSPS gain, ADSPS, which is set by the resistance ratio of two external resistors, RDAC and RCORE. VDSPS ( t ) = A DSPS • VCS ( t ) = (1 + R DAC ) • R CS • iCORE ( t ) R CORE Pentium is a registered trademark of Intel Corporation 9 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER January 28, 2000 In DSPS hysteretic controller configuration (Cont’d) The comparator reference voltage positioning is such that an increasing current sense voltage, VCS, i,e, an elevating load current, causes the reference voltage to decrease, and as a consequence, the core output voltage also droops. At no load current, there is no droop while a maximum load, the droop is likewise maximum. In order for the core voltage to be positioned around the nominal VDAC v oltage symmetrically and not just one way downward from the nominal value, a DSPS offset voltage, VDSPSOFFS, can be introduced. The offset voltage moves the comparator reference voltage upward at no load. At optimal offsetting, the reference voltage is above the nominal level for load currents less than half of the maximum load, and below the nominal value for currents higher than that. The maximum amount of core voltage positioning can be determined from the constrain which says the output voltage at no load condition must still remain below the upper threshold of the core voltage regulation window, and at maximum load, it must be above the lower threshold. The offset voltage can be generated across a resistor, ROH, which is also used to create the hysteresis voltage by forcing a unipolar DSPS offsetting current through it. The offsetting current is conveniently provided by a high value resistor, ROFFSET, connected from the comparator CMP pin to the ground. V DSPSOFFS = R OH • IDSPS = R OH • VCS + VCORE R OH +R OFFSET ≈ R OH R OFFSET • V DAC ® SC1406A Core Voltage Offsetting In order for the core voltage to be positioned around the nominal VDAC v oltage symmetrically and not just always one direction downward, a core offset voltage, VOFFS can be introduced. The offset voltage moves the comparator reference voltage upwards. Using optimal offsetting, the core comparator reference voltage will be above the VID programmed nominal DAC voltage for load currents less than half of the maximum load, and below that for higher current. The maximum amount of the core voltage positioning can be determined from the constraint that the output v oltage regulation window, and at maximum load, it has to be above the lower threshold. The positioning offset voltage can be generated across the same resistor, ROH also used to create the hysteresis voltage, by forcing a unipolar offsetting current through it. The offsetting current is conveniently provided by a high value resistor, ROFFS connected from the comparator CMP pin to the ground. Current Limit Comparator The current limit comparator monitors the core converter output current and turns the high side switch off when the current exceeds the upper current limit threshold, VHCL and re-enable only if the load current drops below the lower current limit threshold, VLCL. The current is sensed by monitoring the voltage drop across the current sense resistor, RCS, connected in series with the core converter main inductor (the same resistor used for DSPS input signal generation). The thresholds have the following relationships: VHCL = 3 • VLCL = 2 • VHYSCL = R CLOH • V REF R CLSET R CLOH • V REF R CLSET VCS