SC202EVB

SC202 3.5MHz, 500mA Step-down Regulator with Integrated Inductor POWER MANAGEMENT Features                      Description The SC202 is a high efficiency 500mA step-down regulator that includes an integrated inductor inside the p ackage. The input voltage range makes it ideal for battery operated applications with space limitations. The SC202 also includes fifteen programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. The output voltage can be fixed to a single setting or dynamically switched between different levels. Pulling all four control pins low disables the output. The SC202 operates at a fixed 3.5MHz switching frequency in normal PWM (Pulse-Width Modulation) mode. A variable frequency PSAVE (power-save) mode is used to optimize efficiency at light loads for each output setting. Built-in hysteresis prevents chattering between the two modes. The SC202 provides several protection features to safe guard the device under stressed conditions. These include short circuit protection, over-temperature protection, under-voltage lockout, and soft-start to control in-rush current. These features, coupled with the small 2.5 x 3.0 x 1.0 (mm) package, make the SC202 a versatile device ideal for step-down regulation in products needing high efficiency and a small PCB footprint. Input Voltage — 2.9V to 5.5V Output Voltage — 0.8V to 3.3V Output current capability — 500mA Internal inductor 15 programmable output voltages High light-load efficiency via automatic PSAVE mode Fast transient response Temperature range — -40 to +85°C Oscillator frequency — 3.5MHz 100% duty cycle capability Quiescent current — 38µA typ Shutdown current — 0.1µA typ Internal soft-start Over-voltage protection Current limit and short circuit protection Over-temperature protection Under-voltage lockout Floating control pin protection MLPQ-13 — 2.5 x 3.0 x 1.0 (mm) package Lead-free and halogen-free WEEE and RoHS compliant Applications        Point of load regulation Smart phones and cellular phones MP3/personal media players Personal navigation devices Digital cameras Single Li-ion cell or 3 NiMH/NiCd cell devices Devices with 3.3V or 5V internal power rails Typical Application Circuit VIN 2.9V to 5.5V SC202 IN CIN 4.7µF CTL3 SNS OUT VOUT 0.8V to 3.3V Control Logic Lines CTL2 CTL1 CTL0 COUT 10µF GND LX NC June 30, 2010 © 2010 Semtech Corporation 1 SC202 Pin Configuration Ordering Information Device SC202MLTRT(1)(2) LX LX LX 1 2 3 TOP VIEW SNS CTL3 CTL0 4 5 6 7 8 CTL1 CTL2 9 IN 10 GND 13 12 11 OUT OUT OUT Package MLPQ-13 — 2.5 x 3.0 Evaluation Board SC202EVB Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. MLPQ-13; 2.5 x 3.0, 13 LEAD θJA = 58°C/W Table 1 – Output Voltage Settings CTL3 CTL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CTL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CTL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout Shutdown 0.80 1.00 1.20 1.40 1.50 1.60 1.80 1.85 1.90 2.00 2.20 2.50 2.80 3.00 3.30 Marking Information 0 0 0 0 0 0 0 202 yyww xxxx yyww = Date Code xxxx = Semtech Lot Number 0 1 1 1 1 1 1 1 1 2 SC202 Absolute Maximum Ratings IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 LX Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to VIN + 0.5 Other Pins (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN + 0.3 Output Short Circuit to GND . . . . . . . . . . . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Recommended Operating Conditions Input Voltage Range (V) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5 Operating Temperature Range (°C) . . . . . . . . . . -40 to +85 Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W). . . . . 58 Junction Temperature Range (°C) . . . . . . . . . . . -40 to +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards. Electrical Characteristics Unless otherwise specified: VIN= 3.6V, CIN= 4.7µF, COUT=10µF, VOUT=1.8V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C Parameter Output Voltage Range Symbol VOUT VOUT_TOL ΔVLINEREG ΔVLOADREG IOUT ILIMIT IFB_LIM VUVLO IQ ISD IOUT RDSON_P RDSON_N Condition Min 0.8 Typ Max 3.3 (1) 2.0 Units V Output Voltage Tolerance Line Regulation Load Regulation Output Current Capability Current Limit Threshold Foldback Current Limit IOUT = 200mA PSAVE mode 2.9 ≤ VIN ≤ 5.5V, IOUT = 200mA 200mA ≤ IOUT ≤ 500mA -2.0 1.5 0.3 -1 500 800 % %/V %/A mA 1300 150 2.9 200 38 0.1 0.1 250 mΩ 350 60 1.0 1.0 mA mA V mV µA µA µA ILOAD > ILIMIT Rising VIN Hysteresis No switching, IOUT = 0mA VCTL 0-3= 0V Into OUT pin IOUT= 100mA IOUT= 100mA Under-Voltage Lockout Quiescent Current Shutdown Current Output Leakage Current High Side Switch Resistance(2) Low Side Switch Resistance(3) 3 SC202 Electrical Characteristics (continued) Parameter Switching Frequency Soft-Start Thermal Shutdown Thermal Shutdown Hysteresis Symbol fSW tSS TOT THYST Condition Min 2.8 Typ 3.5 100 160 20 Max 4.2 500 Units MHz µs °C °C VOUT = 90% of final value Rising temperature Logic Inputs - CTL0, CTL1, CTL2, and CTL3 Input High Voltage Input Low Voltage Input High Current Input Low Current Notes (1) Maximum output voltage is limited to VIN if the input is less than 3.3V. (2) Measured from IN to LX. (3) Measured from LX to GND. VIH VIL IIH IIL VCTL 0-3= VIN VCTL 0-3= GND -2.0 -2.0 1.2 0.4 5.0 2.0 V V µA µA 4 SC202 Typical Characteristics VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, TA = 25°C unless otherwise noted. Efficiency vs. IOUT ( TA = -40°C) 100 90 80 70 3.3V 2.8V VOUT = 1V, 1.8V, 2.8V, and 3.3V 100 95 90 Efficiency vs. VOUT ( TA = -40°C) IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V 3.6V 4.2V 5.0V Efficiency (%) 60 50 40 30 20 10 0 0.1 Efficiency (%) 1 10 Load Current (mA) 100 1000 1.8V 1V 85 80 75 70 65 0.5 1 .0 1 .5 2 .0 VOUT (V) 2 .5 3 .0 3 .5 Efficiency vs. IOUT ( TA = 25°C) 100 90 80 70 3 .3 V 2 .8 V VOUT = 1V, 1.8V, 2.8V, and 3.3V Efficiency vs. VOUT ( TA = 25°C) 100 95 90 IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V 3.6V 4.2V 5.0V Efficiency (%) 60 50 40 30 20 10 0 0 .1 Efficiency (%) 1 10 Load Current (mA) 100 1000 1 .8 V 1V 85 80 75 70 65 0.5 1.0 1 .5 2 .0 VOUT (V) 2 .5 3 .0 3 .5 Efficiency vs. IOUT ( TA = 85°C) 100 90 80 70 3.3V 2.8V VOUT = 1V, 1.8V, 2.8V, and 3.3V Efficiency vs. VOUT ( TA = 85°C) 100 95 90 IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V 3.6V 4.2V 5.0V Efficiency (%) 60 50 40 30 20 10 0 0.1 Efficiency (%) 1 10 Load Current (mA) 100 1000 1.8V 1V 85 80 75 70 65 0 .5 1 .0 1.5 2.0 VOUT (V) 2 .5 3 .0 3 .5 5 SC202 Typical Characteristics (continued) VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, TA = 25°C unless otherwise noted. Frequency vs. Temperature 3.6 3.5 3.4 3 .3 3 .2 3 .1 3 -40 -20 0 20 40 Temperature (°C) 60 80 100 3 .3 V 2 .8 V 79 Efficiency vs. VIN ( VOUT =1.8V) 91 IOUT = 200mA VOUT = 1V, 1.8V, 2.8V, and 3.3V 88 -40°C Frequency (MHz) Efficiency (%) 85 1 .0 V 1 .8 V 25°C 85°C 82 76 2 .5 3 .0 3 .5 4 .0 VIN (V) 4 .5 5 .0 5 .5 Load Regulation (VOUT = 1.8V) 1.83 1.82 -40°C Output Voltage (V) 1.83 Line Regulation (VOUT =1.8V) IOUT = 200mA 1.82 1.81 1.81 25°C 1.80 85°C 1.79 VOUT (V) 1.80 -40°C 25°C 85°C 1.79 1.78 1.77 1.78 1.77 0 100 200 300 Load Current (mA) 400 500 2.5 3 .0 3 .5 4 .0 VIN (V) 4 .5 5 .0 5 .5 6 SC202 Typical Characteristics (continued) Light Load Switching — VOUT = 1.0V Light Load Switching — VOUT = 1.8V VOUT (50mV/div) VOUT (50mV/div) VLX (5V/div) VLX (5V/div) ILX (200mA/div) Time (400ns/div) ILX (200mA/div) Time (400ns/div) Light Load Switching — VOUT = 2.8V VOUT (50mV/div) VLX (5V/div) Light Load Switching — VOUT = 3.3V VOUT (50mV/div) VLX (5V/div) ILX (200mA/div) Time (400ns/div) ILX (200mA/div) Time (400ns/div) Heavy Load Switching — VOUT = 1.0V VOUT (50mV/div) VOUT (50mV/div) Heavy Load Switching — VOUT = 1.8V VLX (5V/div) VLX (5V/div) ILX (200mA/div) ILX (200mA/div) Time (200ns/div) Time (200ns/div) 7 SC202 Typical Characteristics (continued) Heavy Load Switching — VOUT = 2.8V VOUT (50mV/div) VOUT (50mV/div) Heavy Load Switching — VOUT = 3.3V VLX (5V/div) VLX (5V/div) ILX (200mA/div) ILX (200mA/div) Time (200ns/div) Time (200ns/div) Heavy Load Soft-start ILOAD = 500mA ILOAD = 10mA Light Load Soft-start IIN (200mA/div) IIN (200mA/div) VOUT (1.0V/div) Vout (1.0V/div) ILX (500mA/div) Time (40μs/div) ILX (500mA/div) Time (40μs/div) Load Transient Response — 25 to 90mA Load Transient Response — 25 to 500mA VOUT (50mV/div) VOUT (100mV/div) ILX (200mA/div) ILX (500mA/div) ILOAD (50mA/div) ILOAD (500mA/div) Time (20μs/div) Time (20μs/div) 8 SC202 Typical Characteristics (continued) Load Transient Response — 200 to 500mA VOUT (100mV/div) VOUT (500mV/div) VID Transient Response — PWM 1.2V to 1.8V transition ILX (500mA/div) ILX (500mA/div) ILOAD (500mA/div) VCTL2 (2V/div) Time (20μs/div) Time (20μs/div) VID Transient Response — PSAVE 1.2V to 1.8V transition VOUT (2V/div) VOUT (500mV/div) ILX (500mA/div) ILX (500mA/div) Shutdown Transient Response VCTL3-0 (2V/div) VCTL2 (2V/div) Time (20μs/div) Time (20μs/div) Line Transient Response — PWM 4.0V to 3.5V using Li-Ion battery Line Transient Response — PSAVE 4.0V to 3.5V using Li-Ion battery VOUT (50mV/div) VOUT (50mV/div) ILX (200mA/div) ILX (200mA/div) VIN (500mV/div) Time (400μs/div) VIN (500mV/div) Time (400μs/div) 9 SC202 Pin Descriptions Pin 1, 2, 3 4 5 6 7 8 9 10 11, 12, 13 Pin Name LX SNS CTL3 CTL0 CTL1 CTL2 IN GND OUT Pin Function Switching node sense pin — for test purposes only. Output sense pin — connect to output capacitor for proper sensing of output voltage. Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL3 is pulled above the logic high threshold. Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL0 is pulled above the logic high threshold. Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL1 is pulled above the logic high threshold. Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL2 is pulled above the logic high threshold. Input power supply pin — connect a bypass capacitor from this pin to GND. Ground reference and power ground for the SC202. Regulator output pin — connect a 10µF ceramic capacitor to this pin for proper filtering. 10 SC202 Block Diagram Plimit Amp 9 IN Current Amp OSC & Slope Generator Control Logic PWM Comp 1µ H A LX B OUT 500mV Ref Error Amp PSAVE Comp Nlimit Amp CTL3 5 CTL2 8 CTL1 7 CTL0 6 SNS 4 A = pins 1, 2, 3 B = pins 11, 12, 13 Voltage Select 10 GND 11 SC202 Applications Information General Description The SC202 is a synchronous step-down PWM (Pulse Width Modulated) DC-DC regulator utilizing a 3.5MHz fixed-fre quency voltage-mode architecture and an internal 1µH inductor. The device is designed to operate in fixed-fre quency PWM mode and enter PSAVE (power save) mode utilizing pulse frequency modulation under light load conditions to maximize efficiency. Two capacitors are the o nly external components required — one for input d ecoupling and one for output filtering. The output voltage is programmable, eliminating the need for external programming resistors. Loop compensation is also internal, eliminating the need for external components to control stability. ment for systems that reduce the supply voltage when entering sleep states. Note that applying all zeros to the CTL pins when changing the output voltage will temporarily disable the device, so it is important to avoid this combination when dynamically changing levels. Adjustable Output Voltage Selection If an output voltage other than one of the 15 programmable settings is needed, an external resistor divider network can be added to the SC202 to adjust the output voltage setting. This network scales the output based on the resistor ratio and the programmed output setting. T he resistor values can be determined using the equation VOUT VSET RFB1 RFB 2 RFB2 ISNS RFB1 Programmable Output Voltage The SC202 has 15 fixed output voltage levels which can be individually selected by programming the CTL control pins (CTL3-0 — see Table 1 on page 2 for settings). The device is disabled whenever all four CTL pins are pulled low and enabled whenever at least one of the CTL pins is pulled high. This configuration eliminates the need for a dedicated enable pin. Each CTL pin is internally pulled down via 1MΩ if VIN is below 1.5V or if the voltage on the control pin is below the input high voltage. This ensures that the output is disabled when power is applied if there are no inputs to the CTL pins. Each weak pull-down is disabled whenever its pin is pulled high and remains disabled until all CTL pins are pulled low. The output voltage can be set using different approaches. If a static output voltage is required, the CTL pins can be tied to either IN or GND to set the desired voltage whenever power is applied at IN. If enable control is required, each CTL pin can be tied to either GND or to a microprocessor I/O line to create the desired control code whenever the control signal is forced high. This approach is equivalent to using the CTL pins collectively as a single enable pin. A third option is to connect each of the four CTL pins to individual microprocessor I/O lines. Any of the 15 output voltages can be programmed using this approach. If only two output voltages are needed, the CTL pins can be combined in a way that will reduce the number of I/O lines to 1, 2, or 3, depending on the control code for each desired voltage. Other CTL pins could be hard-wired to GND or IN. This option allows dynamic voltage adjust- where VOUT is the desired output voltage, VSET is the voltage s etting selected by the CTL pins, R FB1 i s the resistor between the output capacitor and the SNS pin, RFB2 is the resistor between the SNS pin and ground, and ISNS is the leakage current into the SNS pin during normal operation. The current into the SNS pin is typically 1µA, so the last term of the equation can be neglected if the current through RFB2 is much larger than 1µA. Selecting a resistor value of 10kΩ or lower will simplify the design. If ISNS is neglected and RFB2 is fixed, RFB1 can be determined using the equation RFB1 RFB2 VOUT VSET VSET Inserting resistance in the feedback loop will adversely affect the system’s transient performance if feed-forward capacitance is not included in the circuit. The circuit in Figure 1 illustrates how the resistor divider and feedforward capacitor can be added to the SC202 schematic. The value of feed-forward capacitance needed can be determined using the equation CFF 4 10 6 RFB1 VSET VOUT 0.5 VOUT VSET VSET 2 0 .5 12 SC202 Applications Information (continued) SC202 VIN CIN IN OUT COUT CFF CTL3 CTL2 Enable CTL1 CTL0 GND SNS VOUT RFB1 RFB2 LX pin. The duty cycle (percentage of time PMOS is active) increases as VIN decreases to maintain output voltage regulation. As the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (PMOS always on) and the device enters a passthrough mode until the input voltage increases or the l oad decreases enough to allow PWM switching to resume. Power Save Mode Operation Figure 1 – Application Circuit with External Resistors To simplify the design, it is recommended to program the output setting to 1.0V, use resistor values smaller than 10kΩ, and include a feed-forward capacitance calculated with the previous equation. If the output voltage is set to 1.0V, the previous equation reduces to CFF 8 10 6 VOUT 0.5 RFB1 VOUT 1 2 Example: An output voltage of 1.3V is desired, but this is not a programmable option. What external component values for Figure 1 are needed? Solution: To keep the circuit simple, set RFB2 to 10kΩ so current into the SNS pin can be neglected and set the CTL3-0 pins to 0010 (1.0V setting). The necessary component values for this situation are RFB1 RFB 2 VOUT VSET VSET 3k When the load current decreases below the PSAVE threshold, PWM switching stops and the device automatically enters PSAVE mode. This threshold varies depending on the input voltage and output voltage setting, optimizing efficiency for all possible load currents in PWM or PSAVE mode. While in PSAVE mode, output voltage regulation is controlled by a series of switching bursts. During a burst, the inductor current is limited to a peak value which controls the on-time of the PMOS switch. After reaching this peak, the PMOS switch is disabled and the inductor current decreases to near 0mA. Switching bursts continue until the output voltage climbs to VOUT +2.5% or until the PSAVE current limit is reached. Switching is then stopped to eliminate switching losses, enhancing overall efficiency. Switching resumes when the output voltage reaches the lower threshold of VOUT and continues until the upper threshold again is reached. Note that the output voltage is regulated hysteretically while in PSAVE mode between VOUT and VOUT + 2.5%. The period and duty cycle while in PSAVE mode are solely determined by VIN and VOUT until PWM mode resumes. This can result in the switching frequency being much lower than the PWM mode frequency. If the output load current increases enough to cause VOUT to decrease below the PSAVE exit threshold (VOUT -2%), the device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low threshold levels are both set at or above VOUT to minimize undershoot when the SC202 exits PSAVE. Figure 2 illustrates the transitions from PWM mode to PSAVE mode and back to PWM mode. CFF 8 10 6 VOUT 0.5 RFB1 VOUT 1 2 5.69nF PWM Operation Normal PWM operation occurs when the output load current exceeds the PSAVE threshold. In this mode, the PMOS high side switch is activated with the duty cycle required to produce the output voltage programmed by the CTL pins. An internal synchronous NMOS rectifier eliminates the need for an external Schottky diode on the 13 SC202 Applications Information (continued) Load Demand (IOUT) VOUT +2.5% OFF VOUT VOUT -2% BURST Over-Voltage Protection Over-voltage protection ensures the output voltage does not rise to a level that could damage its load. When VOUT exceeds the regulation voltage by 15%, the PWM drive is disabled. Switching does not resume until VOUT has fallen below the regulation voltage by 2%. Current Limit The SC202 switching stage is protected by a current limit function. If the output load exceeds the PMOS current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150mA. Under these conditions, the output voltage will be the product of IFB-LIM and the load resistance. The load must fall below IFB-LIM for the device to exit fold-back current limit mode. This function makes the device capable of sustaining an indefinite short circuit on its output under fault conditions. Thermal Shutdown The SC202 has a thermal shutdown feature to protect the device if the junction temperature exceeds 160°C. During thermal shutdown, the PMOS and NMOS switches are both disabled, tri-stating the LX output. When the junc tion temperature drops by the hysteresis value (20°C), the device goes through the soft-start process and resumes normal operation. Under-Voltage Lockout UVLO (Under-Voltage Lockout) activates when the supply voltage drops below the falling UVLO threshold. This prevents the device from entering an ambiguous state in which regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the threshold. VLX PWM Mode at Medium/High Load PSAVE Mode at Light Load PSAVE EXIT PWM Mode at Medium/High Load Time Figure 2 — Transitions Between PWM and PSAVE Modes Protection Features The SC202 provides the following protection features: • • • • • Soft-Start Operation Over-Voltage Protection Current Limit Thermal Shutdown Under-Voltage Lockout Soft-Start The soft-start sequence is activated after a transition from an all zeros CTL code to a non-zero CTL code enables the device. At start-up, the PMOS current limit is stepped through four levels: 25%, 40%, 60%, and 100%. Each step is maintained for 60μs following an internal reference start up of 20μs, resulting in a total nominal start-up period of 260μs. If VOUT reaches 90% of the target within the first 2 steps, the device continues in PSAVE mode at the end of soft-start; otherwise, it goes into PWM mode. Note the VOUT ripple in PSAVE mode can be larger than the ripple in PWM mode. 14 SC202 Applications Information (continued) COUT Selection The internal voltage loop compensation in the SC202 limits the minimum output capacitor value to 10μF. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. Increasing the output capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. In addition to ensuring stability, the output capacitor serves other important functions. This capacitor determines the output voltage ripple — as capacitance increases, ripple voltage decreases. It also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Once the loop responds, regulation is restored and the desired output is reached. During the period prior to PWM operation resuming, the relationship between output voltage and output capacitance can be approximated using the equation COUT 3 ILOAD VDROOP f value exceeds the necessary capacitance value at the programmed output voltage. Check the manufacturer’s capacitance vs. DC voltage graphs when selecting an o utput capacitor to ensure the capacitance will be adequate. Table 2 lists the manufacturers of recommended output capacitor options. Table 2 — Recommended Output Capacitors Manufacturer Part Nunber Murata GRM188R60J106ME47D Murata GRM21BR60J106K Taiyo Yuden JMK107BJ106MA-T TDK C1608X5R0J106MT Value (μF) 10±20% 10±10% 10±20% 10±20% Type Rated Voltage (VDC) 6.3 6.3 6.3 6.3 Dimensions LxWxH (mm) Case Size 1.6x0.8x0.8 0603 2.0x1.25x1.25 0805 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 X5R X5R X5R X5R CIN Selection This equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. For example, a load step from 50mA to 400mA requiring droop less than 50mV would require the minimum output capacitance to be COUT 3 0 .4 0.05 3.5 10 6 6. 0 F The SC202 input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required value. For example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5μF. The value of required input capacitance is estimated by determining the acceptable input ripple voltage and calculating the minimum value required for CIN using the equation VOUT VOUT 1 VIN VIN V IOUT ESR f CIN In this example, using a standard 10µF capacitor would be adequate to keep voltage droop less than the desired limit. Note that if the voltage droop limit were decreased from 50mV to 25mV, the output capacitance would need to be increased to at least 12µF (twice as much capacitance for half the droop). Capacitance will decrease from the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose The input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). 15 SC202 Applications Information (continued) The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capacitor should be placed as closely as possible to the IN and GND pins. Table 3 lists recommended input capacitor options from different manufacturers. Table 3 — Recommended Input Capacitors Manufacturer Part Nunber Murata GRM188R60J475K Murata GRM188R60J106K Taiyo Yuden JMK107BJ475KA TDK C1608X5R0J475KT Value (μF) 4.7±10% 10±10% 4.7±10% 4.7±10% Type Rated Voltage (VDC) 6.3 6.3 6.3 6.3 Dimensions LxWxH (mm) Case Size 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 IN X5R X5R X5R X5R 3. Use a ground plane referenced to the GND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 4. Route the output voltage feedback/sense trace (connected to the SNS pin) away from the LX node as shown in Figure 3 to minimize noise and magnetic interference. 5. Minimize the resistance from the OUT and GND pins to the load. This will reduce errors in DC regulation due to voltage drops in the traces. 6. The two smaller exposed pads on this package should not be connected to any traces. The area beneath these two pads must be kept clear so that they do not make electrical contact with any traces, including ground. CTL2 These pads should not be electrically connected to the PCB. CTL1 PCB Layout Considerations The layout diagram in Figure 3 shows a recommended PCB top-layer for the SC202 and supporting components. Specified layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can also result. The following guidelines are recommended for designing a PCB layout: 1. CIN should be placed as close to the IN and GND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to minimize trace impedance. This will also minimize EMI and input voltage ripple by localizing the high frequency current pulses. 2. COUT should be connected as closely as possible to the OUT pin. CIN GND CTL0 CTL3 SNS 3.5mm SC202 COUT OUT LX (no connection needed) 3.8mm Figure 3 — Recommended PCB Layout 16 SC202 Outline Drawing — MLPQ-13 A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS MILLIMETERS MIN NOM MAX 0.80 1.00 0.00 0.05 (0.20) 0.15 0.20 0.25 2.40 2.50 2.60 0.60 0.70 0.75 2.90 3.00 3.10 1.17 1.27 1.32 0.40 BSC 0.40 0.45 0.50 13 0.08 0.10 PIN 1 INDICATOR (LASER MARK) E A aaa C A1 e SEE DETAIL A bbb bxN CAB 0.238 Lx7 0.800 0.355 e E1 2 1 N A2 C SEATING PLANE 0.312 0.157 8X 0.025 E/2 C L 1.30 0.265 2X 0.110 C L C L 0.363 0.684 2X 0.200 0.30 x 45° CHAMFER 0.25 NOTES: 1. 2. D1 2X 0.95 D/2 DETAIL A SCALE: 4/1 C L CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 17 SC202 Land Pattern — MLPQ-13 Z C L K 2X DIMENSIONS 1.55 0.55 .250 0.265 1.30 C L H (P) P 0.355 P1 (3.10) DIM G H K P P1 X Y Z MILLIMETERS 1.50 1.27 0.75 0.40 0.80 0.20 0.80 3.10 Y X 0.238 (P) G 0.684 0.363 0.157 0.312 8X 0.025 2X 0.110 2X 0.200 SMALL EXPOSED PADS LOCATION NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. LAND PATTERNS ( SOLDER PADS) NOT REQUIRED FOR SMALLER EXPOSED PADS. 4. DO NOT PLACE EXPOSED TRACES OR VIAS UNDER SMALLER EXPOSED PADS. 18 SC202 © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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