SC2422

BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC2422A biphase, current mode controller is designed to work with Semtech smart synchronous drivers, such as the SC1205, SC1305 or the SC1405 to provide the DC/DC converter solution for the most demanding Micro-processor applications. Input current rather than output current sensing is used to guarantee precision phase to phase current matching using a single sense resistor on the input power line. Accurate current sharing and pulse by pulse current limit are implemented without the power loss and transient response degradation associated with output current sense methods. Two phase operation allows significant reduction in input/output ripple while enhancing transient response. The DAC step size and range are programmable with external components thus allowing compliance with new and emerging VID ranges. A novel approach implements active droop, minimizing output capacitor requirements during load transients. This avoids the pitfalls of the passive droop implementation. This feature also allows easy implementation of N+1 redundancy and current sharing among modules. Programmable Under Voltage Lockout assures proper start-up and shutdown by synchronizing the controller to the driver supply. Wide PWM frequency range allows use of low profile, surface mount components. FEATURES • • • • • • • • • • • Precision, pulse by pulse phase current matching Active drooping allows for best transient response Input Sensing Current mode control Programmable DAC step size/offset allows Compliance with VRM9.0, VRM8.3 or VRM8.4 Externally programmable soft-start 5V or 12V input for next generation processors 0% minimum duty cycle improves transient response Externally Programmable UVLO with hysteresis Cycle by cycle current limiting Programmable Internal Oscillator to 1 MHz VID IIIII Inhibit (No CPU) APPLICATIONS • • • Intel Advanced Microprocessors TM AMD Athlon power supplies Servers/Workstations, high density power supplies ORDERING INFORMATION DEVICE (1) PACKAGE SO-16 TEMP. RANGE (TJ) 0 - 125°C SC2422ACS.TR SC2422A.EVB Evaluation Board TYPICAL APPLICATION SCHEMATIC INPUT Rsens Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. VIN 1 1 VID4 VID3 VID2 VID1 VID0 ERROUT FB RREF VCC BGOUT OC+ OUT1 OUT2 OCUVLO GND 16 3 2 3 4 5 6 7 Rf 8 15 4 14 13 12 11 1 10 3 9 4 Rref BOOST 8 IN VCC VDD DRVH 7 6 5 To Processor VID control PHASE DRVL PGND 2 SC1305 BOOST 8 VIN DRVH 7 6 5 IN VCC VDD PHASE DRVL SC2422A Ri PGND 2 SC1305 Vout 1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A ABSOLUTE MAXIMUM RATINGS Parameter Input DC Rail Voltage to GND PGND to GND Operating Temperature Range Junction Temperature Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Storage Temperature Range Lead Temperature (Soldering) 10 sec Symbol VIN TA TJ θJC θJA TSTG TLEAD Maximum 15 +1 -20 to 125 0 to 125 20 60 -65 to +150 300 Units V V °C °C °C/W °C/W °C °C ELECTRICAL CHARACTERISTICS Unless specified: VCC = +5V, TAMB = 25°C, RREF = 11.5kΩ. See Typical Application Circuit Parameter Chip_Supply IC Supply Voltage IC Supply Current Reference Section Bandgap Output Source Impedance Supply Rejection VID Step Voltage Accuracy Temperature Stability Voltage Accuracy Oscillator Section Frequency Range Frequency Accuracy Temperature Stability Voltage Error Amplifier Input Offset Voltage Input Offset Current Open Loop Gain PSRR Output Sink Current Output Source Current Unity Gain Bandwidth Slew Rate 1V < VERROUT < 4V VCC = 5 - 12V VERROUT = 1V VERROUT = 4V IO < 100µA IO < 100µA +/-5 0.1 90 80 2.5 2 5 10 mV µA dB dB mA mA MHz V/uS 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 VIN = 12.0V, RREF = 13kΩ or VIN = 5.0V, RREF =11.5kΩ 0°C < TAMB < 70°C 400 450 500 +/-5 1000 550 kHz kHz % 0°C < TAMB < 70°C 0°C < TAMB < 70°C VCC = 5.0V ~ 12.0V RI = 6.49kΩ, RREF = 11.5kΩ -1 5 +/-1 CBG = 4.7nF 1.5 3 2 25 1 V kΩ mV/V mV % % % VCC = 5.0 ~ 12.0V 4.5 5 9 14 V mA Conditions Min Typ Max Units BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A ELECTRICAL CHARACTERISTICS (Cont) Unless specified: VCC = +5V, TAMB = 25°C, RREF = 11.5kΩ. PARAMETER Current Sense Amplifier Amplifier Gain Input Offset Voltage, Input Referred CMRR PSRR Input Common Mode Range Max Differential Signal/ Current Limit Threshold I-Limit Delay Protection UVLO Ramp-up Threshold UVLO Ramp-down Threshold Outputs (OUT 1, OUT 2) Max Duty Cycle Duty Match Typical Output Voltage Swing Per phase, FOSC = 500kHz FOSC = 500kHz RL = 10kΩ RL = 100kΩ VID Logic Threshold VID Logic Pin Bias Current Note: 1. If the VID pins are driven high by an external source (in contrast to being left open), then all VIDs input will need to be externally pulled high. If VIDs are left open, no external pull-up is required. 2. This device is ESD sensitive. Use of standard ESD handling precautions is required. VIN = 0 -.5 .8 .2 0.8 12 47 .5 2.5 3.3 2 % % V V V µA RSOURCE UVLO pin = 20kΩ RSOURCE UVLO pin = 20kΩ 1.475 1.375 V V VOC- - VOC+ Current limit activation to OUT 1 & OUT 2 switching off (VOC- - VOC+ ) < 100mV (VOC- - VOC+ ) < 100mV VICM = 9 ~ 14V @ DC VCC = 9 ~ 14V @ DC 26 4 80 80 VCC +/0.3 100 60 mV ns dB mV dB dB CONDITIONS MIN TYP MAX UNITS 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A PIN DESCRIPTION Pin 1: VID4 , MSB Pin 2: VID3 Pin 3: VID2 Pin 4: VID 1 Pin 5: VID0 , LSB Pin 6: ERROUT Error-amplifier output. Pin 7: FB Error-amplifier inverting input. Pin 8: RREF Frequency setting resistor pin. Also programs the DAC current step size. (see application information for programming the frequency) Pin 9: GND Chip ground. Pin 10: UVLO Programmable Under Voltage LockOut. This pin may be connected to the MOSFET driver supply through a voltage divider to inhibit the SC2422A until the drivers are on. The UVLO comparator trip point is 1.5V. Pin 11: OC- Input current sense, negative input. This pin is connected to the input supply side of the current sense resistor. Pin 12: OUT2 PWM output for phase 2. Drives external Power MOSFET driver. Pin 13: OUT1 PWM output for phase 1. Drives external Power MOSFET driver. Pin 14: OC+ Input current sense positive input. This pin is connected to MOSFET side of the current sense resistor. Pin 15: BGOUT Soft start and reference. Bypass to ground (GSEN) with a .022µF - 0.1µF capacitor to implement soft start in conjunction with internal 3KΩ resistor. To ensure output voltage accuracy, the maximum current source/sink from this pin should be limited to 0.5 uA. Pin 16: VCC Chip positive supply. PIN CONFIGURATION Top View FUNCTIONAL BLOCK DIAGRAM (16-Pin SOIC) 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A OUTPUT VOLTAGE (VRM 9.0) Unless specified: 0 = GND; 1 = High (or Floating). TA = 25°C, VCC = 5V, 2-Phase operation VCCCORE VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (VDC) Output Off 1.1 1.125 1.15 1.175 1.2 1.225 1.250 1.275 1.3 1.325 1.35 1.375 1.4 1.425 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 1.775 1.8 1.825 1.85 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 +5V 1uf R3 C1 C4 10nf 41.2 .01 D7 1uf C13 U2 Q1 TG 1 GFB70N03 5 EN BG Q3 R4 2.2 C32 10u,CER C17 GND 4 CO SC1205S R99 0 8 13 7 R8 0 C8 .01 L1 2 TTIB1106-450 R5 0 .1 C15 2.2 820uf,16V C35 10u,CER C16 BST R31 open VCC 16 LL42 U1 3 C99 FDB7030BL R21 R30 0 C11 open C27 820uf,16V C14 820uf,16V C12 10u,CER 10u,CER 820uf,16V C5 C2 1uf C3 J1 R6 .005 R1 .005 VIN Vin 820uf,OS C33 1u,16V 820uf,16V 820uf,16V 820uf,16V 10u,CER C6 R2 10 1 2 3 4 5 6 C9 C7 C10 C34 R32 C21 75k 3 R20 U3 10k BST R33 TG 1 2 10 GND local gnd C26 R17 6.49k 8 TO OPERATE FROM +12V: R3=20.5 R6=open R11=2.7K R14=12.40K R17=7.50K R19=31.6K R30=20.5 R32=120K R33=22K C25=150pf C99=1nf Cut at X and install R99 to enable Driver side UVLO 652 MITCHELL ROAD NEWBURY PARK CA 91320 100pf EN BG 4 10uf CO SC1205S C25 R14 R19 26.1k 11.5k SC2422A * © 2000 SEMTECH CORP. 1 VID4 INPUT S1 EN * X 10uf 2 VID3 C18 14 BGOUT 15 VS DRN +5V 6 PRELIMINARY - August 7, 2000 ENABLE EN 9 10 11 12 13 14 15 16 3 VID2 OC+ 4 VID1 OUT1 8 7 6 5 4 3 2 1 Vout/Clk switch * 5 VID0 OUT2 12 +5V .1 LL42 R9 0 D6 VIN .01 .1 FDB7030BL C22 Q4 L2 R22 TTIB1106-450 2.2 Place jumper for EN control of SC1205's 6 ERROUT OC11 7 FB 9 36k VS DRN 6 UVLO R11 8 10k RREF GND 10u,CER C19 10u,CER C20 R10 10u,CER C23 GFB70N03 R15 10u,CER C24 100k EN5 7 R13 0 Q5 2.2 .01 C30 10u,CER C29 10u,CER C28 10u,CER C31 BIPHASE CURRENT MODE CONTROLLER VCORE R18 1 Figure 1: TM SC2422A SCHEMATIC WITH +5V INPUT FOR THE AMD ATHLON PROCESSOR * Droop=95mv at 1.6V and 35A load, with above values. Change R10 to change droop. Large changes may affect DC offsets. R19 controls output offset, set for VID=01010=1.600V SC2422A 6 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A Applications Information The SC2422A is an Input Current Mode Controller designed for High Current, High performance two phase DC/DC converters. The Current mode control is implemented by generating the PWM ramp from the Input Current, rather than the output current. This has the advantage of eliminating the output current sense resistors, and the power loss associated with output current sensing. Eliminating the output current sense resistors has the added advantage of improving the transient response by reducing the output impedance. The output voltage is programmed via a 5-bit DAC in 32 steps. A novel technique allows programmable DAC step size and output offset, allowing the SC2422A based DC/DC converters to work in VRM9.0, VRM 8.3, VRM8.4, VRM8.5 or future specified voltage ranges. ramp voltage equals the error amplifier output signal. The current mode control is inherently immune to input voltage changes because the ramp amplitude reflects the input voltage changes. Since the input current sense resistor is the same for both phases, the inherent inaccuracy due to mismatch between output current sense resistors is avoided. Also, since the comparator threshold is the same for both phases, accurate current matching is achieved between phases. This implements a pulse by pulse current matching with a faster response to changes in output current by monitoring the input current for each phase. Programming the SC2422A Figure 2 below, is the connection schematic for the Internal Error Amplifier. Bandgap 1.5V 3K Theory of Operation Pulse by Pulse Current Matching Vid0 BGOUT (P15) E/A + DAC Vid4 Io ERROUT(P6) The operation of the Input Current Mode, ICM, is as follows: The SC2422A Oscillator generates the OUT1 and OUT2 logic output drives. OUT1 and OUT2 are nonoverlapping and sequentially command an external, power MOSFET driver to turn on the Top MOSFETs. When the Top MOSFET is enhanced (each phase), the input voltage is impressed across the MOSFET and the output Inductor. The AC current in the inductor is: IL = ( VIN − VOUT ) x TON ( VIN = L − Ccomp Rcomp VOUT Ri FB(P7) Rf Ros Figure 2: Error amplifier connections The external components, RI, ROS and RF set the DAC step size, output voltage offset and droop, accordingly. A resistor from RREF (pin 8) to ground programs the frequency as well as the DAC current step size. Programming the Switching Frequency VOUT ) x D FxL Where F is the frequency (per phase) and L is the output inductor. D is the duty cycle and is approximately equal to VO/VIN. The approximation arises from the fact that the Duty cycle extends slightly to compensate for losses in the current path. These losses include RDS_ON of the MOSFET, the Equivalent Series Resistance of the Inductors and the PCB trace resistances. The inductor current flows in the input current sense resistor, generating a PWM ramp, same as in all current mode controllers. The ramp is compared with an amplified, level shifted and filtered version of the output voltage at the PWM comparator. The comparator then outputs a gate drive pulse that terminates when the The oscillator frequency can be selected first by setting the value of RREF resistor (pin 8) to ground. fOSC = 13 k Ω * 500 kHz R REF VIN = 12 V The switching frequency per phase is 1/2 of the above oscillator frequency. 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 Programming the DAC Step Size The SC2422A allows programming the output voltage and the DAC step size by selecting external resistors. The DAC current step size, for one MSB is: IDAC _ MSB = VBG R REF SC2422A where RREF is the resistor from RREF pin to Ground. The DAC MSB voltage step size is calculated as follows: VDAC_MSB = IDAC_MSB * RI VDAC _ LSB = VDAC _ MSB 32 the output voltage specification. As the load is increased, the output “droops” towards the lower limit. This makes optimum use of the output voltage error band, yielding minimum output capacitor size and cost. Active drooping, does not compromise the converter response time as does passive droop techniques. The active droop also allows for an accurate Inter-Module current sharing scheme, where multiple DC/DC converters are required to share the current required by a DC bus. As one module supplies more current, that modules output voltage ”droops”, allowing other modules to provide the balance of the required current.Any changes in the output voltage is instantaneously reflected to the error amplifier, which has a high Slew Rate and wide Gain-Bandwidth product to recover the output voltage to its nominal level with minimal delay. The droop is adjusted by setting the feedback resistor, Rf. While the optimum value of RF may be derived experimentally, the following equation can provide the droop at a given output current: VDROOP = G CA * R I * R S * IOUT 2 RF or VDAC _ LSB = VBG R ∗I R REF 32 Note that changing RREF affects both frequency and DAC step size. RI must be proportionally adjusted to keep the same step size at different frequencies. The advantage of this method is that all new VID specifications can be accommodated by modifying external components while maintaining the required precision without the need for converter redesign. Programming the DAC Offset Voltage Kirchoff’s current law can be applied to the error amplifier’s Inverting node (see figure 2) to calculate ROS, the DAC offset setting resistor. The output Offset at zero DAC current (VID=00000), is set as follows: R OS = VBG VO − VBG VEO − VBG + RI RF The Gain of the current amplifier is set to 20 (26dB), while RS is the input sense resistor. The effective inductance of the sense resistor must be minimized to achieve accurate correlation between the above equation and actual droop achieved. This is because the inductive spike, which may also be caused by layout inductance's, will alter the PWM comparator trip point. The value of RF may have to be adjusted to compensate for such parasitic effects. Since Rf also sets the DC gain of the system, changing the value of Rf affects the offset voltage, which is set via Ros. The value of Ros can be modified to achieve exact offset after the droop resistor has been chosen.It must be noted that the Current Amplifier gain is quite precise, with greater than 80dB of Common Mode Rejection Ratio (CMRR). Thus the droop’s accuracy is limited primarily by external components tolerances and the external parasitic effects. Loop Gain Considerations The Modulator gain in Input Current Mode control is equal to: K MOD = VIN VRAMP Where VEO is the error amplifier output voltage and as a first approximation is equal to 1.75V. Where VBG = Precision Reference Voltage = 1.50V. The value of ROS can be fine trimmed using a potentiometer connected from the FB pin to ground. Programming the Dynamic (Active) Droop The SC2422A employs a novel approach to active drooping for optimum transient response. The output voltage is regulated as a function of output current. At zero current the output is regulated to the upper limit of VRAMP = 0.3 V + R SENSE X TOSC X GCA X VIN − VO L 8 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 Where: RS = Input current sense resistor TOSC = Oscillator period GCA = Current Amplifier Gain 0.3V is the ramp added for slope compensation when the output current is near zero. The DC loop gain is the product of the modulator gain and the error amplifier gain and is calculated as follows: GLOOP = VIN * RF VRAMP * RI SC2422A Considerations in Input Current Mode DC/DC Converters”. This application note is available by contacting the factory. Remote Sensing Capability The SC2422 has a single ground for error amplifier and DAC reference and for the internal biasing of the chip. Since the chip uses approximately 10ma of quiescent current, the ground pin may be connected to a remote location without fear of ground loops. When used as a microprocessor power supply, connecting the ground pin directly to the ground plane may result in undesirable voltage drops in the plane at high output current. This is not entirely predictable since the error amplifier is correcting for the DC error with reference with the ground plane and not the processor “feedback ground”. Thus any voltage difference between the two ground will result in a DC error. This error will obviously consume valuable static error band tolerance. To avoid this DC error, the SC2422 ground pin (pin 9) can be connected to a copper “Island”, to which Rref (frequency setting resistor) and Ros (offset setting resistor) will also be connected. This “Island” in turn will only be connected to the “Processor Feedback” ground via a trace. While the trace may be long, it should not be routed through or near the switching sections or noisy components. This method of remote sensing will alleviate the need for a differential amplifier to sense the output voltage/ output return pair and the design effort and costs associated with it. SC2422A Evaluation Board The SC2422A based DC/DC converter utilizes the SC1205 High Speed MOSFET drivers to achieve VRM 9.0 output Voltage Specifications. SC2422A Evaluation Board Schematic (Figure 1) shows the circuit for a 40A, BiPhase DC/DC converter. The Evaluation board is available by contacting the factory or Semtech website at WWW.Semtech.com. Refer to Application note AN00-1 for detailed treatment of frequency compensation component selection as well as programming the SC2422A. The application note is available on the Semtech website or by contacting the factory. Programming the Under Voltage Lockout The SC2422A may be operated from any supply in +5V to +12V range. A pin has been dedicated to externally selecting the voltage at which the SC2422A outputs are active. A good typical turn-on threshold value is 4.5V for a +5V input supply and 9V for a +12V supply. A voltage divider connected to the UVLO pin selects this threshold. The UVLO comparator trip point is approximately 1.475V. Sufficient hysterisis is provided to ensure proper DC/DC converter shutdown. The UVLO setting should consider external MOSFET driver’s UVLO threshold. Ideally, the external MOSFET driver should turn on before the SC2422 controller and turn off before the controller. This assures the converter output will rise and fall slowly using the soft start feature and that the output voltage will not go negative at turnoff. PCB layout Care must be excercised when laying out the PC board for SC2422 or other input current mode DC/DC converters. SInce the current is delivered and sensed in pulse packets, the inductance of the current carrying traces and thus their length must be minimized. Ceramic bypass capacitors must be located near the sense resistor. For a detailed treatment and circuit parasitic models, consult application note: AN00-7:“Component Selection and PC Board layout 9 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 BIPHASE CURRENT MODE CONTROLLER PRELIMINARY - August 7, 2000 SC2422A OUTLINE DRAWING SO-16 Jedec MS-012AC LAND PATTERN SO-16 ECN00-1242 10 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320