SC2616MLTR

Complete DDR Power Solution POWER MANAGEMENT Description The SC2616 is a fully integrated DDR power solution providing power for the VDDQ and the VTT rails. The SC2616 also completely adheres to the ACPI sleep state power requirements. A synchronous buck controller provides the high current of the VDDQ at high efficiency, while a linear sink/source regulator provides the termination voltage with 2 Amp Source/Sink capability. This approach makes the best trade-off between cost and performance. Additional logic and UVLOs complete the functionality of this single chip DDR power solution in compliance with SLP_S3 and SLP_S5 motherboard signals. The SC2616 is capable of sourcing up to 20A at the switcher output, and 2A source/sink at the VTT output. The MLP package provides excellent thermal impedance while keeping small footprint. VDDQ current limit as well as 3 independent thermal shutdown circuits assure safe operation under all fault conditions. SC2616 Features High efficiency (90%) switcher for VDDQ supplies 20 Amps High current gate drives Single chip solution complies fully with ACPI power sequencing specifications Internal S3 state LDO supplies high standby VDDQ current (0.65 Amp Min.) ACPI sleep state controlled 2 Amp VTT source/sink capability UVLO on 5V and 12V Indepent thermal shutdown for VDDQSTBY and VTT Fast transient response 18 pin MLP package Applications Power solution for DDR memory per ACPI motherboard specification High speed data line termination Memory cards Typical Application Circuit 5VCC 12VCC 5VSBY R3 R9 R1 Q1 Cin C8 U1 16 4 SC2616 5VCC TG BG PGND SLP_S3# SLP_S5# 11 10 SLP_S3 SLP_S5 VDDQSTBY VDDQIN FB 18 17 SS/EN AGN D COMP PAD VTTSNS LGN D VTT VTT 9 15 14 13 7 8 1 2 5 6 C18 R4 Q2 VDDQ L1 Cout 0 0 R7 Q3 0 12VCC 5VSBY 0 0 VTT C15 C14 R5 1k R8 1k C5 0.1uF 12 19 R2 C6 3 0 0 0 0 0 October,13, 2003 1 www.semtech.com SC2616 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Supply Voltage, 5VCC to AGND Supply Voltage, 12VCC to AGND Standby Input Voltage Inputs AGND to PGND or LGND VTT Output Current Operating Ambient Temperature Range Operating Junction Temperature Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Storage Temperature TG/BG DC Voltage TG/BG AC Voltage, t ≤ 100ns ESD Rating (Human Body Model) Symbol V 5V C C V 12V C C V 5V S B Y I/O Maximum 7 15 7 5VSTBY +0.3, AGND -0.3 0.3 Units V V V V V A °C °C ° C/W ° C/W °C V V kV IO(VTT) TA TJ θJA θJC TSTG ±3 0 to 70 125 25 4 -65 to 150 12Vcc + 0.3, AGND -0.5 12Vcc + 1.0, AGND -2.0 ESD 2 Electrical Characteristics Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter 5V Supply Voltage 12V Supply Voltage 5V Standby Voltage Quiescent Current SLP_S3 Threshold SLP_S5 Threshold SLP_S3/SLP_S5 Input Current © 2003 Semtech Corp. Symbol V 5V C C V 12V C C V 5V S B Y IQ(5VSBY) Conditions Min 4.5 10 4.5 Typ 5 12 5 5.2 7.8 TTL TTL Max 5.5 14 5.5 Units V V V mA mA V V µA S 0, S 5 S3, IDDQSTBY = 0 IS3,S5 2 50 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter 12VCC Under Voltage Lockout 5VCC Under Voltage Lockout Feedback Reference Feedback Current SS/EN Shutdown Threshold Thermal Shutdown Thermal Shutdown Hysteresis Symbol UVLO12VCC UVLO5VCC VREF IFB VEN(TH) TJ-SHDN TJ-HYST Conditions Min 8 Typ 9.2 2.5 1.25 Max 10 Units V V V VFB = 1.25V 0.3 150 10 0.5 µA V °C °C Sw itcher Load Regulation Oscillator Frequency Soft Start Current Duty Cycle Overcurrent Trip Voltage Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Dead Time Error Amplifier Transconductance Error Amplifier Gain @ DC Error Amplifier Bandwidth Error Amplifier Source/Sink Current VTRIP TGR TGF BGR BGF td GM A EA GBW RCOMP = open % of VDDQ Setpoint Gate capacitance = 4000pF Gate capacitance = 4000pF Gate capacitance = 4000pF Gate capacitance = 4000pF 20 fOSC ISS 0 70 75 25 25 35 35 50 0.8 38 5 ±60 IVDDQ = 0A to 10A; S0 225 0.2 250 25 95 80 275 % KHz µA % % nS nS nS nS nS mS dB MHz µA © 2003 Semtech Corp. 3 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Sw itcher (Cont.) PWM Ramp S TB Y LD O Output Current Load Regulation Current Limit V TT LD O Output Voltage Symbol Conditions Min Typ Max Units VRAMP Peak to Peak 0.55 V IVDDQSTBY ∆ V/∆ I ILIM DC current IVDDQ = 0A to 460mA; S3 S LP _S 3 = 0 650 750 0.3 2.3 850 0.5 mA % A VTT VVDDQSTBY = 2.500V IVTT = 1.8A to -1.8A 1.237 1.250 1.267 1.225 1.250 1.275 ±1.8 ±2 ±0.5 75 ±1.0 V A % dB A Source and Sink Currents Load Regulation Error Amplifier Gain Current Limit IVTT ∆ VTT/ ∆ I AEA_VTT VTTILIM SLP_S3 = high (sink) SLP_S3 = high (source) IVTT =+1.8A to -1.8A 3 3 © 2003 Semtech Corp. 4 www.semtech.com SC2616 POWER MANAGEMENT Pin Configuration TOP VIEW FB VTTSNS LGND 5VSBY VTT VTT VDDQSTBY VDDQIN 5VCC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 SS/EN COMP 12VCC TG BG PGND AGND SLP_S3 SLP_S5 Ordering Information Part Numbers SC2616MLTR(1) P ackag e MLP-18 Note: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (18 Pin MLP) Note: Pin 19 is the thermal Pad on the bottom of the device Pin Descriptions Pin # 1 2 3 4 5, 6 7 Pin Name FB VTTSNS LGND 5V S B Y VTT Pin Function Feedback for the STBY LDO and the switcher for VDDQ. VTT LDO feedback and remote sense input. VTT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2A of current. Bias supply for the chip. Connect to 5V standby. VTT output. Connect to point of load. The trace connecting to this pin must be able to carry 2A of current VDDQSTBY S3 VDDQ output. Provision must be made to prevent the VDDQSTBY supply from back feeding the input supply (see typical application schematic). Traces connecting to this pin must be capable of carring 0.85A of current. VDDQIN 5V C C S LP _S 5 S LP _S 3 AGND PGND BG TG 12V C C COMP SS/EN TH_PAD VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 A of current. Supply to the lnternal logic Connect to SLP_S5 signal from motherboard. Connect to SLP_S3 signal from motherboard. Analog ground. Gate drive return. Keep this pin close to bottom FET source. Bottom gate drive. Top gate drive. Supply to the upper and lower gate drives. Compensation pin for the PWM transconductance amplifier. Soft start capacitor to AGND. Pull low to less than 0.3V to disable the controller. Copper pad on bottom of chip used for heatsinking. This pin must be connected to ground plane under IC. (See application information). 5 www.semtech.com 8 9 10 11 12 13 14 15 16 17 18 19 © 2003 Semtech Corp. SC2616 POWER MANAGEMENT Block Diagram E/A © 2003 Semtech Corp. 6 www.semtech.com SC2616 POWER MANAGEMENT Timing Diagram UVLO 5V,12V Rails SLP_S3 SLP_S5 1.25V 1.0V SS/EN Internal PGOOD 0.3V TG BG VDDQSTBY VTT Vddqsb Vddqsw VDDQ S5 S0 S3 S0 S5 © 2003 Semtech Corp. 7 www.semtech.com SC2616 POWER MANAGEMENT Applications Information Description The Semtech SC2616 DDR power supply controller offers a switching and linear regulator combination to provide the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. VDDQ supply, and VTT termination voltage are supplied to the Memory bus during S0 (normal operation) state. During S0, VDDQ is supplied via the Switching regulator, sourcing high output currents to the VDDQ bus as well as supplying the termination supply current. The SC2616 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply. The VTT termination voltage is an internal sink/source linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking 2 Amps (max). The current limit on this pin is set to 3 Amps (typical). Output Current and PCB layout The current handling capacity of SC2616 depends upon the amount of heat the PC board can sink from the SC2616 thermal pad. (See thermal considerations). The PC board layout must take into consideration the high current paths, and ground returns for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND traces must also be routed using wide traces to minimize power loss and heat in these traces, based on the current handling requirements. S3 and S5 States During S3 and S5 sleep states, the operation of the VDDQ and VTT supplies is governed by the internal sequencing logic in strict adherence with motherboard specifications. The timing diagram demonstrates the state of the controller, and each of the VDDQ and VTT supplies during S3 and S5 transitions. When SLP_S3 is low, the VDDQ supplies the “Suspend To RAM” current of 650 mA (min) to maintain the information in memory while in standby mode. The VTT termination voltage is not needed during this state, and is thus tri-stated during S3. Once SLP_S3 goes high, the VDDQ switcher recovers and takes control of the VDDQ supply voltage. When SLP_S5 and SLP_S3 are both pulled low, all supplies shut down. The SS/EN pin must be pulled low ( VT IT 2 L ⋅ IT 2 ⋅ VT ⋅ VA where VA = VIN − VO for negative transients (load application) and VA = VO for positive transients (load release) values for positive and negative transients must be calculated seperately and the worst case value chosen. For Capacitor values, the calculated value should be doubled to allow for duty cycle limitation and voltage drop issues. www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) Compensation Components Gpwm L EA R Vbg 1.25Vdc C Vin Rc Co Ro R1 The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: (1) Calculate the corner frequency of the output filter: R2 F o := 1 2⋅ π⋅ L⋅ C o Fig. 1. SC2616 control model. (2) Calculate the ESR zero frequency of the output filter capacitor: F esr := 1 2⋅ π⋅ R c⋅ C o The control model of SC2616 can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of: G m := 0.0008A ⋅ V (3) Check that the ESR zero frequency is not too high. F esr < F sw 5 The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is proportional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by: G pwm 1 V ramp If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : F x_over ≤ F sw 5 where the ramp amplitude (peak-to-peak) is 0.55 volts when input voltage is 5 volts. The total control loop-gain can then be derived as follows: 1 s. R. C . T( s) T o . s. R. C 1 s. R c. C o 1 s. R c. C o L Ro 2 s . L. C o . 1 If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: Rc Ro ⎛ F esr ⎞ R := ⋅⎜ G pwm ⋅ V in⋅ G m ⎝ F o ⎠ 1 2 ⋅⎜ ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⎝ F esr ⎠ ⎝ V bg ⎠ where when T o := G m⋅ G pwm ⋅ V in⋅ R ⋅ ⎜ ⎛ V bg ⎞ ⎝ Vo ⎠ 10 F o < F esr < F x_over www.semtech.com © 2003 Semtech Corp. SC2616 POWER MANAGEMENT Applications Information (Cont.) or 2 F.o Step 1. Output filter corner frequency ⎛ Fo ⎞ R := ⋅⎜ G pwm ⋅ V in⋅ G m ⎝ F esr ⎠ 1 ⋅⎜ ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⎝ F o ⎠ ⎝ V bg ⎠ Fo = 1.13 KHz Step 2. ESR zero frequency: Fesr = 4.019 KHz when F esr < F o < F x_over Step 3. Check the following condition: F sw 5 (5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency: Fo 5 F esr < Which is satisfied in this case. F zero C Step 4. Choose crossover frequency and calculate compensator R: zero 1 .π.R .F 2 Fx_over = 50 KHz R = 43.197 KΩ Step 5. Calculate the compensator C: C = 16.287 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given as: V V I F in o o := 5 V := 2.5 V := 20 A sw := 250 KHz L := 3 µH C R R R © 2003 Semtech Corp. o c 1 2 := 6600 µF := 0.006 Ω := 1.0 KΩ := 1.0 KΩ 11 www.semtech.com SC2616 POWER MANAGEMENT 100 50 0 50 10 100 Loop Gain Mag (dB) mag ( i ) 3 1 . 10 Fi 4 1 . 10 5 1 . 10 6 1 . 10 0 phase ( i ) 45 90 135 180 10 100 Loop Gain Phase (Degree) 3 1 . 10 Fi 4 1 . 10 5 1 . 10 6 1 . 10 Fig. 2. Bode plot of the loop © 2003 Semtech Corp. 12 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) Evaluation Board Schematic 5VCC D1 12VCC R13 2.2R C13 1uF C5 0.1uF C6 15n R2 43K 1N 4148 VTT 1 5 0 0 u F /6 .3 V C15 4.7uF C14 5VSBY 4 .7 u F /6 .3 V IP D 1 3 N 0 3 L R1 2R2 Q1 C19 5VCC 0 0 1 5 0 0 u F /6 .3 V 1 5 0 0 u F /6 .3 V 1 5 0 0 u F /6 .3 V C1 IP D 09N 03LA Q2 R4 2R2 C2 4 .7 u F /6 .3 V 0 FB 1 2 U1 FB VTTSNS LGND 5VSBY VTT VTT SS/EN COMP 12VCC TG BG PGND 18 17 16 15 14 13 12 11 10 C7 non pop. 12VCC C3 C4 R3 2R2 C8 0 1uF VDDQ 0 3 4 5 6 7 8 0 L1 3uH R5 1k FB R8 1k Q3 R7 2R2 R6 2R2 C16 1n IP P 06N 03LA 3 3 0 0 u F /6 .3 V 3 3 0 0 u F /6 .3 V 4 .7 u F /6 .3 V 4 .7 u F /6 .3 V C9 C10 C11 C12 VDDQSTBY AGND VDDQIN 5VCC SLP_S3 PAD SLP_S5 0 VDDQ SLP_S3 SLP_S5 9 0 0 C17 1uF SC2616 R9 2R2 C18 1uF 19 0 5VCC 0 0 load point (do not connect to the inductor output at the VDDQ plane near the controller/FETS. Place the voltage divider at the load point and route the divider center and the sense ground close together as a differential pair. Connect the AGND and the sensed ground and LGND at the chip. 5. The VTTSNS must be connected to a distant load point. 6. Adequate copper area must be allocated to both VDDQ and VTT. The copper coverage must be uniform, i. e. it provides low resistance to all areas around the DIMMs. VDDQIN traces (and vias if used to carry current) must be adequate for 2.0Amps. 7. Make the phase node area, which connects the Inductor, Top FET and the Bottom FET, as small as possible to prevent EMI, and ringing. Avoid making this 13 www.semtech.com Guidelines for Layout of DDR Supply Using SC2616 DDR Controllers on Typical Motherboards Signals of arbitrary importance (signals that can be routed last, such as SLP_S3, SLP_S5, 5VCC) have been omitted for simplicity. Parameters of importance in the Layout of the DDR power section are as follows (in order of importance): 1. The VTT decoupling cap,C15, must be placed less than 0.25 inch from Controller. 2. The power rail decoupling cap,C4, must be placed less than 0.25 inch from Q2 drain. 3. The decoupling caps for 5VSBY AND 12Vcc,C13 and C8, must be placed very close to the controller(0.25inch or less) 4. The VDDQ sense lines must be routed from a distant © 2003 Semtech Corp. SC2616 POWER MANAGEMENT Applications Information (Cont.) connection using Vias, to minimize inductance. 8. Route gate drive traces on the Top layer as much as possible, with traces 25 mil or wider. If Vias are used, use multiple vias. While gate drive resistors are not required, they may be needed to reduce ringing if the traces are long and inductive. 9. Place components R2,C5, C6 and C7 near the controller, preferably on an analog ground island. 10. Keep Input electrolytic capacitors near the FETs, to minimize AC current loops. The traces connecting to pins 9, 10, 11 are not critical, since low currents flow in these paths. Thermal considerations 11. The controller must be placed on a copper land, with at least 0.5” square area. Remove the Soldermask under the IC, as shown in the recommend landing pattern in this datasheet. The Solder-mask cutout area(also referred as stencil aperture) allows the Ground contact at the bottom of the controller (pin 19) to be directly soldered to the PC board for heatsinking to the PC board. There must be at least 5 vias connecting the top and bottom layers on this plane to reduce thermal resistance. These thermal vias must be minimum diameter for the PCB process(12mil drill for 62mil thick PCB). Also it is better to plug the vias by copper plating and solder plating. Making the soldermask cutout area too large will add to the risk of solder flowing near the pins and causing shorted connections. 12. The FETs must be placed on a copper area large enough to adequately transfer heat from the FETs to the PC board. Multiple vias aid in cooling the copper area surrounding the FETs, thus reducing the FETs’ junction to ambient thermal resistance. © 2003 Semtech Corp. 14 www.semtech.com SC2616 POWER MANAGEMENT Outline Drawing - MLP-18 TERMINAL 1 IDENTIFIER TOP VIEW TERMINAL 1 BOTTOM VIEW 1 CONTROLLING DIMENSIONS: MILLIMETERS © 2003 Semtech Corp. 15 www.semtech.com SC2616 POWER MANAGEMENT Recommended Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2003 Semtech Corp. 16 www.semtech.com