SC2659SWTR

Programmable Synchronous DC/DC Hysteretic Controller with VRM 8.5 VID Range POWER MANAGEMENT Description The SC2659 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC2659 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium® llI and Athlon®, in both single and multiple processor configurations. Inhibit, under-voltage lockout and soft-start functions are included for controlled power-up. SC2659 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.050V to 1.825V in 25mV increments. The SC2659 high side driver can be configured as either a ground-referenced or as a floating bootstrap driver. The high and low side MOSFET drivers have a peak current rating of 2 amps. SC2659 Features Programmable hysteresis 5 bit DAC programmable output (1.050V-1.825V) On-chip power good and OVP functions Designed to meet latest Intel specifications Up to 95% efficiency VIDs pulled up to +3.3V Applications Server Systems and Workstations Pentium® III Core Supplies AMD Athlon® Core Supplies Multiple Microprocessor Supplies Voltage Regulator Modules Typical Application Circuit +5V R1 * R3 * R2 1k 2 DROOP VID0 27 U1 SC2659 1 IOUT PWRGD 28 R9 10k R10 1k PWRGD "POWER GOOD" C6 0.1 R4 1k INHIB 3 OCP VID1 26 "INHIBIT" R11 1k C7 0.1 4 VHYST VID2 25 R5 * C1 0.1 C2 0.001 5 VREFB VID3 24 L1 0.5uH R6 20k 6 VSENSE VID25 23 + Cin HF Cin Bulk 7 AGND INHIBIT 22 Vin +5V/12V 8 SOFTST IOUTLO 21 _ C8 0.033 C3 0.1 +5V 9 N/C LOSENSE 20 10 LODRV HISENSE 19 C4 0.01 11 LOHIB BOOTLO 18 Q1 FDB6035AL R12 1.0 12 DRVGND HIGHDR 17 13 LOWDR BOOT 16 +12V L2 1.0uH C9 1.0 Q2 FDB7030BL R14 1.6 Cout Bulk Cout HF + 14 DRV VIN12V 15 1.05 to 1.825V C5 C10 _ R8 10k R7 * *) for the values see specific application circuit somewhere else in the datasheet Revision: December 10, 2003 1 www.semtech.com SC2659 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter VIN12V BOOT to DRVGND BOOT to BOOTLO Digital Inputs AGND to DRVGND LOHIB to AGND LOSENSE to AGND IOTLO to AGND HISENSE to AGND VSENSE to AGND Continuous Power Dissipation, TA = 25 0C Continuous Power Dissipation, TC = 25 0C Operating Junction Temperature Range Lead Temperature (Soldering) 10 Sec. Storage Temperature Symbol VINMAX Maximum -0.3 to 14 -0.3 to 25 -0.3 to 15 -0.3 to 7.3 ±0.5 -0.3 to 14 -0.3 to 14 -0.3 to 14 -0.3 to 14 -0.3 to 5 Units V V V V V V V V V V W W °C °C °C PD PD TJ TL TSTG 1.2 6.25 0 to +125 300 -65 to 150 DC Electrical Characteristics Unless specified: 0 < TJ < 125°C, VIN = 12V Parameter Supply Voltage Range Supply Current (Quiescent) Symbol VIN12V IINq Conditions Min 11.4 Typ 12 15 Max 13 Units V mA INH = 5V, Vin above UVLO threshold during start-up, fsw = 200 kHz, BOOTLO = 0V, C D H = C D L = 50pF INH = OV or Vin below UVLO threshold during start-up, BOOT = 13V, BOOTLO = 0V INH = 5V, VIN above UVLO threshold during start-up, fsw = 200kHz, BOOT = 13V, BOOTLO = 0V, C D H = 50pF High Side Driver Supply Current (Quiescent) IBOOTq 2 mA 5 mA  2003 Semtech Corp. 2 www.semtech.com SC2659 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Unless specified: 0 < T < 125°C, VIN = 12V J Parameter Reference/Voltage Identification Reference Voltage Accuracy Symbols Conditions Min Typ Max Units VREF 11.4V < VIN12V< 12.6V, over full VID range (see Output Voltage Table) -1.2 1.2 % VID0 - VID25mV High Threshold Voltage VID0 - VID25mV Low Threshold Voltage Pow er Good Undervoltage Threshold Output Saturation Voltage Hysteresis Over Voltage Protection OVP Trip Point Hysteresis Soft Start Charge Current (1) VTH(H) VTH(L) 2.25 1 V V VTH(PWRGD) VSAT VHYS(PWRGD) IO = 5mA 82 0.5 10 88 %VREF V mV VOVP VHYS(OVP) 12 15 10 20 %VOUT mV ICHG VSS = 0.5V, resistance from VREFB pin to AGND = 20kΩ, VREFB = 1.3V Note: ICHG = (IVREFB / 5) V(SS) = 1V 10.4 13 15.6 µA Discharge Current Inhibit Comparator Start Threshold VIN 12V UVLO Start Threshold Hysteresis Hysteretic Comparator Input Offset Voltage Input Bias Current Hysteresis Accuracy Hysteresis Setting Idischg 1 mA Vstart(NH) 1 2.0 2.4 V VstartUVLO VhysUVLO 9.25 1.8 10.25 2.1 11.25 2.4 V V VosHYSCMP IbiasHYSCMP VHYS ACC VHYS SET VDROOP pin grounded 5 1 7 60 mV uA mV mV  2003 Semtech Corp. 3 www.semtech.com SC2659 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Parameter Droop Compensation Initial Accuracy Overcurrent Protection OCP Trip Point Input Bias Current High-Side VDS Sensing Gain Initial Accuracy IOUT Source IOUT Sink Current VIOUT AC C Symbols Conditions Min Typ Max Units VDROOP ACC VDROOP = 50 mV 8 mV VOCP IbiasOCP 0.09 0.1 0.11 100 V nA 2 VHISENSE = 12V, VIOUTLO = 11.9V VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V VIOUT =0.05V, VHISENSE = 12V, VIOUTLO = 12V VHISENSE = 11V, RIOUT = 10K Ω VHISENSE = 4.5V, RIOUT = 10k Ω VHISENSE = 3V, RIOUT = 10k Ω VHISENSE = 4.5V (Note 1) VHISENSE = 4.5V (Note 1) (Note 1) 50 65 500 38 0 0 0 2.85 1.8 80 50 3.75 2.0 1.0 6 V/V mV µA µA V V V V V Ω IsourceIOUT IsinkIOUT VIOUT(11) VIOUT Voltage Swing VIOUT(4.5V) VIOUT(3V) LOSENSE High Level Input Voltage LOSENSE Low Level Input Voltage Sample/Hold Resistance Buffered Reference VREFB Load Regulation Deadtime Circuit (1) LOHIB High Level Voltage LOHIB Low Level Input Voltage LOWDR High Level Input Voltage LOWDR Low Level Input Voltage Drive Regulator DRV Voltage Load Regulation Short Circuit Current VihLOSENSE VilLOSENSE RS/H VldregREFB 10µA < IREFB < 500µA 2 mV VihLOHIB VilLOHIB VihLOWDR VilLOWDR 2 1.0 2 1.0 V V V V VDRV VldregDRV IshortDRV 11.4 < VIN12V < 12.6V, IDRV = 50mA 1mA < IDRV < 50mA 7 100 100 9 V mV mA  2003 Semtech Corp. 4 www.semtech.com SC2659 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Parameter High-Side Output Driver Peak Output Current IsrcHIGHDR IsinkHIGHDR Equivalent Output Resistance RsrcHIGHDR RsinkHIGHDR Low -Side Output Driver Peak Output Current IsrcLOWDR IsinkLOWDR Equivalent Output Resistance RsrcLOWDR RsinkLOWDR duty cycle < 2%, tpw < 100us, TJ = 125°C VDRV = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (sink) TJ = 125°C VDRV = 6.5V, VLOWDR = 6V TJ = 125°C VDRV = 6.5V, VLOWDR = 0.5V 2 A duty cycle < 2%, tpw < 100us, TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src), or VHIGHDR = 5V (sink) TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V 45 Ω 5 2 A Symbol Conditions Min Typ Max Units 45 Ω 5 AC Electrical Characteristics (Note 1) Parameter Hysteretic Comparators Propagation Delay Time from VSENSE to HIGHDR or LOWDR (excluding deadtime) Output Drivers HIGHDR rise/fall time LOWDR rise/falltime Overcurrent Protection Comparator Propagation Delay Time Deglitch Time (Includes comparator propagation delay time) tOVPROP tOVDGL 2 1 5 µs µs trHIGHDR trHIGHDR trLOWDR tfLOWDR CI = 9nF, VBOOT = 6.5v, VBOOTLO = grounded, TJ =125°C CI = 9nF, VDRV = 6.5V, TJ =125°C 60 60 ns ns tHCPROP 10mV overdrive, 1.3V ≤ Vref ≤ 1.8V 150 250 ns Symbol Conditions Min Typ Max Units  2003 Semtech Corp. 5 www.semtech.com SC2659 POWER MANAGEMENT AC Electrical Characteristics (Cont.) (Note 1) Parameter Overvoltage Protection Comparator Propagation Delay Time Deglitch Time (Includes comparator protection delay time) High-Side Vds Sensing Response Time tVDSRESP VHISENSE = 12V, VIOUTLO pulsed from 12V to 11.9V, 100ns rise and fall times VHISENSE = 4.5V, VIOUTLO pulsed from 4.5V to 4.4V, 100ns rise and fall times VHISENSE = 3V, VIOUTLO pulsed from 3.0V to 2.9V, 100ns rise and fall times Short Circuit Protection Rising Edge Delay Sample/Hold Switch turn-on/turn-off Delay Pow er Good Comparator Propagation Delay Softstart Comparator Propagation Delay Deadtime Driver Non-overlap Time LODRV Propagation Delay TLODRVDLY 400 ns tNOL CLOWDR = 9nF, 10% threshold on LOWDR 30 100 ns tSLST overdrive = 10mV 560 900 ns tPWRGD 1 µs tVDSRED tSWXDLY LOSENSE grounded 3V < VHISENSE < 11V VLOSENSE = VHISENSE 300 30 2 µs tOVPROP tOVDGL 1 1 3 µs µs Symbols Conditions Min Typ Max Units 3 µs 3 µs 500 100 ns ns Note: (1) Guaranteed, but not tested. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2003 Semtech Corp. 6 www.semtech.com SC2659 POWER MANAGEMENT Test Circuit Timing Diagram Simplified Block Diagram  2003 Semtech Corp. 7 www.semtech.com SC2659 POWER MANAGEMENT Pin Configuration Top View Ordering Information Device (1) P ackag e SO-28 Temp Range (TJ) 0° to 125°C SC2659SWTR S C 2659E V B Evaluation Board Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (28-Pin SOIC) Pin Descriptions Pin # 1 Pin Name IOUT DROOP 2 3 4 5 6 7 8 9 10 11 12 13 OCP VHYST VREFB VSENSE AGND SOFTST NC LODRV LOHIB DRVGND LOWDR Pin Function Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD. Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a function of load current. The voltage is set by a resistor divider between IOUT and AGND. Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. Buffered Reference Voltage (from VID circuitry). Output Voltage Sense. Small Signal Analog and Digital Ground. Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. Not connected. Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. Low Side Inhibit. This pin is used to eliminate shoot-thru current. Power Ground. Insure output capacitor ground is connected to this pin. Low Side Driver Output. Connect to gate of low side MOSFET. 8 www.semtech.com  2003 Semtech Corp. SC2659 POWER MANAGEMENT Pin Descriptions (Cont.) Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name DRV VIN12V BOOT HIGHDR BOOTLO HISENSE LOSENSE IOUTLO INHIBIT VID25 VID3 VID2 VID1 VID0 PWRGD Pin Function Drive Regulator for the MOSFET Drivers. 12V Supply. Connect to 12V power rail. Bootstrap. This pin is used to generate a floating drive for the high side FET driver. High Side Driver Output. Connect to gate of high side MOSFET. Bootstrap Low. In applications where VIN ≤ 5V is used as a power source, this pin can be connected to DRVGND. High Current Sense. Connected to the drain of the high side FET,or the input side of a current sense resistor between the input and the high side FET. Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. Programming Input . Programming Input. Programming Input. Programming Input. Programming Input . Power Good. This open collector logic output is high if the output voltage is within 15% of the set point.  2003 Semtech Corp. 9 www.semtech.com  2003 Semtech Corp. POWER MANAGEMENT Block Diagram PWRGD IOUT HISENSE IOUTLO LOSENSE SOFTST ++ -- 50uA G=2 ANALOG BIAS PREREG Vcc VIN12V I(VREFB) / 5 FAULT BANDGAP RISING EDGE DELAY DRIVE REGULATOR DRV R + - Q - + S SHUTDOWN 1.15VREF 0.85VREF HIGHDR LOWDR FILTER 0.85VREF BOOT DEGLITCH UVLO + + + INH DEGLITCH HIGHDR 10 VID DAC FILTER - + - + BOOTLO 10V + + Vcc VREF FILTER 1.15VREF + + - - VSENSE - LOWDR DRVGND + - + 2V VREF 100mV OCP AGND INHIBIT VID0 VID2 VID25 VID1 VID3 DROOP VSENSE VHYST VREFB LOHIB LODRV www.semtech.com SC2659 SC2659 POWER MANAGEMENT Output Voltage Table 0 = GND, 1 = OPEN VID25mV (2) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID3 (1) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 (1) 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID1 (1) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VIDO (1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDC (V) 1.05 1.075 1.10 1.125 1.15 1.175 1.20 1.225 1.25 1.275 1.30 1.325 1.35 1.375 1.40 1.425 1.45 1.475 1.50 1.525 1.55 1.575 1.60 1.625 1.65 1.675 1.70 1.725 1.75 1.775 1.80 1.825 NOTE: (1) VID (3:0) correspond to legacy VRM 8.4 voltage levels for 1.3V - 1.8V. (2) VID 25mV provides a 25mV increment.  2003 Semtech Corp. 11 www.semtech.com SC2659 POWER MANAGEMENT Applications Information - Functional Description Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +3.3V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 1.050V to 1.825V in 25mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VREF is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the REFB pin. The voltage on this pin will be within 3mV of VREF. It is not recommended to drive loads with REFB other than setting the hysteresis of the hysteretic comparator, because the current drawn from REFB sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis of tne comparator will be equal to twice the voltage difference between REFB and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink current. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When  2003 Semtech Corp. configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the FET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 2 volts, and the low side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit that controls the high-side driver, to filter out noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side FET while it is turned on. The sampling network consists of an internal 50Ω switch and an external 0.033µF hold capacitor. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF equal to VREF • (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load 12 www.semtech.com SC2659 POWER MANAGEMENT Applications Information - Functional Description (Cont.) current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on the DROOP pin from VREF. The voltage on the IO pin is divided down with an external resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to: VOUT = VREF • (1+R7/R8) - IOUT • R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INH goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INH, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. VIN The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SS and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current proportional to VREF, the power-up time for VOUT will be independent of VREF. Thus, CSS can remain the same value for all VID settings. The soft start charging current is determined by the following equation: ISS = IREFB/5. Where IREFB is the current flowing out of the REFB pin. It is recommended that no additional loads be connected to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by REFB is 500µA. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 15% (nominal) below VREF, then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VREF, than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side FET. The overcurrent threshold is adjustable with an external resistor divider between IO and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side FET against a short-toground fault on the terminal common to both power FETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA. 13 www.semtech.com  2003 Semtech Corp. +5V  2003 Semtech Corp. U1 SC2659 PWRGD +12V PWRGD 28 1 IOUT R10 10k R11 1k "POWER GOOD" +12V R1 2k 2 DROOP VID0 27 J0 GND INHIB J1 C9 0.1 R3 4.3k 3 OCP VID1 26 POWER MANAGEMENT Application Circuit C1 C2 "INHIBIT" R12 1k C10 0.1 0.001 4 VHYST VID2 25 0.001 J2 R2 1k 5 VREFB VID3 24 R4 1k J3 L1 6 VSENSE VID25 23 R5 150* C3 0.1 POS/IN R6 20k J4 0.5uH C4 0.1 + Vin +5V/12V 7 AGND INHIBIT 22 C5 0.001 8 SOFTST IOUTLO 21 R13 0 R14,15,16 0 C15-23 1.0 C24-32 820uF 16V _ C11 0.033 R17 NS C12 22.0 R19 0 GND/IN +5V 19 C6 0.1 9 N/C LOSENSE 20 14 R18 NS D1 MBRA130L 18 LODRV HISENSE LOHIB BOOTLO DRVGND 2pl. R7 100 10 C7 0.01 Q1 R20 FDB6035AL 1.0 R24,25 3.3 C33,34 LOWDR BOOT 16 11 12 HIGHDR 17 Q2 R21 FDB6035AL 1.0 13 0.0022 2pl. L2 1.0uH@40A POS/OUT +12V DRV VIN12V 15 C13 1.0 Q3 FDB7030BL + R26,27 3.3 2pl. 14 R22 1.6 Q4 FDB7030BL R23 1.6 C37-46 1500uF 6.3V C35,36 0.0022 2pl. C47-58 10.0 D2(opt) MBRB3030CT Vout=1.7Vtyp. C8 2.2 C14 2.2 _ GND/OUT D(opt) MBRA130L R9 150 R8 10k C59 1.0 L1 - #T51-26C, 2ts, 18AWG L2 - #77310-A7, 3ts, 4x20AWG www.semtech.com SC2659 SC2659 POWER MANAGEMENT Typical Characteristics VIN = 5V; IOUT = 0A to 40A “Droop” & “Offset” Disabled VOUT = 1 .8V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40 Efficiency VOUT = 1 .5V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40 Efficiency VOUT = 1 .1V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40  2003 Semtech Corp. Efficiency 15 www.semtech.com SC2659 POWER MANAGEMENT Typical Characteristics (Cont.) VIN = 12V; IOUT = 0A to 40A “Droop” & “Offset” Disabled VOUT = 1 .8V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40 Efficiency VOUT = 1 .5V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40 Efficiency VOUT = 1 .1V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40 Efficiency  2003 Semtech Corp. 16 www.semtech.com SC2659 POWER MANAGEMENT Evaluation Board Artwork Top Layer Bottom Layer Mid Layer  2003 Semtech Corp. 17 www.semtech.com SC2659 POWER MANAGEMENT Evaluation Board Artwork (Cont.) Top Overlay Bottom Overlay  2003 Semtech Corp. 18 www.semtech.com SC2659 POWER MANAGEMENT Materials List Quantity 3 6 1 1 11 2 9 10 12 4 1 1 1 1 2 2 1 4 1 1 1 1 2 1 2 2 4 1 Reference C1,C2,C5 C3,C4,C6,C7,C9,C10 C11 C 12 C13, C15-C23, C59 C8,C14 C 24 - C 32 C 37 - C 46 C 47 - C 58 C 33 - C 36 D1 D2 (optional) L1 L2 Q1,Q2 Q3,Q4 R1 R2,R4,R11,R12 R3 R6 R5 R7 R8,R10 R9 R20,R21 R22,R23 R24,R25,R26,R27 U1 Part/Description 0.001µF 0.1µF 0.033µF 22µF 1µF 2.2µF 820µF, 16V 1500µF, 6.3V, thru hole 10µF .0022µF MBRA130L. Schottky MBRB2515L 0.5uH, Toroid 1.0uH, Toroid D2Pak, MOSFET D2Pak, MOSFET 2k 1k 4.3k 20k 150 * 100 10k 150 1 1.6 3.3 SC2659CSW.TR Vendor TDK, Murata, Taiyo-Yuden any any any any any SANYO P/N: 16MV820AX SANYO P/N: 6R3MV1500AX any any ON Semi ON Semi Micrometals P/N: T51-26C, 18 AWG Magnetics, #77310, 3ts, 4 X 20 AWG Fairchild P/N: FDB6035AL Fairchild P/N: FDB7030BL any any any any any any any any any any any Semtech Corp. 805-498-2111  2003 Semtech Corp. 19 www.semtech.com SC2659 POWER MANAGEMENT Layout Guidelines (See pg. 1) 1. Locate R8 and C2 close to pins 6 and 7. 2. Locate C1 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C5 and C10 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin. 9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. 10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND. Outline Drawing - SO-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2003 Semtech Corp. 20 www.semtech.com