SC410MLTRT

SC410 3A EcoSpeed TM Step-Down Regulator with LDO and Ultrasonic Power Save POWER MANAGEMENT Features Input voltage — 5.5V to 24V Output voltage — 0.75V to 7.5V Output current — Up to 3A Internal reference — + 1% Small ceramic capacitors Power good pin (open-drain) Patented adaptive on-time control: Excellent transient response Programmable pseudo-fixed frequency during CCM Fault protection features: Cycle-by-cycle current limit Short circuit protection Over and under output voltage protection Over-temperature Internal soft-start Ultrasonic power save and smart PSAVE Internal LDO for bias voltage Ultra-small lead-free 3 x 3mm, 10-Pin MLPD package WEEE and RoHS compliant Description The SC410 is an integrated, synchronous 3A EcoSpeedTM step-down regulator. It incorporates Semtech’s advanced, patented adaptive on-time architecture to achieve bestin-class dynamic performance using point-of-load applications. The input voltage range is 5.5V to 24V with a programmable output voltage from 0.75V up to 7.5V. The device features an internal LDO and ultrasonic PSAVE mode for high efficiency across the output load range. Adaptive on-time control provides programmable pseudo-fixed frequency operation in continuous conduction and excellent transient performance. The switching frequency can be set from 200kHz to 1MHz, allowing the designer to reduce external LC filtering and minimize light load (standby) losses. Additional features include cycle-by-cycle current limit, soft start, input UVLO and output OV protection, and over temperature protection. The open-drain PGOOD pin provides output status. Standby current is less than 10μA when disabled. The device is available in a low profile, thermally enhanced MLPD 3 x 3mm 10-pin package. • • • • • • Applications Networking Equipment, Embedded Systems Medical Equipment, Office Automation Instrumentation, Portable Systems Consumer Devices such as DTV and Set-top Boxes POL Converters Typical Application Circuit SC410 Enable VIN EN VIN PGOOD CBST BST LX L1 COUT RTON LDO CLDO1 AGND FB PGND RBOT RTOP VOUT PGOOD TON CIN CLDO2 October 26, 2010 © 2010 Semtech Corporation 1 SC410 Pin Configuration Ordering Information Device SC410MLTRT(1)(2) SC410EVB BST VIN LX PGND PGOOD 1 2 3 4 5 TOP VIEW 10 9 8 7 6 LDO AGND TON EN FB Package MLPD-10 3 x 3 Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. MLPD; 3 x 3, 10 LEAD θJA = 40°C/W Marking Information 410 yyww xxxx yyww = Date code xxxx = Lot number 2 SC410 Absolute Maximum Ratings LX to GND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +28 VIN to PGND, EN/PSV to AGND (V) . . . . . . . . . . . . -0.3 to +28 VIN to LDO (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0 . 3 BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +34 LDO to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 FB, PGOOD, TON (V) . . . . . . . . . . . . . . . . . . . . -0.3 to LDO +0.3 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 Maximum Peak Inductor Current (A) . . . . . . . . . . . . . . . . . 5 . 5 Peak IR Reflow Temperature (°C ) . . . . . . . . . . . . . . . . . . . . . 260 ESD Protection Level (kV)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Recommended Operating Conditions Supply Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . 5.5 to 24 Maximum Continuous Output Current (A) . . . . . . . . . . . . . 3 Maximum Peak Inductor Current (A) . . . . . . . . . . . . . . . . . 5.0 Thermal Information Storage Temperature (°C ) . . . . . . . . . . . . . . . . . . -60 to +150 Maximum Junction Temperature (°C ) . . . . . . . . . . . . . . . . 150 Operating Junction Temperature (°C ) . . . . . . . -40 to +125 Thermal Resistance, Junction to Ambient(2) (°C/W ) . . . . 40 Electrical Characteristics Unless specified: VIN =12V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C, per detailed application circuit Parameter Input Supplies Conditions Min Typ Max Units VIN UVLO Threshold VIN UVLO Hysteresis Internal Bias UVLO Threshold Internal Bias UVLO Hysteresis Programmable with EN pin after 2 switching cycles 1.5 50 V mV V V μA mA Rising UVLO V TH 4 0.3 VEN = 0V VIN Supply Current IOUT= 0A, fSW=25kHz(1) 9 2.5 Controller FB On-Time Threshold Frequency Programming Range Minimum Frequency Range FB Input Bias Current See RTON Calculation during Ultrasonic PSAVE FB=5V or 0V -1 0.7425 200 22 +1 0.75 0.7575 1000 V kHz kHz μA 3 SC410 Electrical Characteristics (continued) Parameter Timing On-Time Minimum On-Time(1) Minimum Off-Time(1) Continuous Mode VIN=15V, VOUT=3V, RTON= 200kΩ 0.9 1 100 320 1.1 μs ns ns Conditions Min Typ Max Units Soft start Soft start Time(1) Delay from PWM Switching to Output Regulation 850 μs Current Sense Zero-Crossing Detector Threshold LX - PGND -10 0 +10 mV Power Good Upper Limit, VFB > internal 750mV reference Power Good Threshold Lower Limit, VFB < internal 750mV reference PGOOD Delay Time(1) Noise Immunity Delay Time (1) Leakage Power Good On-Resistance 10 Between VOUT at 90% of its regulation value and the PGOOD signal transitioning to high 90 1 5 1 ms μs μA Ω 120 %VREF Fault Protection Output Under-Voltage Fault Output Over-Voltage Fault Smart PowerSave Protection Threshold OV, UV Fault Noise Immunity Delay (1) Over-Temperature Shutdown (1) OT Latched FB with Respect to REF, 8 Consecutive Switching Cycles FB with Respect to REF FB with Respect to REF 75 120 110 5 145 %VREF %VREF %VREF μs °C Enable Logic PWM Output Enabled(1) LDO Output Enabled EN Input Bias Current VEN = 5V -10 1.5 0.8 10 V V μA 4 SC410 Electrical Characteristics (continued) Parameter Gate Drivers BST Switch On resistance 25 Ω Conditions Min Typ Max Units Internal Power MOSFETs Current Limit(2) LX Leakage Current Inductor Valley Current Limit, VLDO=5V VIN=24V, LX=0V, High Side High Side Switch Resistance Low Side Non-overlap time (1) 110 15 ns 2.4 3.2 1 215 mΩ A 10 μA Linear Regulator ( The LDO is shorted to the bias node, internally) LDO Accuracy Short circuit protection, VIN = 12V, VLDO 80% of final VLDO value LDO Drop Out Voltage From VIN to VLDO, ILDO = 100mA -4 35 mA 100 1.2 V 4 %VLDO LDO Current Limit Note: (1) Typical value from EVB, not ATE tested. (2) The minimum inductor valley current limit of 2.4V gives an average output current limit of 3A assuming 1.2A inductor ripple current. 5 SC410 Detailed Application Circuit-1 VLDO RPGOOD U1 CBST 1 2 3 4 5 VIN S C 410 BST VIN LX PGND PGOOD LDO AGND TON EN FB VIN +5 to +24VDC CIN(1) 10µF 10 9 8 7 6 0.1μF CLDO1 0.1μF CLDO2 1μF REN 10nF RTON 90.9k Ω L1 2.2μ H RL 12.4k Ω CC_1 NP CL 10nF CC 47pF CTOP NP RTOP 34k Ω RBOT 10k Ω R8 0Ω Position as close to IC as possible COUT1(1) 22µF COUT2(1) 22µF COUT3(1) 22µF VOUT 3A max. Note: (1) Ceramic capacitors 6 SC410 Detailed Application Circuit-2 VLDO RPGOOD U1 CBST 1 2 3 4 5 VIN S C 410 BST VIN LX PGND PGOOD LDO AGND TON EN FB VIN +5 to +24VDC CIN( 1) 10µF 10 9 8 7 6 0.1μF CLDO1 0.1μ F CLDO2 1μF REN 10nF RTON 90.9kΩ L1 2.2μH CTOP NP RTOP 34k Ω COUT2( 2) VOUT 3A max. RBOT 10kΩ R8 0Ω Position as close to IC as possible Notes: (1) Ceramic capacitor ( 2) Capacitor must provide ESR for user application 7 SC410 Typical Characteristics Characteristics are based on a circuit with VIN = 12V, L = 2.2μH (DCR = 35mΩ), COUT = 66μF, VOUT = 3.3V, VLDO = 5V, RTON = 90.9kΩ. Efficiency — Power Loss 90 VIN = 12V 80 VIN = 8V Efficiency VIN = 24V VIN = 18V 70 PLOSS 1.0 VIN = 8V VIN = 12V 0.0 0.1 IOUT (ADC) 1.0 2.0 3.0 4.0 Load Regulation 1.8 1.2 0.6 PLOSS (W) VIN = 18V VIN = 24V Efficiency (%) VOUT (%) 0 -0.6 -1.2 -1.8 VIN = 12V VIN = 8V VIN = 24V 60 VIN = 18V 50 0.0 10.0 -2.4 0 0.1 IOUT (ADC) 1.0 10.0 Switching Frequency 700 600 500 Switching Ripple 0.20 0.18 VIN = 12V 0.15 Frequency (kHz) VOUT Ripple (V) 0.13 0.10 0.08 0.05 0.03 0.00 0.0 0.5 1.0 VIN = 12V 1.5 IOUT (ADC) 2.0 2.5 3.0 VIN = 24V VIN = 8V VIN = 18V 400 300 200 100 0 0.0 VIN = 8V VIN = 24V VIN = 18V 0.5 1.0 1.5 IOUT (ADC) 2.0 2.5 3.0 On-Time vs. VIN 1.4 1.2 1 Line Regulation 1.8 1.2 0.6 0 -0.6 -1.2 -1.8 -2.4 6 9 12 15 18 Input Voltage (V) 21 24 IOUT = 1.5A IOUT = 1.5A On-Time (ms) 0.6 0.4 0.2 0 6 9 12 15 18 Input Voltage (V) 21 24 VOUT (%) 0.8 8 SC410 Typical Characteristics (continued) Characteristics are based on a circuit with VIN = 12V, L = 2.2μH (DCR = 35mΩ), COUT = 66μF, VOUT = 3.3V, VLDO = 5V, RTON = 90.9kΩ. Transient Response IOUT = 3A to 0A (20mV/div) Power Save IOUT = 0A (50mV/div) (10V/div) (10V/div) Time (100μs/div) Time (10μs/div) CCM IOUT = 1.5A (5V/div) Shutdown IOUT = 1.5A (5V/div) (20mV/div) (1V/div) (10V/div) (10V/div) Time (2μs/div) Time (40μs/div) Start-up IOUT = 0A (5V/div) (5V/div) Start-up IOUT = 1.5A (5V/div) (2V/div) (1V/div) (200mV/div) (10V/div) Time (400μs/div) (10V/div) Time (400μs/div) 9 SC410 Pin Descriptions Pin # 1 2 3 4 5 Pin Name BST VIN LX PGND PGOOD Pin Function Bootstrap pin — A capacitor is connected between BST to LX to develop the floating voltage for the high-side gate drive. Power input supply voltage Switching (phase) node Power ground Open-drain power good indicator — High impedance indicates power is good. An external pull-up resistor is required. Feedback input for switching regulator — Connect to an external resistor divider from the output to program the output voltage. Enable input for switching regulator —Pull EN high to enable the part with ultrasonic power save mode enabled. Connect to AGND to disable the switching regulator. A voltage divider can be added between VIN and AGND pins for input UVLO functionality. On-time set input — Set the on-time by connecting a series resistor to AGND. 6 FB 7 EN 8 TON 9 AGND Analog Ground. Output for the internal LDO and internal connection to the bias node — Decoupling capacitors are required to AGND and PGND regardless of the use of the LDO for external loads. Thermal pad for heatsinking purposes. (Not connected internally) Connect to AGND plane using multiple vias. 10 LDO PAD 10 SC410 Block Diagram PGOOD 5 FB EN 7 LDO BST 1 AGND 9 Reference Control and Status 2 VIN Soft Start LX 3 FB 6 FB Comparator On-Time Generator Gate Drive Control LDO LX TON 8 Zero Cross Detector RILIM VIN Valley Current Limit ILIM 5V LDO LDO 4 PGND 10 LDO 11 SC410 Applications Information Synchronous Buck Converter The SC410 is a step down synchronous buck DC-DC regulator. The device is capable of 3A operation at very high efficiency in a tiny 3 x 3-10 pin package. The programmable operating frequency range of 200kHz – 1MHz enables the user to optimize the design for minimum board space and optimum efficiency. The buck regulator employs pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response thereby lowering the size of the power components used in the system. output voltage value and VIN. The period is proportional to output voltage and inversely proportional to input voltage. The value of the output voltage is obtained by filtering the voltage seen on the LX pin. With this adaptive on-time design, the device automatically anticipates the on-time needed to regulate VOUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: • • • • • Input Voltage Range The SC410 can operate with a wide input voltage ranging from 5.5V to 24V. The internal LDO generates a fixed 5V output that provides power for the bias of the SC410. The LDO can also provide additional power to an external load. Psuedo-fixed Frequency Adaptive On-time Control The PWM control method used by the SC410 is pseudofixed frequency, adaptive on-time, as shown in Figure 1. The ripple voltage generated at the output capacitor ESR is divided down by the feedback resistor network and used as a PWM ramp signal. The ripple seen at the FB pin is used to trigger the on-time of the controller. VIN TON VLX CIN Predictable operating frequency during CCM compared to other variable frequency methods. Reduced component count by eliminating the error amplifier and compensation components. Reduced component count by removing the need to sense and control inductor current. Fast transient response — the response time is controlled by a fast comparator instead of a typically slow error amplifier. Reduced output capacitance due to fast transient response One-Shot Timer and Operating Frequency The one-shot timer operates as shown in Figure 2. The feedback comparator output goes high when VFB is less than the internal 750mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator, timing capacitor, and a low pass filter (LPF) which regenerates VOUT from LX. One comparator input is connected to the filtered LX voltage, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to VIN. When the capacitor voltage reaches VOUT, the on-time is completed and the high-side MOSFET turns off. Q1 VLX VFB FB Threshold VOUT L Q2 ESR FB + COUT Figure 1 — PWM Control Method, VOUT Ripple The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the feedback ripple, the device sends a single on-time pulse to the high-side MOSFET. The pulse period is determined by the 12 SC410 Applications Information (continued) FB Ref. + PWM S R Q Hi-side and Lo-side Gate Drivers VIN Q1 LPF VOUT VLX Q2 L ESR COUT RTON Time = K x (VOUT/VIN) + FB VLX_FILTER VOUT Voltage Selection The switcher output voltage is regulated by comparing VOUT as seen through a resistor divider at the FB pin to the internal 750mV reference voltage, see Figure 3. VOUT To FB pin R2 VLX_FILTER VIN One-Shot Timer R1 Figure 2 — On-Time Generation This method automatically produces an on-time that is proportional to VOUT and inversely proportional to VIN. Under steady-state operating conditions in continuous conduction mode, the switching frequency can be determined from the on-time by the following equation. Figure 3 — Output Voltage Selection Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC output voltage VOUT is offset by the output ripple according to the following equation. VOUT 0.75 1 R1 R2 VRIPPLE 2 fSW VOUT t ON VIN The SC410 uses an external resistor to set the on-time which indirectly sets the frequency. The on-time can be programmed to provide operating frequencies from 200kHz to 1MHz using a resistor between the TON pin and ground. The resistor value is selected by the following equation. RTON 1 25pF fSW 400 VIN VOUT Enable Input The EN input is used to enable or disable the switching regulator. When EN is low (grounded), the switching regulator and LDO are disabled and the SC410 is in its lowest power state. When disabled, the output power switches are tri-stated. When EN is higher than 0.8V, the internal LDO will be activated. The switching regulator remains off until the voltage at the EN pin exceeds 1.5V. The EN pin can be used for implementing UVLO for the input voltage by configuring a voltage divider from VIN to EN to PGND. The maximum RTON value allowed is shown by the following equation. RTON _ MAX VIN _ MIN 10 1.5 A Continuous Mode Operation Immediately after the on-time, the DL (the drive signal for the low side FET) output drives high to turn on the low-side MOSFET. DL has a minimum high time of ~320ns, after which DL continues to stay high until one of the following occurs: The SC410 operates in CCM (Continuous Conduction Mode) at larger load currents when the load is greater than or equal to half of the inductor ripple current (Figure 4). In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid crossconduction. This mode of operation results in uniform frequency. • • VFB falls below the 750mV reference The zero cross detector senses that the voltage on the LX node is below ground. PSAVE is activated 8 periods after the zero cross is detected. 13 SC410 Applications Information (continued) FB Ripple Voltage (VFB) FB threshold (750mV) FB Ripple Voltage (VFB) Minimum fSW ~ 25kHz FB threshold (750mV) (0A) Inductor Current DC Load Current Inductor Current On-time (TON) DH DH on-time is triggered when VFB reaches the FB Threshold. DH On-time (TON) DH On-Time is triggered when VFB reaches the FB Threshold 40μsec time-out DL DL After the 40μsec time-out, DL drives high if VFB has not reached the FB threshold. DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. Figure 4 — Continuous Mode Operation Figure 5 — Ultrasonic Power Save Operation Ultrasonic Power Save Operation The SC410 provides ultrasonic power save operation at light loads, with the minimum operating frequency fixed at 22kHz. This is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40μs, DL drives high to turn the low-side MOSFET on. This draws current from VOUT through the inductor, forcing both VOUT and VFB to fall. When VFB drops to the 750mV threshold, the next DH on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. Because the on-times are forced to occur at intervals no greater than 40μs, the frequency will not fall below ~22kHz. Figure 5 shows ultrasonic power save operation. Smart Power Save Protection Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with power save enabled, this can force VOUT to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. Smart power save prevents this condition. When the FB voltage exceeds 10% above nominal (exceeds 825mV), the device immediately disables power-save, and DL drives high to turn on the low-side MOSFET. This draws current from VOUT through the inductor and causes VOUT to fall. When VFB drops back to the 750mV trip point, a normal TON switching cycle begins. This method prevents a hard OVP shutdown and also cycles energy from VOUT back to VIN. Figure 6 shows typical waveforms for the smart power save feature. 14 SC410 Applications Information (continued) VOUT drifts up to due to leakage current flowing into COUT Smart Power Save Threshold (825mV) FB threshold DH and DL off High-side Drive (DH) Single DH on-time pulse after DL turn-off Low-side Drive (DL) DL turns on when Smart PSAVE threshold is reached DL turns off when FB threshold is reached Normal DL pulse after DH on-time pulse VOUT discharges via inductor and low-side MOSFET Normal VOUT ripple In the SC410, the valley current limit is set to 3A. This results in a peak inductor current of 3A plus the peak-to-peak ripple current. In this situation, the average (load) current through the inductor is 3A plus one-half the peak-to-peak ripple current. The internal 10μA current source is temperature compensated at 2500ppm in order to provide tracking with the RDSON. Peak Inductor Current The peak current through the inductor and switching FETs must be less than 5A. The only way to meet this requirement is to select the switching frequency and inductor value so that the peak inductor current is less than or equal to 5A when the trough of the inductor current is 3A. Figure 6 — Smart Power Save Current Limit Protection Programmable current limiting is accomplished by using the RDSON of the lower MOSFET for current sensing. The current limit is set by an internal resistor RILIM. The resistor connects from an ILIM node to the LX node which is also the drain of the low-side MOSFET. When the low-side MOSFET is on, an internal ~10μA current flows from the ILIM Node and through the RILIM resistor, creating a voltage drop across the resistor. While the low-side MOSFET is on, the inductor current flows through it and creates a voltage across the RDSON. The voltage across the MOSFET is negative with respect to ground. If this MOSFET voltage drop exceeds the voltage across RILIM, the voltage at the ILIM node will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on and will not allow another high-side on-time, until the current in the low-side MOSFET reduces enough to bring the ILIM voltage back up to zero. This method regulates the inductor valley current at the level shown by ILIM in Figure 7. Inductor Current IPEAK ILOAD ILIM Soft start of PWM Regulator Soft start is achieved in the PWM regulator by using an internal voltage ramp as the reference for the FB comparator. The voltage ramp is generated using an internal charge pump which drives the reference from zero to 750mV in ~1.8mV increments, using an internal ~500kHz oscillator. When the ramp voltage reaches 750mV, the ramp is ignored and the FB comparator switches over to a fixed 750mV threshold. During soft start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft start profile for a wide range of applications. Typical soft start ramp time is 850μs. During soft start the regulator turns off the low-side MOSFET on any cycle if the inductor current falls to zero. This prevents negative inductor current, allowing the device to start into a pre-biased output. Power Good Output The PGOOD (power good) output is an open-drain output which requires a pull-up resistor. When the output voltage is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns to the nominal voltage. PGOOD is held low during soft start and activated approximately 1ms after VOUT reaches regulation. Time Figure 7 — Valley Current Limit 15 SC410 Applications Information (continued) PGOOD will transition low if the VFB pin exceeds +20% of nominal, which is also the over-voltage shutdown threshold (900mV). While the EN pin is above 0.5V, the LDO will be activated. While the VLDO output voltage remains below 4V (80% of the final LDO voltage), the LDO short-cicuit protection is enabled and limits the current to about 35mA. After the VLDO exceeds 4.0V, then the LDO operates in its normal regulation mode where the current is limited to about 100mA. VLDO Final 80% of VLDO Final Voltage regulating with ~100mA current limit Output Over-Voltage Protection OVP (Over-Voltage Protection) becomes active as soon as the device is enabled. The threshold is set at 750mV + 20% (900mV). When VFB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN input is toggled or VIN is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Sort-circuit Protection @ ~35mA Output Under-Voltage Protection When VFB falls to 75% of its nominal voltage (falls to 562.5mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to turn off the MOSFETs. The controller stays off until EN is toggled or VIN is cycled. Figure 8 — LDO Start-Up Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design. Over-Temperature Protection If the temperature rises to 145°C the device will latch off. The device can be activated after the temperature is reduced below 145°C by cycling the EN pin. VLDO UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the power FETs until VLDO rises above 4.0V. An internal POR (Power-On Reset) occurs when VLDO exceeds 4.0V, which resets the fault latch and soft start counter to begin the soft start cycle. The SC410 then begins a soft start cycle. The PWM will shut off if VLDO falls below 3.7V. Internal LDO Regulator The SC410 has an internal regulator that supplies the bias voltage for the PWM controller. This LDO can also supply an additional external current for an external load through the LDO pin. • • • • Nominal output voltage (VOUT ) Static or DC output tolerance Transient response Maximum load current (IOUT ) When activated, the LDO checks the status of the following signals to ensure proper operation can be maintained. 1. EN pin 2. VLDO output voltage 3. VIN input voltage The two values of load current to evaluate are continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. 16 SC410 Applications Information (continued) The following values are used in this design example. • • • • VIN = 12V + 10% VOUT = 3.3V + 4% fSW = 500kHz Load = 3A maximum save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 2A then power-save operation will typically start for loads less than 1A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. During the DH on-time, voltage across the inductor is (VIN - VOUT ). The equation for determining inductance is shown next. L ( VIN VOUT ) t ON IRIPPLE Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 500kHz which results from using components selected for optimum size and cost. A resistor (RTON) is used to program the on-time (indirectly setting the frequency) using the following equation. RTON 1 25pF fSW 400 VIN VOUT Example In this example, the inductor ripple current is set equal to 75% of the maximum load current. Therefore ripple current will be 75% x 3A or 2.25A. To find the minimum inductance needed, use the VIN and TON values that correspond to VINMAX. L (13.2V 3.3 V ) 501ns 2.25 A 2.204 H To select RTON, use the maximum value for VIN, and for TON use the value associated with maximum VIN. t ON V OUT V INMAX f SW A s tandard value of 2.2μH is selected. This gives a maximum IRIPPLE of 2.53A. The peak ripple can be calculated by the equation, below where LTOL is assumed to be an inductor tolerance of 20%. IRIPPLE_PEAK = IRIPPLE_MAX x (1 + LTOL) = 2.705 Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. ILSAT_MIN = IRIPPLE_PEAK X 0.5 + IOUT = 4.353 The ripple current under minimum VIN conditions is also checked using the following equations. tON = 500 ns at 13.2VIN, 3.3VOUT, 500kHz Substituting for RTON results in the following solution. RTON = 78.5kΩ, use RTON = 78.7kΩ Now, tON = 501ns given that RTON = 78.7kΩ. Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for powersave operation. The switching will typically enter power- t ON _ VINMIN IRIPPLE ( VIN 25pF R TON VOUT VINMIN VOUT ) t ON L 10ns 611ns IRIPPLE _ VINMIN (10.8 V 3.3 V ) 612ns 2.2 H 2.08 A 17 SC410 Applications Information (continued) Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 750mV reference tolerance is 1%. Assuming a 1% tolerance from the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 132mV for a 3.3V output. The maximum ripple current of 2.7A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 3A + 1/2 x 2.7A = 4.353A Rate of change of Load Current dlLOAD dt ESRMAX 2 VRIPPLE IRIPPLEMAX 132mV 2.705 A ESRMAX = 48.8 mΩ The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1μs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. L 1 L TOL COUTMIN IOUT VPEAK 2 IMAX = maximum load release = 3A L 1 L TOL COUT ILPK ILPK VOUT IMAX d lLOAD dt 2 VPK VOUT Example dlLOAD dt 2A 1s 1 IRIPPLE _ PEAK 2 VOUT 2 2 This causes the output current to move from 3A to 0A in 4.8μs, giving the minimum output capacitance requirement shown in the following equation. 2.2 H 1 20 % COUT 4.353 A 4.353 A 3 A 1s 3 .3 V 2A 2 3.432 V 3.3 V Assuming a peak voltage VPEAK of 1.150 (132mV rise upon load release), and a 6A load release, the required capacitance is shown by the next equation. 2.2 H 1 20% 3 A COUTMIN COUTMIN = 56μF 1 2.705 A 2 3 .3 V 2 2 Note that COUT is much smaller in this example, 33μF compared to 56μF based on a worst-case load release. To meet the two design criteria of minimum 56μF, select three capacitors rated at 22μF and 15mΩ ESR. 3.432V 2 18 SC410 Applications Information (continued) Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Doublepulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout. An alternate method to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 9. This capacitor should be left unpopulated unless it can be confirmed that doublepulsing exists. Adding the CTOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be provided for this capacitor. CTOP One simple method of solving this problem is to add trace resistance in the high current output path. A side effect of adding trace resistance is a decrease in load regulation. ESR Requirements A minimum ESR is required for two reasons. The first reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications, the total output ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the following equation. 3 C OUT ESR MIN 2 f sw Using Ceramic Output Capacitors When applications use ceramic output capacitors, the ESR is normally too small to meet the previously stated ESR criteria. In these applications it is necessary to add a small signal injection network as shown in Figure 10. In this network RL and CL filter the LX switching waveform to generate an in-phase ripple voltage comparable to the ripple seen on higher ESR capacitors. CC is a coupling capacitor used to AC couple the generated ripple onto the FB pin. VOUT R1 R2 To FB pin Figure 9 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. 19 SC410 Applications Information (continued) Output Voltage Dropout L Highside RL CC FB pin CL R1 COUT R2 Lowside The output voltage adjustable range for continuous-conduction operation is limited by the fixed 320ns (typical) minimum off-time. When working with low input voltages, the duty-factor limit must be calculated using worstcase values for on and off times. The duty-factor limitation is shown by the next equation. DUTY t ON(MIN) t ON(MIN) t OFF(MAX ) Figure 10 — Signal Injection Circuit The values of RL, CL, and CC are dependent on the conditions of the specific application such as VIN, VOUT, fSW and IOUT. Select a value for CL, like 10nF. Using CL, calculate RL as shown in the following equation: RL L DCR The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy — VOUT Controller Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 750mV, +1%. The on-time pulse from the SC410 in the design example is calculated to give a pseudo-fixed frequency of 500kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors may result in up to an additional 1% error. If tighter DC accuracy is required, resistors with lower tolerances should be used. CL Where L is the inductor value and DCR is the resistance of the inductor. The value for CC can be between CC_MIN and CC_MAX. CC _ MIN t ON REQ T REQ CC _ MAX Where T = 1/fSW and REQ is represented by the following equation. REQ RBOTTOM RTOP RBOTTOM RTOP It is beneficial to use the smallest value of CC that provides stability and enough voltage ripple at feedback. Larger values of CC may negatively affect the load regulation performance. 20 SC410 Applications Information (continued) The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the power FET switching. As VIN i ncreases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to fall slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essentially constant for a given VOUT and VIN combination, to offset the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. 21 SC410 Applications Information (continued) PCB Layout Guidelines The optimum layout for the SC410 is shown in Figure 11. This layout shows an integrated FET buck regulator with a maximum current of 3A. The total PCB area is approximately 19.1mm x 11.3mm. Critical Layout Guidelines The following critical layout guidelines must be followed to ensure proper performance of the device. PGND Plane PGND requires its own copper plane with no other signal traces routed on it. Copper planes, multiple vias, and wide traces are needed to connect PGND to input capacitors, output capacitors, and the PGND pins on the IC. The PGND copper area between the input capacitors, output capacitors, and PGND pins must be as small as and as compact as possible to reduce the area of the PCB that is exposed to noise due to current flow on this node. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the IC as possible. • • • • • • • • • • • IC Decoupling capacitors PGND plane AGND island FB and other analog control signals BST and LX Capacitors and Current Loops • IC Decoupling Capacitors A 0.1 μF capacitor must be located as close as possible to the IC and directly connected to pins 10 (LDO) and 9 (AGND). All other decoupling capacitors must be located as close as possible to the IC. AGND Island AGND should have its own island of copper with no other signal traces routed on this layer that connects the AGND pins and pad of the IC to the analog control components. All of the components for the analog control circuitry should be located so that the connections • • LX connection using a Via SC410 FB node VESR node PGND Figure 11 — PCB Layout 22 SC410 Applications Information (continued) • to AGND are done by wide copper traces or vias down to AGND. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the IC as possible. FB and Other Analog Control Signals The connection from the V OUT p ower to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. The traces between VOUT and the analog control circuitry (AGND, and FB pins) must be as short as possible. The traces must also be routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. The TON node must be as short as possible to ensure the best accuracy for the on time. The feedback components for the switcher need to be as close to the FB pin of the IC as possible to reduce the possibility of noise corrupting these analog signals. • • BST and LX LX and BST are very noisy nodes and must be carefully routed to minimized the PCB area that is exposed to these signals. The connections for the boost capacitor between the IC and LX must be short and directly connected to the LX (pin 3). The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the possibility of LX noise corrupting other signals. • • • • • Capacitors and Current Loops The current loops between the input capacitors, the IC, the inductor, and the output capacitors must be as close as possible to each other to reduce IR drop across copper planes and traces. All bypass and output capacitors must be connected as close as possible to their respective pin on the IC. • • 23 SC410 Outline Drawing — MLPD-10 3x3 A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .031 .039 .000 .002 (.008) .007 .009 .011 .114 .118 .122 .074 .079 .083 .114 .118 .122 .042 .048 .052 .020 BSC .012 .016 .020 10 .003 .004 0.80 1.00 0.00 0.05 (0.20) 0.18 0.23 0.30 2.90 3.00 3.10 1.87 2.02 2.12 2.90 3.00 3.10 1.06 1.21 1.31 0.50 BSC 0.30 0.40 0.50 10 0.08 0.10 E PIN 1 INDICATOR (LASER MARK) A aaa C SEATING PLANE C A1 A2 D1 1 2 LxN E/2 E1 N e bxN bbb CAB D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS. 24 SC410 Land Pattern — MLPD-10 3x3 K DIM (C) H G Y X P C G H K P X Y Z DIMENSIONS INCHES MILLIMETERS (.114) .083 .055 .087 .020 .012 .031 .146 (2.90) 2.10 1.40 2.20 0.50 0.30 0.80 3.70 Z NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 25 SC410 © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. 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