SC415MLTRT

SC415 Dual Synchronous Buck Controller POWER MANAGEMENT Features VIN Range 3-25V Outputs Adjustable from 0.75 to 5.25V, or Preset Output Voltages: VOUT1 = 1.8 or 1.5V VOUT2 = 1.25 or 1.05V Low Shutdown Power Constant On-Time for Fast Dynamic Response Adjustable Switching Frequency Separated Frequencies for Minimal Switching Interaction: VOUT1 = up to 600kHz VOUT2 = up to 720kHz Power Save or Continuous Operation at Light Load Adjustable Soft-start Rates for Each Output Soft-Shutdown for Each Output Over-Voltage and Under-Voltage Fault Protection Cycle-by-Cycle Valley Current Limit DC Current Sense Using Low-Side RDSON Sensing, or RSENSE in Source of Low-Side MOSFET for Greater Accuracy Separate Power Good Outputs Separate Enable/Power Save Inputs 3.1A Non-Overlapping Gate Drive SmartDriveTM for High-Side MOSFET MLP 4x4 24 Pin Package Industrial Temperature Range Description The SC415 is a versatile, constant on-time, pseudo fixedfrequency, dual synchronous buck PWM controller intended for notebook computers and other battery operated portable devices. The SC415 contains all the features needed to provide cost-effective control of two independent switchmode power supplies. The two DC outputs are adjustable from 0.75V to 5.25V. Additional features for each output include cycle-bycycle current limit, voltage soft-start, under-voltage and over-voltage protection, programmable over-current protection, soft shutdown, selectable power save and non-overlapping gate drive. The SC415 provides two enable/power save inputs, two soft-start inputs, two power good outputs and an on-time adjust input. The constant on-time topology provides fast dynamic response. The excellent transient response means that SC415 based solutions require less output capacitance than competing fixed-frequency converters. Switching frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency moves to counter the change in output voltage. After the transient event, the controller frequency returns to steady state operation. At light loads with power save enabled, the SC415 reduces switching frequency for improved efficiency. • • • • Applications Notebook and Sub-Notebook Graphics Voltage Controllers Tablet PCs Embedded Applications July 23, 2008 © 2008 Semtech Corporation 1 SC415 Typical Application Circuit VIN PGD1 Q1 PGD2 Q3 VIN CIN1 CIN2 24 23 22 21 20 19 PGD1 PGD2 DH1 ILIM1 ILIM2 DH2 VOUT1 L1 D1 100NF RLIM1 RLIM2 PAD LX2 BST2 VDD2 25 18 17 16 VOUT2 100NF D2 L2 1 +5V + COUT1 Q2 2 3 4 5 LX1 BST1 VDD1 DL1 EN1 +5V + Q4 COUT2 SC415 VOUT1 VOUT2 TON RTN DL2 EN2 SS2 15 14 1UF 13 1UF 10NF EN1 VOUT1 6 SS1 FB1 FB2 10NF EN2 VOUT2 10 11 1NF 12 RTON VIN 7 8 9 2 SC415 Pin Configuration PGD1 PGD2 ILIM1 ILIM2 DH1 DH2 Ordering Information Device SC415MLTRT(1) SC415EVB Package MLPQ-24 4X4 Evaluation Board 24 LX1 BST1 VDD1 1 TOP VIEW 19 18 LX2 BST2 VDD2 Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. SC415 DL1 EN1 SS1 6 7 VOUT1 RTN TON FB2 FB1 DL2 GND (PAD) 13 12 VOUT2 EN2 SS2 MLPQ24: 4x4 24 LEAD Marking Information SC415 yyww xxxxx xxxxx nnnn = Part Number (example: SC415 yyww = Date Code (example: 0652) xxxxx = Semtech Lot No. (example: 09010 xxxxx 01-10) 3 SC415 Absolute Maximum Ratings DHx, BSTx, GND (DC) ……………………………… -03 to +30V DHx, BSTx to GND (transient - 100nsec max) ………… -2.0 to +33V LXx, TON to GND (DC) ……………………………… -0.3 to +25V LXx, TON to GND (transient - 100nsec max) ………… -2.0 to +28V BST1 to LX1, BST2 to LX2 (DC) ……………………… -0.3 to +6.0V BST1 to LX1, BST2 to LX2 (transient - 100nsec max) … 0.3 to +7.5V DLx to GND (DC) ……………………………………-0.3 to +6.0V GND to RTN ……………………………………… -0.3 to +0.3V VDDx to RTN ……………………………………… -0.3 to +6.0V ENx, FBx, ILIMx, PGDx, SSx, VOUTx to RTN…… -0.3 to VDDx +0.3V Thermal Information Junction to Ambient(1) ……………………………… 29°C/W Storage Temperature Range ……………… -60 to +150°C Operating Junction Temperature Range … -40 to +125°C Peak IR Reflow Temperature (10s to 30s) …….……… 260°C ESD Protection Level(2) ………………………………… 2kV Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Test Conditions: VIN = 15V, VOUT = 1.5V, TA = 25 oC, 0.1% resistor dividers; RTON = 1Meg; VDD1/2 = 5.0V; GND connects to PAD pin. 25°C Parameter Input Supplies VIN Input Voltage VDDx Input Voltage VDD1 + VDD2 Shutdown Current VDD1 + VDD2 Operating Current EN1, EN2 = 0V EN1, EN2 = 5V (Powersave Mode) FB1, FB2 > REF 3.0 4.5 7 800 25 5.5 -40° to 85°C Max Min Max Units Conditions Min Typ V V 10 1200 μA μA Regulation FB1, FB2 On-Time Threshold VOUTx Output Voltage Range 0 to 85°C -40 to 85°C External Resistors FB1 = 5V; 0 to 85°C FB1 = 5V; -40 to 85°C VOUT1 On-Time Threshold FB1 = RTN; 0 to 85°C FB1 = RTN; -40 to 85°C 1.5 1.5 1.4812 1.4737 1.5188 1.5263 V 1.8 0.75 0.7425 0.7388 0.75 1.775 1.773 0.7575 0.7612 5.25 1.8225 1.8315 V V V 4 SC415 Electrical Characteristics (continued) 25°C Parameter Regulation (Continued) FB1 = 5V; 0 to 85°C FB1 = 5V; -40 to 85°C VOUT2 On-Time Threshold FB1 = RTN; 0 to 85°C FB1 = RTN; -40 to 85°C VOUTx Line Regulation Error VOUTx Load Regulation Error 1.05 1.05 0.04 0.3 1.0368 1.0316 1.0631 1.0684 V %/V % 1.25 1.25 1.2343 1.2281 1.2656 1.2718 V -40° to 85°C Max Min Max Units Conditions Min Typ Timing VOUTx On-Time(1) VOUTx Set to 1.5V VOUT1; RTON = 1Meg VOUT2; RTON = 1Meg VOUT1; RTON = 499K VOUT2; RTON = 499K DH1, DH2 DL1, DL2 400 330 200 167 50 330 320 260 480 400 nsec Minimum On-Time Minimum Off-Time nsec nsec Soft-Start/Shutdown Soft-Start SSx Current Source Soft-Start Ramp Time SSx Shutdown Discharge Resistance VOUTx Shutdown Discharge Resistance CSSx = 4.7nF ENx = RTN, VOUTx < 300mV ENx = RTN, VOUTx < 300mV 5 1500 16 3.5 6.5 μA μsec Ω 16 Ω Analog Inputs/Outputs VOUT1 Input Resistance VOUT2 Input Resistance FBx Input Bias Current EN1 = VDD1 EN2 = VDD2 120 90 -1 +1 kΩ kΩ μA Current Sense ILIMx Source Current ILIMx Comparator Offset Current Limit (Negative) Zero Crossing Detector Threshold ILIMx - GND LXx - GND LXx - GND 80 0 10 9 -10 60 -7 11 +10 100 +7 μA mV mV mV Power Good PGDx Threshold PGDx Threshold Delay Time (2) 1% Hysteresis Typical, with Respect to Regulation Point -12% 5 -9% -15% μsec 5 SC415 Electrical Characteristics (continued) 25°C Parameter PGDx Leakage -40° to 85°C Max Min Max 1 Conditions Min Typ Units μA Fault Protection VDD1 Under-Voltage Lockout VOUTx Under-Voltage Fault VOUTx Under-Voltage Fault Delay (2) VOUTx Over-Voltage Fault VOUTx Over-Voltage Fault Delay (2) Thermal Shutdown (2) Latching, >10°C Hysteresis VDD1 Falling Edge (typical hysteresis 100mV) VOUTx Falling Edge 4.0 -30 8 20 5 160 +17 +23 3.7 -35 4.2 -25 V % clks % μsec °C Inputs/Outputs EN1, EN2 Input Low Voltage ENx Input Forced Continuous Mode Operation ENx Input High Voltage VOUTx Disabled ENx = Open VOUTx Enabled, Power Save Enabled R Pull Up to VDDx ENx Input Resistance R Pull Down to RTN FBx Input Low Voltage FBx Input High Voltage Power Good Output Low Voltage RPGDx = 10kΩ to VDDx 1 0.3 VDDx -0.7 0.4 MΩ V V V 1.5 2.0 1.2 V V 3.1 V MΩ Gate Drivers Shoot-Thru Protection Delay(2) DLx Pull-Down Resistance DLx Sink Current (2) DHx or DLx Rising DL Low VDLx = 2.5V DLx High VDLx = 2.5V DHx Low, BSTx - LXx = 5V DHx High, BSTx - LXx = 5V VDHx = 2.5V 30 0.8 3.1 2 1.3 2 4 4 1.6 nsec Ω A Ω A Ω DLx Pull-Up Resistance DLx Source Current (2) DHx Pull-Down Resistance DHx Pull-Up Resistance(3) DHx Sink/Source Current (2) 2 1.3 4 Ω A Notes: 1) RTON = 1Meg. 2) Guaranteed by design. 3) Semtech’s SmartDrive™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typical) until LX = 1.5V (typical). At this point, an additional pull-up device is activated, reducing the resistance to 2Ω (typical). This negates the need for an external gate or boost resistor. 6 SC415 Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 Pin Name LX1 BST1 VDD1 DL1 EN1 SS1 VOUT1 FB1 RTN TON Pin Function Switching (phase) node for VOUT1 Boost capacitor connection for VOUT1 high-side gate drive 5V supply input for VOUT1 analog circuits and gate drive outputs. Under-voltage lockout for the 5V supply is sensed on VDD1 only. Gate drive output for the VOUT1 low-side external MOSFET Enable input for VOUT1. Ground to disable the VOUT1 switcher. Leave open to enable VOUT1 switcher with power-save disabled. Connect to VDD1 to enable VOUT1 in power-save mode. Soft-start input for VOUT1. For independent start-up, connect a capacitor to RTN. Connect to the output capacitor of VOUT1. Used for DH1 On-Time generation, and for VOUT1 regulation when FB1 is connected to VDD1 or RTN. Feedback input for VOUT1. Connect to an external resistor divider to adjust VOUT1, or connect to RTN or VDD1 to select internal feedback resistors via the VOUT1 pin. Analog return (ground) for both VOUT1 and VOUT2 On-time adjust input. Connect a resistor from VIN to TON to program the on-time. The on-time one-shot for VOUT1 is internally set at 20% greater than for VOUT2, to prevent frequency interaction between the two converters. Feedback input for VOUT2. Connect to an external resistor divider to adjust VOUT2, or connect to RTN or VDD2 to select internal feedback resistors via the VOUT2 pin. Connect to the output capacitor of VOUT2. Used for side 2 On-Time generation, and for VOUT2 regulation when FB2 is connected to VDD2 or RTN. Soft-start input for VOUT1. For independent start-up, connect a capacitor to RTN. Enable input for VOUT2. Ground to disable the VOUT2 switcher. Leave open to enable VOUT2 switcher with power-save disabled. Connect to VDD2 to enable VOUT2 in power-save mode. Gate drive output for the VOUT2 low-side external MOSFET 5V supply input for VOUT2 analog circuits and gate drive outputs. VDD2 must connect to the same supply as VDD1. Boost capacitor connection for VOUT2 high-side gate drive Switching (phase) node for VOUT2 Gate drive output for the VOUT2 high-side external MOSFET Current limit input for VOUT2. Connect through a resistor to the drain of the VOUT2 low-side MOSFET. Open-drain Power Good output for VOUT2 Open-drain Power Good output for VOUT1 Current limit input for VOUT1. Connect through a resistor to the drain of the VOUT1 low-side MOSFET. Gate drive output for the VOUT1 high-side external MOSFET Power ground for VOUT1 and VOUT2 gate drivers, and thermal pad for heatsinking 11 12 13 14 15 16 17 18 19 20 21 22 23 24 T FB2 VOUT2 SS2 EN2 DL2 VDD2 BST2 LX2 DH2 ILIM2 PGD2 PGD1 ILIM1 DH1 PAD 7 SC415 Block Diagram VDD1 VDD1 REF FB1 Comparator FB1 Select BST1 VIN FB1 EN1 SS1 VOUT1 DH1 S Q DRV SS1 Control VDD1 TON1 TON1 One-Shot UV- OV Monitor VDD1 Valley ILIM/ ZCD Detect REF LX1 R QB DRV LX1 DL1 PGD1 ILIM1 TON TON Reference VDD2 VDD2 REF FB2 Comparator BST2 DH2 S Q DRV LX2 DL2 DRV VIN FB2 EN2 SS2 VOUT2 FB2 Select SS2 Control TON2 One-Shot UV- OV Monitor TON2 R QB VDD2 PGD2 Valley ILIM/ ZCD Detect ILIM2 LX2 PAD RTN GND SC415 Block Diagram 8 SC415 Applications Information SC415 Synchronous Buck Controller The SC415 is a dual synchronous controller which simplifies the task of designing a dual-output power supply. VIN and +5V Bias Supplies The SC415 requires an external +5V bias supply in addition to the VIN supply. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. Pseudo-Fixed Frequency Constant On-Time PWM Controller The PWM control method for each output is a constant-ontime, pseudo-fixed frequency PWM controller, see Figure 1. The ripple voltage seen across the output capacitor’s ESR provides the PWM ramp signal. The on-time is determined by an internal one-shot whose period is proportional to output voltage and inversely proportional to input voltage. A separate one-shot sets the minimum off-time (typically 330ns). The two converters are designed to operate at different frequencies to minimize interaction. Side2 frequency is set typically 20% higher than Side1. On-Time One-Shot (TON) Each side has an internal on-time one-shot comparator which has two inputs. One input looks at the output voltage via the VOUT pin, while the other input samples the input voltage via the TON pin and converts it to a proportional current. This current charges an internal ontime capacitor. The TON on-time is the time required for this capacitor to charge from zero volts to VOUT, thereby making the on-time directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a fairly constant switching frequency with no clock generator. The nominal frequency is set through an external resistor connected between VIN and the TON pin. To minimize interaction between the two converters, Side2 is set to operate at a slightly higher frequency. The general equations for the side1 and side2 on-times are: TON1 = 3.3 × (RTON+37) × (VOUT/VIN) + 35 TON2 = 2.75 × (RTON+37) × (VOUT/VIN) + 35 (TON2 in nsec, RTON in kΩ) TON VIN LX CIN LX L Q2 ESR VOUT Switch-Mode Operation The switch-mode operation is explained below and is identical for both sides except for the difference in the TON timing. The output voltage is sensed at the FB pin and is compared to the internal 750mV reference. (The output voltage can also be sensed at the VOUT pin which uses an internal resistor divider, see VOUT Voltage Selection.) When the sensed voltage drops below 750mV, this triggers a single TON pulse, which is fed to the DH high-side driver. The DH pulse-width follows TON according to the TON equation, and after that time DH drives low to shut off the high-side MOSFET. After DH drives low, the DL output drives high to energize the low-side MOSFET. Q1 VOUT / FB FB Threshold 0.75V + COUT Figure 1 9 SC415 Applications Information (continued) Once high, DL has a minimum pulse width of typically 330nsec which is the minimum off-time. At the end of the minimum off-time, DL continues to stay high until one of the following occurs: The FB comparator input drops to the 750mV reference, as sensed through the FB pin or the VOUT pin The Zero Cross detector trips, if psave is active The Negative Current Limit detector trips If DL drives low because FB has dropped to 750mV, then another DH on-time is started. This is normal operation at heavy load (fully synchronous operation where either DH or DL is high except during transitions). The Zero Cross detector monitors the voltage across the low-side MOSFET during the DL high time and detects when it reaches zero. If DL drives low because of the Zero Cross detector, and psave is active, then both DH and DL will remain low until FB drops to 750mV, at which point the next DH on-time will begin. If a Zero Cross is detected on eight consecutive cycles, then for each subsequent switching cycle DL will shut off when the Zero Cross detector trips; see the PSAVE Operation section. When this occurs, both DH and DL will stay low until FB drops to 750mV, which will begin the next DH on-time. This is normal operation at light load, (PSAVE Operation, where each cycle consists of a DH pulse, a DL pulse, and dead time with both DH and DL low). The Negative Current Limit detector trips when the drain voltage at the low-side MOSFET reaches +80mV, indicating that a large negative current flows through the inductor from VOUT. When this occurs, DL drives low. Both DH and DL will then stay low until FB drops to 750mV, which will begin the next DH on-time. Tripping Negative Current Limit is rare. To help reduce noise interaction between sides, the rising edge of each DH driver is inhibited momentarily if the other side is switching. For example, if FB2 reaches the 750mV trip point at the same instant that side1 is performing a DH or DL transition (up or down), then side2’s DH driver is held off for roughly 30nsec to allow side1 to finish switching. VOUT Voltage Selection Output voltage is regulated by comparing VOUT as seen through a resistor divider to the internal 750mV reference, see Figure 2. Each output can be adjusted to a voltage between 0.75–5.25V. The output voltage is set by the equation: VOUT = 0.75 × (1 + R1/R2) VOUT R1 to FB R2 + COUT Figure 2 Note: the parallel resistance of R1 and R2 should not be less than 2kΩ. Using a smaller resistance can cause the IC to default to the internal preset output voltages shown on Page 11. There are fixed output voltages accessible through each FB pin. If the FB pin is connected to either RTN or +5V, then the IC will ignore the FB pin and instead regulate the output voltage using the VOUT pin which is connected to internal resistor divider. Note that each FB input operates independently of the other. 10 SC415 Applications Information (continued) The voltages available are shown: FB Internal Voltage Selection FB = RTN 1.5V 1.05V FB = +5V 1.8V 1.25V efficiency improvement at light loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller immediately exits PSAVE. Once PSAVE is exited, it requires 8 switching cycles at light load to reenter PSAVE. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps. When operating in PSAVE mode at light loads, the LX waveform will not have the typical square wave shape seen when operating in continuous conduction mode. Shortly after DL drives low, and both MOSFETs are off, the LX voltage will show ringing. This ringing is caused by the LC circuit formed by the inductor and device capacitance of the MOSFETs and low-side diode. When the lowside MOSFET turns off the inductor current falls toward zero. When it reaches zero, the inductance and MOSFET capacitances will tend to ring freely. This is normal PSAVE operation as shown in Figure 3: VIN Side1 Side2 Enable/Psave Inputs Each converter has a separate Enable pin. Each EN input operates as follows: EN = GND. This turns the converter off. EN = open (float). This turns the converter on with psave mode disabled (continuous conduction mode). In this case, the EN pin will float to approximately 2V due to an internal 1.5Meg/1Meg resistor divider from the +5V supply at VDDx to ground. EN = high (3.1V min). This turns the converter on with psave mode enabled. At light loads, the converter will operate in psave mode. Note that the two EN pins are separate, so each output can be disabled or operated with or without psave independently. If both EN1 and EN2 are grounded, the device is placed into the lowest-power state, drawing typically 10μA from the +5V supply. PSAVE Operation Each output provides automatic PSAVE operation at light loads if the ENx pin is set high. The internal ZeroCross comparator looks for inductor current (via the voltage across the lower MOSFET) to fall to zero on eight consecutive switching cycles. Once observed, the controller enters PSAVE mode and turns off the low-side MOSFET on each subsequent cycle when the current crosses zero. To add hysteresis, the on-time is also increased by 25% when PSAVE mode is active, for that output only; it does not affect the other converter. The CQ1 DH Q1 L VOUT COUT DL Q2 CQ2 DL VIN VOUT LX Typical ringing at LX Figure 3 11 SC415 Applications Information (continued) Smart Psave Protection In some applications, active loads on VOUT can leak current from a higher voltage and thereby cause VOUT to slowly rise and reach the OVP threshold, causing a hard shutdown; the SC415 uses Smart Power Save to prevent this. When the output voltage exceeds 8% above nominal (810mV at FB), that converter then exits PSAVE (if already active), and DL drives high to energize the low-side MOSFET. This will draw current from VOUT via the inductor causing VOUT to fall. When FB drops to the 750mV trip point, a normal TON switching cycle begins. This method cycles energy from VOUT back to VIN and prevents a hard OVP shutdown, and also minimizes operating power by avoiding continuous conduction-mode operation. If a light load is present, DH/DL switching continues for 8 consecutive cycles and then the IC re-turns to PSAVE mode to reduce operating power. Current Limit Current limiting can be accomplished in two ways. The RDSON of the lower MOSFET can be used as a current sensing element, or a sense resistor at the lower MOSFET source can be used if greater accuracy is needed. RDSON sensing is more efficient and less expensive. In both cases, the RILIM resistor sets the over-current threshold. RILIM connects from the ILIM pin to either the lower MOSFET drain (for RDSON sensing) or the high side of the current-sense resistor. RILIM connects to a 10μA current source from the ILIM pin which turns on when the lowside MOSFET turns on (DL is high). If the voltage drop across the sense resistor or low-side MOSFET exceeds the voltage across RILIM, then the voltage at the ILIM pin will be negative or below GND, and current limit will activate. The high-side MOSFET is not allowed to turn on until the voltage drop across the sense resistor or MOSFET falls below the voltage across the RILIM resistor (ILIM pin reaches GND). If the overload at the output continues, the DH pulses will get farther apart, and the output voltage will fall. Eventually the output will fall enough to cause FB to drop to 525mV, activating the under-voltage protection and shutting down the converter. The current sensing scheme actually regulates the inductor valley current, (see Figure 4). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus ½ the peak-to-peak ripple current. INDUCTOR CURRENT I PEAK I LOAD I LIMIT TIME Valley Current Limit Figure 4 The RDSON sensing circuit is shown in Figure 5 with RILIM = R1 and RDSON of Q2. VIN +5V D1 Q1 + C1 BST DH LX ILIM VDD DL PAD C2 L VOUT R1 Q2 D2 + C3 Figure 5 12 SC415 Applications Information (continued) The resistor sensing circuit is shown in Figure 6 with RILIM = R1 and RSENSE = R4 +5V VIN PGD also transitions low if the FB pin exceeds +20% of nominal (900mV), which is also the over-voltage shutdown point. Output Over-Voltage Protection (OVP) In steady state operation, when FB exceeds 20% of nominal (900mV), DL latches high and the low-side MOSFET is turned on. DL stays high and the SMPS stays off until the EN/PSV input is toggled or VDD1 is recycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGD is also held low after an OVP. Output Under-Voltage Protection (UVP) When FB falls 30% below nominal (to 525mV) for eight consecutive clock cycles, the output is shut off ; the DL/ DH drivers are pulled low to tristate the MOSFETs, and the converter stays off until its Enable input is toggled or the VDD1 supply is recycled. The other output does not shut off during UVP. POR and UVLO Under-voltage lockout circuitry (UVLO) inhibits switching and tristates all DH/DL drivers until the +5V supply at VDD1 rises above typically 4.1V. An internal power-on reset (POR) occurs when VDD1 exceeds 4.1V, which resets the fault latches and quickly discharges the soft-start capacitors to prepare the PWM for startup switching. At this time the SC415 will exit UVLO and begin the soft-start cycle. Startup Sequence The startup sequence for each output relies on an external ramp at the SS pin. During startup, the FB comparator uses the SS ramp voltage as the reference until SS reaches 750mV, at which point the FB comparator switches over to the internal fixed 750mV reference. The external ramp is created by connecting a capacitor to the SS pin. Before starting, with EN low, the SS pin is internally tied to GND through 4kΩ. When EN is released, SS is briefly pulled to GND through 16 ohms to discharge residual voltage on the SS capacitor. Then the resistances are removed and a 5μA source current flows out of the SS pin. + D1 C1 Q1 C2 BST DH LX ILIM VDDP DL PAD Q2 L1 Vout D2 + C3 R1 R4 Figure 6 The following over-current equation can be used for both RDSON or resistive sensing. For RDSON sensing, the MOSFET RDSON rating is used for the value of RSENSE. ILOC(Valley) = 10μA × RILIM / RSENSE Power Good Output Each output provides a power good (PGD) output, which is an open-drain output requiring a pull-up resistor. When the output voltage as sensed at FB is -9% from the 750mV reference (682mV), PGD is pulled low. It is held low until the output voltage returns above -9% of nominal; the falling edge of PGD is not latched. PGD is held low during start-up and will not be allowed to transition high until soft-start is completed, when SS reaches 750mV. There is a 5μs delay built into the PGD circuit to prevent false transitions. 13 SC415 Applications Information (continued) The 5μA current into the capacitor creates a linear voltage ramp. The internal FB comparator tracks this SS ramp, which forces VOUT to also track the SS ramp. The time in msec needed for the SS ramp to reach the 750mV reference is: TSTART = Css × 150 (TSTART in μsec, Css in nF) At the end of this time, the SS pin has reached 750mV and the output voltage is at its nominal value. The FB comparator then switches over to the internal 750mV REF, and the SS pin is thereafter ignored. The 5μA current source remains on, so the Css capacitor continues to charge up to +5V. The startup waveforms when using a capacitor for the voltage ramp are shown in Figure 7. Shutdown When the EN pin is set low, the SS pin is discharged and the output DH/DL drivers are pulled low. There is a small delay between EN going low and DH/DL turning off. The shutdown delay is given by the equation: TSD_DELAY = Css × 19 (TSD_DELAY in usec, Css in nF) With DH/DL set low, there is no switching, and the output capacitor is discharged into the VOUT pin discharge resistance of 16 ohms. This provides a soft-discharge with no need for a clamp diode across the output capacitor. When DH/DL stop switching, then that side is placed into an inactive, low-power state. MOSFET Gate Drivers The DH and DL drivers are optimized to drive moderate high-side and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off ; another circuit monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Note: be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. SmartDriveTM Each side uses Semtech’s proprietary SmartDrive to reduce switching noise. The DH drivers will turn on the high-side MOSFET at a lower rate initially, allowing a softer, smooth turn-off of the low-side diode. Once the diode is off, the SmartDrive circuit automatically drives the high-side MOSFET on at a rapid rate. This technique reduces switching less while maintaining high efficiency, and also avoids the need for snubbers or series resistors in the gate drive. TSTART 5V VOUT 750mV SS linear ramp - 5uA current source into CSS SS EN EN CSS SS SC415 Figure 7 14 SC415 Applications Information (continued) Design example: VIN = 10V min, 20V max VOUT1 = 1.8V +/- 4% Load = 10A maximum Side1 will be used as an example. Inductor Selection Low inductor values result in smaller size but create higher ripple current. Higher inductor values will reduce the ripple current but are larger and more costly. Because wire resistance varies widely for different inductors and because magnetic core losses vary widely with operating conditions, it is often difficult to choose which inductor will optimize efficiency. The general rule is that higher inductor values have better efficiency at light loads due to lower core losses and lower peak currents, but at high load the smaller inductors are better because of lower resistance. The inductor selection is generally based on the ripple current which is typically set between 20% to 50% of the maximum load current. Cost, size, output ripple and efficiency all play a part in the selection process. The first step is to select the switching frequency. In this case VOUT1 will be used at a nominal 270kHz. For 15V input and 1.8V output, the typical on-time is: 1. 2. 3. 4. Nominal output voltage (VOUT) Static or DC output tolerance Transient response Maximum load current (IOUT) TONtyp = VOUT/VIN/Freq TONtyp = 444nsec. Figure 8 Design Procedure Prior to designing a switch mode supply, the input voltage, load current, and switching frequency must be specified. For notebook systems the maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage, and the minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. In general, four parameters are needed to define the design: There are two values of load current to consider: continuous load current and peak load current. Continuous load current is concerned with thermal stresses which drive the selection of input capacitors, MOSFETs and diodes. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors and design of the current limit circuit. The timing resistor RTON must be selected to provide TONtyp: RTON = (TONtyp – 35) × (VIN/(3.3 × VOUT) – 37 RTON = 976k. We will use RTON = 1Meg. Note that side2 will run typically 20% faster than side1, in this case 320kHz. 15 SC415 Applications Information (continued) During the DH on-time, voltage across the inductor is (VIN - VOUT). To determine the inductance, the ripple current must be defined. Smaller ripple current will give smaller output ripple voltage but will require larger inductors. The ripple current will also set the boundary for PSAVE operation. The switcher will typically enter PSAVE operation when the load current decreases to ½ of the ripple current; (i.e. if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then PSAVE will occur for loads less than 20% of maximum). The equation for inductance is: L = ( VIN - VOUT) × TON / IRIPPLE Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The ESR requirement is driven by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple, plus ½ of the peak-to-peak ripple. Changing the ripple voltage will lead to a change in DC output voltage. The design goal is +/-4% output regulation. The internal 750mV reference tolerance is 1%, and assuming 1% tolerance for the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from ½ of the ripple voltage, the allowable ripple is 4%, or 72mV for a 1.8V output. Although this is acceptable from a regulation standpoint, 72mV ripple is high for a 1.8V output and therefore more realistic ripple value of 36mV will be used (2% of VOUT). The maximum ripple current of 4.2A creates a ripple voltage across the ESR. The maximum ESR value allowed would create 36mV ripple: ESRMAX = VRIPPLE/IRIPPLEMAX = 36mV / 4.2A ESRMAX = 8.6 mΩ Use the maximum value for VIN, and for TON use the value associated with maximum VIN, and that side’s TON using the RTON value selected. For selecting the inductor, we start with the highest VOUT setting and a maximum ripple current of 4A. TON1 = 343 nsec at 20VIN, 1.8VOUT L = (20 - 1.8) × 343 nsec / 4A = 1.56μH We will use 1.5μH which will slightly increase the maximum IRIPPLE to 4.2A. Note: the inductor must be rated for the maximum DC load current plus ½ of the ripple current. The minimum ripple current is also calculated. This occurs when VIN is at the minimum value of 10V. TONVINMIN = 3.3 × (RTON+37) × (VOUT/VIN) + 35 TONVINMIN = 651nsec IRIPPLE = ( VIN - VOUT) × TON / L IRIPPLE_VINMIN = (10 – 1.8) × 651 nsec / 1.5μH = 3.55A While the ESR is chosen to meet ripple requirements, the output capacitance (μF) is typically chosen based on transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, defines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in a very small time), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the equation: COUTMIN = L × (IOUT + 1/2 × IRIPPLEMAX)2 _______________________ ( VPEAK2 - VOUT2) 16 SC415 Applications Information (continued) With a peak voltage VPEAK of 1.98V (180mV or 10% rise above 1.8V upon load release), the required capacitance is, COUTMIN = 1.5μH × (10 + 1/2 • 4.2) / (1.98 - 1.8 ) COUTMIN = 323μF 2 2 2 Note that 204μF is less than the 330μF needed to meet the harder (instantaneous) transient load release. Stability Considerations Unstable operation shows up in two related but distinctly different ways: fast-feedback loop instability due to insufficient ESR and double-pulsing. Loop instability can cause oscillations at the output as a response to line or load transients. These oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is a sign that the ESR should be increased. SC415 ESR Requirements The on-time control used in the SC415 regulates the valley of the output ripple voltage. This ripple voltage consists of a term generated by the ESR of the output capacitor and a term based on the capacitance charging and discharging during the switching cycle. A minimum ESR is required to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than one-third the switching frequency. The formula for minimum ESR is: ESRMIN = 3 / (2 × π × COUT × FREQ) The above requirements (323μF, 6.4mΩ) can be met using a single 330μF 6mΩ capacitor. Note that output voltage ripple is often higher than expected due to the ESL (inductance) of the capacitor. See the Stability Considerations section. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt in the inductor, then the inductor current can track change in load current, and there will be relatively less overshoot from a load release. The following formula can be used to calculate the needed capacitance for a given dILOAD/dt. ILPEAK = IMAX + 1/2 × IRIPPLEMAX ILPEAK = 10 + 1/2 × 4.2 = 12.1A Rate of change of Load current = dILOAD/dt IMAX = maximum DC load current = 10A COUT = ILPEAK × (L ×ILPEAK / VOUT - IMAX/dILOAD /dt) _________________________________ 2 × (VPEAK - VOUT ) Example: Load dI/dt = 2.5A/μsec This would cause the output current to move from 10A to zero in 4μsec. COUT = 12.1× (1.5μH×12.1/1.8 - 10/(2.5/1μsec) ________________________________ 2 × (1.98 - 1.8) COUT = 204 μF For applications using ceramic output capacitors, the ESR is generally too small to meet the above criteria. In these cases it is possible to create a ripple voltage ramp that mimics the ESR ramp. 17 SC415 Applications Information (continued) This virtual ESR ramp is created by integrating the voltage across the inductor, and coupling the signal into the FB pin as shown in Figure 9. The schematic with added capacitor C as shown in Figure 10. VOUT L DH C R1 COUT R2 RL DL CC CL To FB R1 COUT R2 To FB Figure 10 Figure 9 This capacitor should be left out until confirmation that double-pulsing exists. It is best to leave a spot on the PCB in case it is needed. FB/VOUT Ripple Waveform Because the constant on-time control method triggers a DH pulse whenever the FB waveform reaches the 750mV trip point, it is important that the VOUT and FB ripple waveforms are well shaped. This waveform will depend on the output capacitors. The idealized circuit has an inductor, a capacitor COUT with series ESR. The charging and discharging of COUT is generally much smaller than the ripple voltage due to ESR, so the resulting ripple waveform is generally determined by ESR only. Double-Pulsing Double-pulsing occurs because the ripple waveform seen at the FB pin is either too small, or because the FB and VOUT ripple waveform is very noisy and prone to cause premature triggering of the FB comparator. Both are discussed below. Increasing FB Ripple If the ripple waveform at FB is too small, the FB waveform will be susceptible to switching noise. Note that under normal conditions the FB voltage is within 10-20mV of the 750mV trip point. Noise can couple into the FB point from either side1 or side1, or even from an external circuit. This causes the FB comparator to trigger too quickly after the 330nsec minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output but in most cases is harmless. A way to remedy this is to couple more ripple into FB from VOUT. Note that the feedback resistor divider attenuates the FB ripple. This can be compensated by placing a small capacitor in parallel with the top resistor, which effectively increases the ripple that appears at FB. 18 SC415 Applications Information (continued) The result is a well-defined sawtooth waveform, as shown in Figure 11. Ripple Current VOUT ripple from ESR FB ripple In addition to the ESL, most applications also have a small capacitor in parallel with COUT; this is typically a small ceramic capacitor intended to absorb high frequency noise not filtered by the output capacitor, as shown by CB in Figure 13. Ripple Current 750 mV VOUT ripple from ESR LX (to MOSFETs) R1 To FB COUT R2 ESR VOUT LOAD VOUT ripple from ESL VOUT ripple from ESL FB ripple VOUT ESL ESR R2 COUT 750 mV LX (to MOSFETs) R1 LOAD Figure 11 In real applications, the output capacitor also has some series inductance (ESL), and this can have a large effect on ripple. The ripple current creates voltage across the ESL; this is a square wave similar to the LX waveform. The result is shown below. Note the fast rising and falling edges created by the ESL as show in Figure 12. Ripple Current VOUT ripple from ESR VOUT ripple from ESL VOUT ripple from ESL FB ripple VOUT R1 To FB R2 COUT ESL ESR To FB CB Figure 13 This capacitor CB can have a large effect on the ripple waveform. The switch transitions are fast, typically 10-30nsec. At this high speed, the output capacitor impedance is dominated by ESL. In parallel with this is CBP. The effective circuit is a parallel L-C filter, with ESL in parallel with CPB. Thus the choice of CB can have significant effect on the ripple waveform. The parallel LC circuit can ring at high levels, and this can cause the VOUT and therefore FB ripple to go below the trip point too early. Since the FB waveform goes below the threshold soon after the DH pulse is finished, there is the potential for double-pulsing. 750 mV LX (to MOSFETs) LOAD Figure 12 19 SC415 Applications Information (continued) Figure 14 shows example of this. A second solution is to add a small RC filter in series with the FB resistor path, shown by RF/CF. This RC filter is intended to remove the high-frequency noise but still allow the ripple to reach the FB pin as shown in Figure 16. Recommended values are 10 ohms and 10nF. Actual ripple with CBP Idealized ESL ripple VOUT RF FB trip point R1 CF To FB R2 VOUT ripple False trigger on FB FB ripple FB trip point False trigger on FB Figure 16 Figure 14 Dropout Performance The VOUT adjust range for continuous-conduction operation is limited by the fixed 330nsec (typical) Minimum Off-time One-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. There are two ways to deal with this issue. One is to use a larger ceramic capacitor, typically 2.2–10μF, which significantly smooths the ripple waveform as shown in Figure 15. The IC duty-factor limitation is given by: Actual ripple with CB = (~2.2 – 10 uF) Ripple from ESL DUTY = TONMIN/(TONMIN + TOFFMAX) FB trip point Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. Figure 15 20 SC415 Applications Information (continued) SC415 System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the switching frequency variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed to trip when the feedback pin is 750mV, +/-1% over the range of 0 to 85°C. The on-time pulse is programmed using the RTON resistor to give a desired frequency. However, some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, If the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25 volts, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. The use of 1% feedback resistors contributes typically 1% error. If tighter DC accuracy is required use 0.1% resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. The output ESR also affects the ripple and thus the DC output voltage. Switching Frequency Variations The switching frequency will vary somewhat due to line and load conditions. The line variations are a result of a fixed offset in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As input voltage increases, these factors make the actual DH on-time slightly longer than the idealized on-time. The net effect is that frequency tends to fall slightly with increasing input voltage. The frequency variation with load is due to losses in the power train from IR drop and switching losses. For a conventional PWM constant-frequency topology, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time topology must also overcome the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). Since the on-time is constant for a given VOUT/VIN combination, the way to increase duty cycle is to gradually shorten the off-time. The net effect is that switching frequency increases slightly with increasing load. 21 SC415 Applications Information (continued) Layout Guidelines As with any switch-mode converter, and especially a dual-channel converter, a good pcb layout is essential for optimum performance. The following guidelines should be used for pcb layout. Placement Note that the pins on the IC are arranged in four groups, i.e. Side1 Power, Side2 Power, Side1 Analog, and Side2 Analog, as shown below. Ground Connections When doing placement, be aware that there are four grounds. 1. 2. 3. 4. Power ground for Side1 Power ground for Side2 Analog ground for Side1 Analog ground for Side2 Side 1 Power/Gate Drive LX1 BST1 VDD1 1 24 19 18 Side 2 Power/Gate Drive LX2 BST2 VDD2 Note that grounds (1) and (2) are high-current and contain high noise. These grounds carry the DL gate drive current as well as the high switching current through the MOSFETs and low-side diode. It is important to note that the SC415 has only one power ground pin (PAD, pin 25), which must drive DL for both side1 and side2. As such, the low-side MOSFET and diode will need to be near the IC. Grounds (3) and (4) are low-current and intended for lownoise VOUT/FB ripple sensing. Note that there is only one analog ground pin (RTN, pin 9) which shared between sides 1 and 2. Proper connection between the grounds is needed for good operation. Generally, all ground connections between the power components and the SC415 should be short and direct, without vias where possible. Each side has significant high-current switching in the ground path, moving between the input capacitors, the lowside MOSFET, the low-side diode if used, and the output capacitors. Moreover, each side has significant highcurrent pulses to/from the ground PAD, created by the DL drive to the low-side MOSFETs. The DL gate-drive current peaks can be 2 amps or more, with fast switching. As such the ground connection between the low-side MOSFETs and the ground PAD should be as short and wide as practical. Note that the ground PAD, which is the return path for the high-noise DL drive current, is not accessible on the top layer of the pcb, due to the other pins. The ground PGD1 PGD2 ILIM1 ILIM2 DH1 SC415 DL1 EN1 SS1 6 7 12 GND (PAD) 13 DL2 EN2 SS2 RTN VOUT1 TON FB1 FB2 VOUT2 DH2 Side 1 Analog Side 2 Analog Figure 17 For placement, power devices for side1 should be grouped together near the gate drive pins for side1 (pins 23-24 and 1-8). Power devices for side2 should be grouped together near the gate-drive pins for side2 (pins 15-20). The feedback and VOUT sense components should be located near the FBx/VOUTx pins. This includes the feedback resistors and capacitors if used. 22 SC415 Applications Information (continued) PAD connection to the MOSFETs must therefore be done on an inner or bottom layer. For this reason, it is best to place the low-side MOSFET on the opposite side of the pcb, to allow a wide and direct connection to the ground PAD on the bottom layer. Otherwise an inner layer must be used for the ground PAD connection; if needed, this should be done with many vias to minimize the highfrequency impedance. This applies to both side1 and side2 MOSFETs. The remaining power devices should then be placed with their ground pins near each other, and near the IC. That is, the ground connections between the IC, the low-side MOSFET, the low-side diode (if used), the input capacitors, and the output capacitor, should be short. The other nonground power connections (from input cap to high-side MOSFET, from MOSFETs to inductor, and from inductor to output capacitor) should be short and wide as well, to minimize the loop length and area. Use short, wide traces from the DL/DH pins to the MOSFETs to reduce parasitic impedance; the low-side MOSFET is most critical. Maintain a length to width ratio of