SC419

SC419 POWER MANAGEMENT Features  EcoSpeedTM DC-DC Converter with Integrated Boost Diode Description The SC419 is a synchronous buck power supply controller. I t features a bootstrap switch in a space-saving MLPQ3 x 3mm 20-pin package. The device is highly efficient and uses minimal PCB area. It uses pseudo-fixed frequency adaptive on-time operation to provide fast transient response. The SC419 supports using standard capacitor types such as electrolytic or special polymer in addition to ceramic, at switching frequencies up to 1MHz. The programmable frequency, synchronous operation, and programmable power-save provide high efficiency operation over a wide load range. Additional features include cycle-by-cycle current limit, soft-start, under and over-voltage protection, programmable over-current protection, soft shutdown, selectable power-save modes, and programmable ultra-sonic powersave. The device also provides an enable input and a p ower good output, useful for sequencing multiple devices. The input voltage can range from 3V to 28V. The wide input voltage range and programmable frequency make the device extremely flexible and easy to use in a broad range of applications. Support is provided for single cell or multi-cell battery systems in addition to traditional DC power supply applications. • • • • • •       Power system Input voltage — 3V to 28V Integrated bootstrap switch 1% reference tolerance -40 to +85 °C EcoSpeedTM architecture with pseudo-fixed frequency adaptive on-time control Internal soft-start and soft-shutdown at output SmartDriveTM Logic input/output control Independent control EN for LDO and switcher Programmable VIN UVLO threshold Power good output Selectable power save mode Programmable ultrasonic power save mode Protections Over-voltage/under-voltage TC compensated RDS(ON) sensed current limit Thermal shutdown Smart power save Output capacitor types High ESR — SP, POSCAP, OSCON Ceramic capacitors Package — 3 x 3mm, 20-pin MLPQ Lead-free and halogen free RoHS and WEEE compliant • • • • • • • • • • • Applications Office automation and computing  Networking and telecommunication equipment  Point-of-load power supplies and module replacement  Typical Application Circuit VIN PGOOD ENABLE RTON 5V 0.1µF 5V VIN VIN PGOOD EN TON VDDA VDDP 1µF DH LX VIN CIN VOUT + L1 RILIM SC419 BST ILIM DL VOUT COUT PSV PSV AGND PGND FB July 27, 2010 © 2010 Semtech Corporation 1 SC419 Pin Configuration AGND TON AGND IL M EN Ordering Information Device SC419ULTRT(1)(2) SC419EVB 15 14 Package MLPQ-UT20 Evaluation Board 20 19 18 17 16 FB NC VDDA VOUT NC Top View 1 2 3 4 5 PGOOD PSV VDDP DL PGND Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. AGND PAD 13 12 11 6 7 8 9 10 V IN NC BST DH MLPQ-UT20 Marking Information 419 yyww xxxx yyww = Date Code xxxx = Semtech Lot Number LX 2 SC419 Absolute Maximum Ratings(1) LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +30 LX to PGND (V) (transient — 100ns) . . . . . . . . . . . -2 to +30 DH, BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 DH, BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 EN, FB, ILIM, to AGND (V) . . . . . . . . . . . -0.3 to +(VDDA + 0.3) PGOOD, PSV, VOUT to AGND (V) . . . . -0.3 to +(VDDA + 0.3) TON to AGND (V). . . . . . . . . . . . . . . . . . . -0.3 to +(VDDA -1.5) VDDP to PGND, VDDA to AGND (V) . . . . . . . . . . . . 0.3 to +6 VDDA to VDDP (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Recommended Operating Conditions Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 VDDA to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5 VDDP to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5 VOUT to AGND (V). . . . . . . . . . . . . . . . . . . . . . . 0.5 to VDDA Thermal Information Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150 Operating Junction Temperature (°C) . . . . . . . . -40 to +125 Thermal resistance, junction to ambient(2) (°C/W) . . . . . 50 Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260 Electrical Characteristics Unless specified: VIN =12V, VDDA = VDDP = 5V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, Typical Application Circuit Parameter Input Supplies Input Supply Voltage VDDA, VDDP Voltage Conditions Min Typ Max Units 3 4.5 Measured at VDDA pin, rising edge 3.7 3.5 3.9 3.6 0.3 EN = AGND EN = AGND EN = 5V, RPSV = 115kΩ, VFB > 500mV(1) EN = 5V, PSV = open (float), VFB > 500mV(1) Operating fSW = 250kHz, PSV = VDDA, no load(1) Static VIN and load, 0 to +85 °C 0.496 0.495 8.5 3 3 0.7 10 0.500 28 5.5 4.1 V V VDDA UVLO Threshold Measured at VDDA pin, falling edge VDDA UVLO Hysteresis VIN Supply Current 3.75 V V 20 7 μA μA VDDA + VDDP Supply Current mA 0.504 0.505 V V FB On-Time Threshold Static VIN and load, -40 to +85 °C 3 SC419 Electrical Characteristics (continued) Parameter Frequency Range Timing On-Time Minimum On-Time (1) Minimum Off-Time(1) Soft-Start Soft-Start Ramp Time(1) Analog Inputs/Outputs VOUT Input Resistance Current Sense Zero Cross Detector Threshold Power Good Upper limit, VFB > internal 500mV reference Lower limit, VFB < internal 500mV reference Start-Up Delay Time Fault (noise immunity) Delay Time(1) Leakage Power Good On-Resistance Fault Protection ILIM Source Current ILIM Source Current Temperature Coefficient(1) ILIM Comparator Offset Output Under-Voltage Threshold Smart Power-Save Protection Threshold(1) Over-Voltage Protection Threshold Over-Voltage Fault Delay(1) Over-Temperature Shutdown(1) 10°C hysteresis VFB with respect to internal 500mV reference, 8 consecutive cycles VFB with respect to internal 500mV reference VFB with respect to internal 500mV reference -8 9 10 0.41 0 -25 +10 +20 5 150 +8 11 μA %/°C mV % % % μs °C 10 Includes Soft-Start Ramp Time +20 -10 2 5 1 % % ms µs µA Ω LX - PGND -7 0 +7 mV 500 kΩ VOUT ramp from zero to programmed value 850 μs Forced continuous mode operation, VIN = 15V, VOUT = 5V, RTON = 300kΩ 2385 2650 80 250 2915 ns ns ns Conditions Continuous mode operation Min Typ Max 1000 Units kHz Power Good Threshold 4 SC419 Electrical Characteristics (continued) Parameter Logic Inputs/Outputs Logic Input High Voltage - EN Logic Input High Voltage - PSV Logic Input Low Voltage - EN EN Input Bias Current FB Input Bias Current PSV Input Bias Current High-Side Driver (DH, BST, LX) Peak Current(1) RDH_PULL-UP, LX < 0.5V On Resistance RDH_PULL-UP, LX > 0.5V RDH_PULL-DOWN Rise Time(1) Fall Time(1) Propagation Delay(1) Shoot-thru Protection Delay(1) Bootstrap Switch On Resistance CDH-LX = 3nF CDH-LX = 3nF From FB Comparator Input to DH 30 10 2.0 3.0 1.0 0.6 22 12 45 20 10 60 30 6.0 2.0 1.2 A Ω Ω Ω ns ns ns ns Ω Forced continuous mode (PSV pulled to VDDA); PSV with respect to VDDA With respect to VDDA EN = VDDA or AGND FB = VDDA or AGND PSV = VDDA -10 -1 1 1.0 -0.4 0.4 +10 +1 V V V μA μA μA Conditions Min Typ Max Units Low-Side Driver (DL, VDDP, PGND) Peak Current(1) RDL_PULL-UP RDL_PULL-DOWN Rise Time(1) Fall Time(1) Notes: (1) Guaranteed by design. CDL = 3nF CDL = 3nF 4.0 1.3 0.50 7 3.5 2.1 0.86 A Ω Ω ns ns On Resistance 5 SC419 Detailed Application Circuit EN PGOOD RTON 154kΩ PAD 1 FB NC 20 19 AGND TON 18 AGND 17 EN 16 ILIM RILIM 10kΩ 15 14 13 12 11 RPSV (see note) 1µF 5V PGOOD PSV 5V 2 3 4 100nF 5 VDDA VOUT NC SC419 VDDP DL PGND VIN BST VIN NC DH VIN 100nF 6 7 8 9 10 LX Q1 CIN1 CIN2 100nF Q2 L1 12V to 1.05V @ 10A, 250kHz RFB1 11kΩ CTOP 100pF COUT1 + + COUT2 10nF VOUT RFB2 10kΩ Key Components Component CIN1, CIN2 COUT1, COUT2 L1 (option 1) L1 (option 2) Q1 Q2 Value 10µF/25V 220µF/15mΩ/6.3V 0.88µH/2.3mΩ 1.0µH/2.3mΩ IRF7821 IRF7832 Manufacturer Murata Panasonic NEC-Tokin Vishay I.R. I.R. Part Number GRM32DR71E106KA12L EEFUE0J221R MPC1040LR88C IHLP4040DZER1R0M11 IRF7821 IRF7832 Web www.murata.com www.panasonic.com www.nec-tokin.co www.vishay.co www.irf.com www.irf.com Note - RPSV: Use 115kΩ for Ultrasonic operation Remove RPSV for Power-Save operation Connect PSV pin to VDDA for Forced Continuous Mode operation 6 SC419 Typical Characteristics Characteristics in this section are based on using the Detailed Application Circuit. Efficiency vs. Load — Forced Continuous Mode 100 VIN = 12V, VOUT = 1.050V, PSV = VDDA 1.100 1.075 OUT VIN = 12V, VOUT = 1.050V, PSV = VDDA V vs. Load — Forced Continuous Mode 90 85% Efficiency (%) 1.050 VOUT (V) 80 1.025 1.000 70 60 0.975 0.950 50 0 1 2 3 4 5 6 IOUT (A) 7 8 9 10 0 1 2 3 4 5 IOUT (A) 6 7 8 9 10 Efficiency vs. Load — Ultrasonic Power-save 100 VIN = 12V, VOUT = 1.050V, RPSV = 115kΩ 1.100 1.075 1.050 VOUT vs. Load — Ultrasonic Power-save Mode VIN = 12V, VOUT = 1.050V, RPSV = 115kΩ 85% 80 Efficiency (%) 60 VOUT (V) 1.025 1.000 40 0.975 20 0.01 0 .1 IOUT (A) 1 10 0.950 0 1 2 3 4 5 IOUT (A) 6 7 8 9 10 Efficiency vs. Load — Power-save Mode 100 VIN = 12V, VOUT = 1.050V, PSV = open 1.100 1.075 1.050 Efficiency (%) VOUT vs. Load — Power-save Mode VIN = 12V, VOUT = 1.050V, PSV = open 85% 80 60 VOUT (V) 1.025 1.000 40 0.975 20 0.01 0 .1 IOUT (A) 1 10 0.950 0 1 2 3 4 5 IOUT (A) 6 7 8 9 10 7 SC419 Typical Characteristics (continued) Characteristics in this section are based on using the Detailed Application Circuit. Forced Continuous Operation — No Load VIN = 12V, VOUT = 1.05V, PSV = VDDA Transient Response — Load Rising VIN = 12V, VOUT = 1.05V, RPSV = 115k Ω, IOUT = 0A to 10A VOUT (50mV/div) IOUT (5A/div) VOUT (50mV/div) LX (10V/div) DH (10V/div) DL (5V/div) Time (10µs/div) LX (10V/div) Time (20µs/div) Ultrasonic Power-save Operation — No Load VIN = 12V, VOUT = 1.05V, RPSV = 115k Ω VOUT (50mV/div) VOUT (50mV/div) IOUT LX (10V/div) DH (10V/div) DL (5V/div) Time (10µs/div) LX (10V/div) (5A/div) Transient Response — Load Falling VIN = 12V, VOUT = 1.05V, RPSV = 115k Ω, IOUT = 10A to 0A Time (20µs/div) Power-save Operation — No Load VIN = 12V, VOUT = 1.05V, IOUT = 0A, PSV = open VOUT (50mV/div) LX (10V/div) LX (5V/div) VOUT (500mV/div) Enable to Power Good True VIN = 12V, VOUT = 1.05V, PSV = open DH (10V/div) DL (5V/div) Time (10ms/div) PGOOD (5V/div) Time (400µs/div) 8 SC419 Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PAD Pin Name FB NC VDDA VOUT NC VIN NC BST DH LX PGND DL VDDP PSV PGOOD ILIM EN AGND TON AGND AGND Pin Function Feedback input for switching regulator — connect to an external resistor divider from output — used to program the output voltage. No Connection Supply input for internal analog circuits — connect to 5V supply — and the sense input for VDDA UVLO. Bypass with a 100nF minimum capacitor to AGND. Output voltage sense pin No Connection Input supply voltage — connect to the same supply as the high-side MOSFET. Connect a 100nF capacitor to AGND. No Connection Bootstrap pin — connect a 100nF minimum capacitor from BST to LX to develop the floating voltage for the high-side gate drive. High-side gate drive output Switching (phase) node Power ground Low-side gate drive output Supply input for the DH and DL gate drives — connect to the same 5V supply used for VDDA. Bypass with a 1μF minimum capacitor to PGND. Power-save programming input — connect a resistor to AGND to set the minimum power-save frequency. Float pin to select power-save at no minimum frequency or pull up to VDDA to disable power-save. Open-drain Power Good indicator — high impedance indicates the switching regulator output power is good. An external pull-up resistor is required. Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX. Enable input for switching regulator — logic low disables the switching regulator or logic high enables the switching regulator. Analog ground ON time programming input — set the on-time by connecting through a resistor to AGND. Connect this pin to AGND along with pins 18 and PAD. Analog ground 9 SC419 Block Diagram VDDA 3 VDDA AGND A PGOOD 15 PSV 14 EN 17 VIN 6 VDDP VDDP 13 VDDA UVLO Control & Status DL Bootstrap Switch 8 BST Reference 9 Soft Start On-time Generator FB Comparator Gate Drive Control DL 12 11 Zero Cross Detector VOUT 4 Current Limit 16 10 VDDP DH LX FB 1 DL PGND TON 19 ILIM A = connected to pins 18, 20, and PAD Not used: pins 2, 5, 7 10 SC419 Applications Information General Description The SC419 is a step down synchronous DC-DC buck controller. It provides high efficiency operation in a space saving 3 x 3 (mm) 20-pin package. The programmable operating frequency range from 200kHz to 1MHz enables optimizing the configuration for PCB area and efficiency. The controller uses a pseudo-fixed frequency adaptive on-time control. This allows fast transient response which permits the use of smaller output capacitors. VIN. The period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time configuration, the device automatically antici pates the on-time needed to regulate VOUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: • • • • • Input Voltage Requirements The SC419 requires three input supplies for normal operation: VIN, VDDA, and VDDP. VIN can operate over the wide range of 3V to 28V. VDDA and VDDP require an external 5V supply. VDDA and VDDP should be connected to the same source voltage. Psuedo-fixed Frequency Adaptive On-time Control The PWM control method used by the SC419 is pseudofixed frequency, adaptive on-time, as shown in Figure 1. The ripple voltage generated at the output capacitor ESR is used as a PWM ramp signal. This ripple is used to trigger the on-time of the controller. VIN TON VLX Q1 VLX L Q2 ESR + FB COUT CIN VFB Predictable operating frequency compared to other variable frequency methods. Reduced component count by eliminating the error amplifier and compensation components. Reduced component count by removing the need to sense and control inductor current. Fast transient response — the response time is controlled by a fast comparator instead of a typically slow error amplifier. Reduced output capacitance due to fast transient response. One-Shot Timer and Operating Frequency One-shot timer operation is shown in Figure 2. The FB comparator output goes high when VFB is less than the internal 500mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to V OUT, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to VIN. When the capacitor voltage reaches VOUT, the on-time is completed and the high-side MOSFET turns off. FB Comparator + FB Threshold VOUT FB 500mV Gate Drives DH VIN Q1 VLX Q2 L ESR COUT + VOUT FB Figure 1 — PWM Control Method, VOUT Ripple The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and VOUT VIN RTON One-Shot Timer DL On-time = K x RTON x (VOUT/VIN) Figure 2 — On-Time Generation 11 SC419 Applications Information (continued) This method automatically produces an on-time that is proportional to VOUT and inversely proportional to VIN. Under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. fSW VOUT TON VIN VOUT 0 .5 1 R1 R2 VRIPPLE 2 Forced Continuous Mode Operation The SC419 operates in FCM (Forced Continuous Mode) by connecting the PSV pin to VDDA. (The PSV pin should not exceed the VDDA supply.) See Figure 4 for FCM waveforms. In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid cross-conduction. This results in uniform frequency across the full load range with the trade-off being reduced efficiency at light loads due to the high-frequency switching of the MOSFETs. FB Ripple Voltage (VFB) FB threshold (500mV) The SC419 uses an external resistor to set the on-time which indirectly sets the frequency. The on-time can be programmed to provide an operating frequency from 200kHz to 1MHz using a resistor between the TON pin and ground. The resistor value is selected by the following equation. RTON (TON 10ns) VIN 25pF VOUT The maximum RTON value allowed is shown by the following equation. R TON _ MAX VIN _ MIN 15 A Inductor Current DC Load Current Immediately after the on-time, the DL output drives high to energize the low-side MOSFET. DL has a minimum high time of ~250ns, after which DL continues to stay high until one of the following occurs: On-time (TON) DH DH on-time is triggered when VFB reaches the FB Threshold. • • VFB falls below the 500mV reference The Zero Cross Detector trips if power-save is active DL DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. VOUT Voltage Selection Figure 4 — Forced Continuous Mode Operation The switcher output voltage can be programmed higher than 5V with careful design. In this case the VOUT pin cannot connect directly to the switcher output due to its t he maximum voltage rating. An additional resistor divider network is required to connect from the switcher output to the VOUT pin. The voltage at the VOUT pin should be at least 500mV lower than the VDDA supply, to prevent the VLDO switch-over function. For example, the voltage at the VOUT pin can be 4V if VDDA is set for 5V. When the SC418 operates from an external power source and the LDO is disabled by grounding the ENL pin, the voltage at the VOUT pin can be as high as shown in Recommended Operating Conditions. Note that RTON must be adjusted higher by the same divider ratio to The output voltage is regulated by comparing VOUT as seen through a resistor divider at the FB pin to the internal 500mV reference (see Figure 3). VOUT R1 To FB pin R2 Figure 3 — Output Voltage Selection Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC value of VOUT is offset by the output ripple according to the following equation. 12 SC419 Applications Information (continued) maintain the desired on-time. On-time is calculated according to the voltage at the VOUT pin. The equation for determining the RPSV resistor value is shown next. The desired minimum frequency is fSWMIN. RPSV 1 350pF fSWMIN Programmable Ultra-sonic Power-Save Operation The device provides programmable ultra-sonic powersave operation at light loads. The minimum operating fre quency is programmed by connecting a resistor from PSV to AGND. The SC419 uses the PSV resistor to set an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds the programmed timer, DL drives high to turn the low-side MOSFET on. This draws current from VOUT through the inductor, forcing both VOUT and VFB to fall. When VFB drops to the 500mV threshold, the next DH on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the l ow-side MOSFET turns on, and the internal timer is restarted. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. This ends the cycle until VFB falls below the 500mV threshold, or the internal timer forces another DL turn-on. B ecause the period between on-times is limited to a maximum value, a minimum operating frequency is maintained. Figure 5 shows ultrasonic power-save operation. minimum frequency FB Ripple Voltage (VFB) Power-Save Mode Operation The device provides power-save operation at light loads with no minimum operating frequency, selected by floating the PSV pin (no connection). In this mode of operation, the internal zero crossing comparator monitors the i nductor current via the voltage across the low-side MOSFET during the off-time. If the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save operation. It will then turn off the lowside MOSFET on each subsequent cycle, provided that the current crosses zero. After the low-side MOSFET is off, both high-side and low-sides MOSFETs remain off until VFB drops to the 500mV threshold. While the MOSFETs are off the load is supplied by the output capacitor. If the inductor current does not reach zero on any switching cycle, the controller immediately exits power-save and returns to forced continuous mode. Figure 6 shows power-save operation at light loads. Dead time varies according to load FB threshold (500mV) Zero (0A) FB threshold (500mV) (0A) FB Ripple Voltage (VFB) Inductor Current Inductor Current On-time (TON) On-time (TON) DH programmable time-out DL DH On-time is triggered when VFB reaches the FB Threshold DH DL DH On-time is triggered when VFB reaches the FB Threshold. After the programmable time-out, DL drives high if VFB has not reached the FB threshold. DL drives high when on-time is completed. DL remains high until inductor current reaches zero. Figure 5 — Ultrasonic Power-Save Operation Figure 6 — Power-Save Operation 13 SC419 Applications Information (continued) Smart Power-Save Protection Active loads may leak current from a higher voltage into the output. Under light load conditions with power-save enabled, this can force VOUT to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. Smart power-save prevents this condition. When the FB voltage exceeds 10% above nominal (exceeds 550mV), the device immediately disables power-save and DL drives high to turn on the low-side MOSFET. This draws current from VOUT through the inductor and causes VOUT to fall. When VFB drops back to the 500mV trip point, a normal TON switching cycle begins. This method prevents a hard OVP shutdown and cycles energy from VOUT back to VIN. It also minimizes operating power by avoiding forced conduction mode operation. Figure 7 shows typical waveforms for the Smart Power-save feature. VOUT drifts up to due to leakage current flowing into COUT Smart Power Save Threshold (550mV) FB threshold DH and DL off High-side Drive (DH) Single DH on-time pulse after DL turn-off Low-side Drive (DL) DL turns on when Smart PSAVE threshold is reached DL turns off when FB threshold is reached Normal DL pulse after DH on-time pulse VOUT discharges via inductor and low-side MOSFET Normal VOUT ripple prevent undesired or erratic startup, the EN pin should not be allowed to float as open-circuit. Current Limit Protection The SC419 features programmable current limiting, which is accomplished using the RDSON of the lower MOSFET for current sensing. The current limit is set by RILIM resistor which connects from the ILIM pin to the drain of the lowside MOSFET. When the low-side MOSFET is on, an internal 10μA current flows from the ILIM pin and through the RILIM resistor, creating a voltage drop across the resistor. While the low-side MOSFET is on, the inductor current flows through it and creates a voltage across the RDS(ON). The voltage across the MOSFET is negative with respect to PGND. If this MOSFET voltage drop exceeds the voltage across RILIM, the voltage at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on, preventing another high-side ontime until the current in the low-side MOSFET reduces enough to bring the voltage at the ILIM pin back up to zero. This method regulates the inductor valley current at the level shown by ILIM in Figure 8. Inductor Current IPEAK ILOAD ILIM Time Figure 7 — Smart Power-Save Figure 8 — Valley Current Limit Enable Input The EN input is a logic level input. When EN is low (grounded), the regulator is off and in its lowest power state. When EN is low and VDDA is above the VDDA UVLO threshold, the output soft-discharges into the VOUT pin through an internal 15Ω resistor. When EN is a logic high (>1V) the switching regulator is enabled. The EN input has internal resistors: a 2MΩ pullup to VDDA, and a 1MΩ pulldown to AGND. These resistors will normally cause the EN voltage to be above the logic high trip point as VDDA reaches the VDDA UVLO threshold. To 14 SC419 Applications Information (continued) The current limit schematic with the RILIM resistor is shown in Figure 9. VIN + CIN L VOUT Power Good Output The PGOOD (Power Good) output is an open-drain output which requires a pull-up resistor. When the voltage at the FB pin is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the FB voltage returns above -8% of nominal. PGOOD is held low during start-up and will not be allowed to transition high until soft-start is com pleted (when VFB reaches 500mV). The delay time starting from EN going high is typically 2ms. PGOOD will transition low if the FB voltage exceeds +20% o f nominal, which is also the over-voltage threshold (600mV). PGOOD also pulls low if the EN pin is low when VDDA is present. BST CBST DH LX ILIM DL PGND RILIM Q1 Q2 D2 COUT + Figure 9 — Valley Current Limit Setting the valley current limit to 10A results in a peak inductor current of 10A plus peak ripple current. In this situation the average current through the inductor is 10A plus one-half the peak-to-peak ripple current. The RILIM value is calculated by the next equation. RILIM RDSON ILIM 10 A Output Over-Voltage Protection OVP (Over-voltage protection) becomes active as soon as the device is enabled. The OVP threshold is set at 500mV + 20% (600mV). When VFB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off until the EN input is toggled or VDDA is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Soft-Start of PWM Regulator Soft-start is achieved in the PWM regulator by using an internal voltage ramp as the reference for the FB comparator. The voltage ramp is generated using an internal charge pump which drives the reference from zero to 500mV in 1.2mV increments, using an internal 500kHz oscillator. When the ramp voltage reaches 500mV, the ramp is ignored and the FB comparator switches over to a f ixed 500mV threshold. During soft-start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft-start profile. Typical soft-start ramp time is 850μs. During soft-start the regulator turns off the low-side MOSFET on any cycle if the inductor current falls to zero, regardless of the PSAVE mode setting. This prevents negative inductor current, allowing the device to start into a pre-biased output. Output Under-Voltage Protection When VFB falls 25% below its nominal voltage (falls to 375mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN is toggled or VDDA is cycled. VDDA UVLO and POR The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib its switching and tri-states the DH/DL drivers until VDDA rises above 3.9V. When VDDA exceeds 3.9V, an internal POR (Power-On Rese) resets the fault latch and the softstart counter and then the SC419 begins the soft-start c ycle. The device will shut off if VDDA falls below 3.6V. VDDP does not have ULVO protection. 15 SC419 Applications Information (continued) Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design. To select RTON, use the maximum value for VIN, and for TON use the value associated with maximum VIN. T ON V INMAX f SW V OUT TON = 318 ns at 13.2VIN, 1.05VOUT, 250kHz Substituting for RTON results in the following solution. RTON = 154.9kΩ, use RTON = 154kΩ Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then Power-save operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is (VIN - VOUT ). The following equation is used to determine the inductance. L ( VIN VOUT ) TON IRIPPLE • • • • Nominal output voltage (VOUT ) Static or DC output tolerance Transient response Maximum load current (IOUT ) There are two values of load current to evaluate — continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. • • • • VIN = 12V + 10% VOUT = 1.05V + 4% fSW = 250kHz Load = 10A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 250kHz. A resistor, RTON is used to program the on-time (indirectly setting the frequency) using the following equation. RTON (TON 10ns) VIN 25pF VOUT In this example the inductor ripple current is set equal to 50% of the maximum load current. Thus ripple current will be 50% x 10A or 5A. 16 SC419 Applications Information (continued) To find the minimum inductance needed, use the VIN and TON values that correspond to VINMAX. L (13.2 1.05) 318ns 5A 0.77 H A slightly larger value of 0.88µH is selected. This will decrease the maximum IRIPPLE to 4.4A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum VIN conditions is also checked using the following equations. TON _ VINMIN IRIPPLE ( VIN The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. COUTMIN L IOUT 1 IRIPPLEMAX 2 2 2 VPEAK VOUT 2 25pF RTON VOUT VINMIN VOUT ) TON L 10ns 384ns Assuming a peak voltage VPEAK of 1.150 (100mV rise upon load release), and a 10A load release, the required capacitance is shown by the next equation. 0.88 H 10 COUTMIN 1.15 2 1 4 .4 2 1.05 2 2 IRIPPLE _ VINMIN (10.8 1.05 ) 384ns 088 H 4.25 A COUTMIN = 595µF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 500mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following five equations can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 10 + 1/2 x 4.4 = 12.2A Rate of change of Load Current dlLOAD dt Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 500mV reference tolerance is 1%. Allowing 1% tolerance from the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 42mV for a 1.05V output. The maximum ripple current of 4.4A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. ESRMAX VRIPPLE 42mV 4 .4 A IRIPPLEMAX ESRMAX = 9.5 mΩ 17 SC419 Applications Information (continued) IMAX = maximum load release = 10A L COUT ILPK ILPK VOUT 2 VPK IMAX dlLOAD VOUT dt increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small capacitor across the upper feedback resistor, as shown in Figure 10. This capacitor should be left unpopulated unless it can be confirmed that double-pulsing exists. Adding the CTOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. CTOP Example dlLOAD dt 2 .5 A s This would cause the output current to move from 10A to zero in 4µs. The output capacitance required in this case is shown by the following equation. 0.88 H 12.2 10 1s 1.05 2.5 2 1.15 1.05 COUT 12.2 VOUT R1 R2 To FB pin COUT = 379 µF Note that COUT is much smaller in this example, 379µF compared to 595µF based on a worst-case load release. To meet the two design criteria of minimum 379µF and maximum 9mΩ ESR, select two capacitors rated at 220µF and 15mΩ ESR. It is recommended that an additional small capacitor be placed in parallel with COUT in order to filter high frequency switching noise. Figure 10 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of adding trace resistance is decreased load regulation. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis18 SC419 Applications Information (continued) charging during the switching cycle. For most applications the ripple voltage is dominated by the ESR of the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre quency. The formula for minimum ESR is shown by the following equation. ESR MIN 2 3 C OUT f sw The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 500mV, 1%. The on-time pulse from the SC419 in the design example is calculated to give a pseudo-fixed frequency of 250kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors contributes up to 1% error. If tighter DC accuracy is required, 0.1% resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. When applications use ceramic output capacitors, the ESR is normally too small to meet the minimum ESR criteria. In these applications it is necessary to add a small virtual ESR network composed of two capacitors and one resistor, as shown in Figure 11. This network creates a ramp voltage across CL, analogous to the ramp voltage generated across the ESR of a standard capacitor. This ramp is then capacitively coupled into the FB pin via capacitor CC. L Highside RL CC FB pin CL R1 COUT Lowside R2 Figure 11 — Virtual ESR Ramp Current Dropout Performance The output voltage adjust range for continuous-conduction operation is limited by the fixed 250ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The duty-factor limitation is shown by the following equation. DUTY TON(MIN) TON(MIN) TOFF(MAX ) 19 SC419 Applications Information (continued) Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As VIN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency con verter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset the losses the off-time will tend to reduce slightly as load i ncreases. The net effect is that switching frequency increases slightly with increasing load. • Connect PGND and AGND together with a zero ohm resistor or copper trace. Make the connection near the AGND and PGND pins of the IC. PCB Layout Guidelines As with any switch-mode converter, good PCB layout is essential to achieving high performance. The following guidelines will provide an optimum PCB layout. The device layout can be considered in four parts; Power Components Use short, wide connections between the power components: Input capacitors and high-side MOSFETs High-side and Low-side MOSFETs and inductor (LX connection). Use wide copper traces to provide high current carrying capacity and for heat dissipation. Inductor and output capacitors All PGND connections — the input capacitors, low-side MOSFETs, output capacitors, and the PGND pin of the SC419.  An inner layer ground plane is recommended.  Each component should have a good, low impedance connection to the ground plane.  Place vias to the PGND plane directly near the component pins. Use short wide traces for the pin connections from the SC419 (LX, DH, DL and BST). Do not route these traces near the sensitive analog signals (FB, TON, VOUT ). • • • • • • • • • • • Grounding for PGND and AGND Power Components Low-noise Analog Circuits Bypass capacitors Low-Noise Analog Circuits Low-noise analog circuits are sensitive circuits that are referenced to AGND. Due to their high impedance and sensitivity to noise, it is important that these circuits be kept away from the switching signals. • Grounding A ground plane layer for PGND is recommended to minimize the effects of switching noise, resistive losses, and to maximize heat removal from the power components. A separate ground plane or island should be used for AGND and all associated components. The AGND island should avoid overlapping the switching signals on other layers (DH/DL/BST/LX). • Use a ground plane or solid copper area for AGND. Place all components connected to AGND above this area.  Use short direct traces for the AGND connections to all components.  Place vias to the AGND plane directly near the component pins. Proper routing of the VOUT sense trace is essential since it feeds into the FB resistor divider. Noise on the FB waveform will cause instability and multiple pulsing. 20 SC419 Applications Information (continued) Connect the VOUT sense trace directly to the output capacitor or a ceramic bypass capacitor.  Route this trace over to the VOUT pin, carefully avoiding all switching nets and power components.  Route this trace in a quiet layer if possible.  Route this trace away from the switching traces and components, even if the trace is longer. Avoid shorter trace routing through the power switching area.  If a bypass capacitor is used at the IC side of the trace, it should be placed near the FB resistor divider. All components connected to the FB pin must be located near the pin. The FB traces should be kept small and not routed near any noisy switching connections or power components. Place the RILIM resistor near the IC. For an accurate ILIM current sense connection, route the RILIM trace directly to the drain of the low-side MOSFET (LX). Use an inner routing layer if needed. Place the RTON resistor near the TON pin. Route this to the TON trace using a short trace and avoid all switching signals.  • • • Bypass Capacitors The device requires bypass capacitors for the following pins. • • • • VDDA pin with respect to AGND. This 100nF minimum capacitor must be placed and routed close to the IC pins, on the same layer as the IC. VDDP with respect to PGND. This 1μF minimum capacitor must be placed and routed close to the IC pins and on the same layer as the IC. BST pin with respect to LX. This 100nF minimum capacitor must be placed near the IC, on either side of the PCB. Use short traces for the routing between the capacitor and the IC. V IN pin with respect to AGND. T his 100nF minimum capacitor must be placed and routed close to the IC pins. This capacitor provides noise filtering for the input to the internal ontime circuit. 21 SC419 Outline Drawing — MLPQ-UT20 3x3 A D B DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b D D1 E E1 e L N aaa bbb .020 .000 (.006) .006 .008 .010 .114 .118 .122 .061 .067 .071 .114 .118 .122 .061 .067 .071 .016 BSC .012 .016 .020 20 .003 .004 .024 .002 0.50 0.00 (0.1524) 0.15 0.20 0.25 2.90 3.00 3.10 1.55 1.70 1.80 2.90 3.00 3.10 1.55 1.70 1.80 0.40 BSC 0.30 0.40 0.50 20 0.08 0.10 0.60 0.05 PIN 1 INDICATOR (LASER MARK) E A2 A aaa C A1 e LxN E/2 E1 2 1 N C D1 SEATING PLANE D/2 bxN bbb NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES ). CAB 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS . 3. DAP is 1.90 x 190mm. 22 SC419 Land Pattern — MLPQ-UT20 3x3 H R DIM Z C G H K P R X Y Z DIMENSIONS INCHES (.114) .083 .067 .067 .016 .004 .008 .031 .146 MILLIMETERS (2.90) 2.10 1.70 1.70 0.40 0.10 0.20 0.80 3.70 (C ) K G Y X P NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 3. 23 SC419 © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. 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