SC4524AEVB

SC4524A 28V 2A Step-Down Switching Regulator POWER MANAGEMENT Features            Description The SC4524A is a constant frequency peak current-mode step-down switching regulator capable of producing 2A output current from an input ranging from 3V to 28V. The switching frequency of the SC4524A is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4524A is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4524A achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4524A is available in SOIC-8 EDP package. Wide input range: 3V to 28V 2A Output Current 200kHz to 2MHz Programmable Frequency Precision V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications       XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs Typical Application Circuit 10V – 28V C4 2.2mF D1 1N4148 C1 0.1mF L1 8.2mH R4 42.2k SS270 REV 4 Efficiency V 90 85 80 5V/2A OUT IN IN BST SW Efficiency (%) 75 70 65 60 55 50 45 40 0 VIN = 12V VIN = 24V SS/EN SC4524A FB COMP C7 10nF R7 28.0k ROSC GND D2 20BQ030 R6 10.5k C2 22mF C8 10pF R5 18.2k C5 2.2nF L1: Coiltronics DR73-8R2 C2: Murata GRM31CR60J226K C4: Murata GRM31CR71H225K 0.5 1 1.5 2 Load Current (A) Figure 1. 1MHz 10V-28V to 5V/2A Step-down Converter June 26, 2008  Fig.1 Efficiency of the 1MHz 10V-28V to 5V/2A Step-Do SC4524A Pin Configuration Ordering Information Device SC4524ASETRT()(2) SW IN ROSC GND 1 2 3 4 9 8 7 6 5 BST FB COMP SS/EN Package SOIC-8 EDP Evaluation Board SC4524AEVB Notes: () Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E900) 2 SC4524A Absolute Maximum Ratings VIN Supply Voltage ……………………………… -0.3 to 32V BST Voltage ……………………………………………… 42V BST Voltage above SW …………………………………… 36V SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to VIN SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (0ns Duration)……… -2.5V to VIN +.5V Peak IR Reflow Temperature …………………………. (2) Thermal Information Junction to Ambient () ……………………………… 36°C/W Junction to Case () ………………………………… 5.5°C/W Maximum Junction Temperature……………………… 50°C Storage Temperature ………………………… -65 to +50°C Lead Temperature (Soldering) 0 sec ………………… 300°C Recommended Operating Conditions Input Voltage Range ……………………………… 3V to 28V Maximum Output Current ……………………………… 2A Operating Ambient Temperature …………… -40 to +05°C Operating Junction Temperature …………… -40 to +25°C 260°C ESD Protection Level ………………………………… 2000V Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES() Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. (2) Tested according to JEDEC standard JESD22-A4-B. Electrical Characteristics Unless otherwise noted, VIN = 2V, VBST = 5V, VSS = 2.2V, -40°C < TJ < 25°C, ROSC = 2.kΩ. Parameter Input Supply Input Voltage Range VIN Start Voltage VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown Conditions Min 3 Typ Max 28 Units V V mV VIN Rising 2.70 2.82 225 2.95 VCOMP = 0 (Not Switching) VSS/EN = 0, VIN = 2V 2 40 2.6 50 mA µA Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Pin to Switch Current Gain COMP Maximum Voltage COMP Source Current COMP Sink Current VIN = 3V to 28V VFB = V, VCOMP = 0.8V 0.980 .000 0.005 -70 280 60 8 -340 .020 V %/V nA µΩ- dB A/V V µA VFB = 0.9V VFB = 0.8V, VCOMP = 0.8V VFB = .2V, VCOMP = 0.8V (Note ) ISW = -2.6A 2.6 2.4 7 25 Internal Power Switch Switch Current Limit Switch Saturation Voltage 3.3 250 4.3 400 A mV 3 SC4524A Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 2V, VBST = 5V, VSS = 2.2V, -40°C < TJ < 25°C, ROSC = 2.kΩ. Parameter Minimum Switch On-time Minimum Switch Off-time Switch Leakage Current Minimum Bootstrap Voltage BST Pin Current Conditions Min Typ 35 00 Max Units ns ns 0 ISW = -2.6A ISW = -2.6A .8 60 2.3 95 µA V mA Oscillator Switching Frequency ROSC = 2.kΩ ROSC = 93.kΩ ROSC = 2.kΩ, VFB = 0 ROSC = 93.kΩ, VFB = 0 .04 230 0 50 .3 300 230 00 .56 370 350 70 MHz kHz kHz Foldback Frequency Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current Soft-start Discharging Current Hiccup Arming SS/EN Voltage Hiccup SS/EN Overload Threshold Hiccup Retry SS/EN Voltage 0.2 0.3 .3 .7 .2 2.0 .5 2.8 0.4 .3 V V µA µA V V .2 V VFB = 0 V VSS/EN = 0 V VSS/EN = .5 V VSS/EN Rising VSS/EN Falling VSS/EN Falling .0 2.5 .9 0.6 .0 Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note : Switch current limit does not vary with duty cycle. 65 0 °C °C 4 SC4524A Pin Descriptions SO-8  2 3 4 Pin Name SW IN ROSC GND Pin Function Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. An external resistor from this pin to ground sets the oscillator frequency. Ground pin Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. 5 SS/EN 6 7 8 9 COMP FB BST Exposed Pad 5 SC4524A Block Diagram Fig.2 IN COMP 6 SLOPE COMP 2 + + EA + S + + ISEN 6.1mW OC + ILIM 20mV BST FB 7 V1 + PWM FREQUENCY FOLDBACK 8 S R CLK Q POWER TRANSISTOR ROSC 3 OSCILLATOR R R SS/EN 5 OVERLOAD A1 + - 1.23V 1 SW PWM 1 GND 4 1V 1.9V FAULT REFERENCE & THERMAL SHUTDOWN SOFT-START AND OVERLOAD HICCUP CONTROL Fig.3 Figure 2. SC4524A Block Diagram 1.9V IC 2mA B4 + B1 S Q R OVERLOAD SS/EN 1V/2.15V B2 FAULT ID 3.5mA _ Q S R OC PWM B3 Figure 3. Soft-start and Overload Hiccup Control Circuit 6 Curve 2 SC4524A/B Curve 3 SC4524A SS270 REV 6-7 SC4524A Typical Characteristics Efficiency V O=5V V O=3.3V V O=2.5V 90 85 80 75 70 65 60 55 50 40 0 SS270 REV 6-7 0.5 90 85 80 75 70 65 60 55 50 40 Efficiency Feedback Voltage vs Temperature 1.02 VIN = 12V 1.01 1.00 0.99 0.98 0.97 V O=5V V O=3.3V Efficiency (%) Efficiency (%) V O=1.5V Curve 5 45 1MHz, VIN =12V D2 =20BQ030 Curve 6 45 1.5 2 0 0.5 SS270 REV 6-7 1MHz, VIN =24V D2 =20BQ030 1 VFB (V) V O=2.5V 1 1.5 2 -50 -25 0 25 50 75 o 100 125 Load Current (A) Load Current (A) Temperature ( C) 1000 Frequency Setting Resistor vs Frequency VIN = 12V Frequency vs Temperature 1.2 ROSC=93.1k Foldback Frequency vs VFB 1.25 1 ROSC=93.1k 1.1 100 Normalized Frequency Normalized Frequency ROSC (k ) 0.75 0.5 0.25 ROSC=12.1k 1.0 ROSC=12.1k 10 Curve 8 1 0 0.5 1 1.5 2 2.5 0.9 Curve 9 -50 -25 0 25 50 75 100 125 Temperature (o C) TA = 25oC 0.8 0 0.0 0.2 0.4 0.6 0.8 1.0 Frequency (MHz) SS270 REV 6-7 SS270 REV 6-7 VFB (V) SS270 REV 6-7 300 250 200 150 100 50 0.0 Switch Saturation Voltage v s Switch Current Switch Current Limit vs Temperature 4.5 100.0 BST Pin Current vs Switch Current VIN = 12V -40oC 125oC 25oC 3.5 BST Pin Current (mA) Current Limit (A) 4.0 75.0 VBST = 15V VCESAT (mV) 50.0 -40oC 125oC 3.0 25.0 2.5 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125 Switch Current (A) Temperature (o C) 0.0 0 0.5 1 1.5 2 2.5 3 Switch Current (A) 7 Curve 11 SS270 REV 6-7 Curve 12 SS270 REV 6-7 SC4524A Typical Characteristics (Cont.) SS270 REV 6-7 VIN T hresholds vs Temperature 3.0 2.9 Start 2.5 2.0 VIN Supply Current vs Soft-Start Voltage 125oC -40oC 100 80 VIN Shutdown Current vs VIN VSS = 0 VIN Threshold (V) Current (mA) Current (uA) 2.8 2.7 2.6 1.5 1.0 0.5 0.0 60 -40oC 40 20 0 125oC Curve 14 2.5 2.4 -50 -25 0 UVLO Curve 15 0 0.5 1 VSS (V) 1.5 2 SS270 REV 6-7 25 50 o 75 100 125 0 5 10 15 VIN (V) 20 25 30 Temperature ( C) SS270 REV 6-7 SS270 REV 6-7 VIN Quiescent Current vs VIN 2.5 2.0 125oC -40oC 0.40 SS Shutdown Threshold vs Temperature Soft-Start Charging Current vs Soft-Start Voltage 0.0 -0.5 SS Threshold (V) 0.35 Current (mA) Current (uA) 1.5 1.0 0.5 0.0 0 5 10 15 VIN (V) 20 25 30 -1.0 -1.5 -2.0 -2.5 125oC 0.30 -40oC 0.25 VCOMP = 0 0.20 -50 -25 0 25 50 o -3.0 75 100 125 0 0.5 1 VSS (V) 1.5 2 Temperature ( C) 8 SC4524A Applications Information Operation The SC4524A is a constant-frequency, peak currentmode, step-down switching regulator with an integrated 28V, 2.6A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 6.mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 20mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C and the diode D in Figure ) generates such a voltage at the BST pin for driving the power transistor. Shutdown and Soft-Start The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4524A is summarized in Table . Table 1 Table 1 When the SS/EN pin is released, the soft-start capacitor is charged with an internal .6µA current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, the internal bias circuit of the SC4524A turns on and the SC4524A draws 2mA from VIN. The .6µA charging current turns off and the 2µA current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision V reference and the other non-inverting input is tied to the output of the amplifier A. Amplifier A produces an output V = 2(VSS/EN -.23V). V is zero and COMP is forced low when VSS/EN is below .23V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above .23V. Once VSS/EN exceeds .23V, COMP is released. The regulator starts to switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V during start up. VSS/EN must be at least .83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4524A. Table 2: Fault conditions and protections Cycle-by-cycle limit at Over current Fault Protective Action frequency programmed Cycle-by-cycle limit at limit with Cycle-by-cycle Condition Condition Fault Protective Action IL>ILimit, V FB>0.8V Condition Condition Table 1: SS/EN operation modes Mode Supply Current Shutdown 18uA @ 5Vin Mode switching Supply Current Not 2mA Shutdown 18uA @ 5Vin Switching & hiccup disabled Load dependent Not switching hiccup armed 2mA Switching & Load dependent programmed frequency frequency foldback Cycle-by-cycle limit with retry VSS/EN Falling Persistent over current Shutdown, then Over current IL>ILimit, V FBILimit, V FB>0.8V FBILimit, V SS/EN 2.1V Switching & hiccup disabled Switching & hiccup armed Pulling the SS/EN pin below 0.2V shuts off the regulator and reduces the input supply current to 8µA (VIN = 5V). As summarized in Table , overload shutdown is disabled during soft-start (VSS/EN 200 190 180 170 IO 4 ⋅ DVIN ⋅ FSW Minimum On Time vs Temperature VO = 1.5V 1MHz TON(MIN) (ns) Setting the Output Voltage The regulator output voltage is set with an external resistive divider (Figure ) with its center tap tied to the FB pin. For a given R6 value, R4 can be found by 160 150 140 130 120 V R4 = R6  O −       .0 V   VFB   110 AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   CO O 100  CA S -50 -25 0 25 50 75 100 125 O Temperature ( C) () VO + VD Setting the Switching Frequency D= VIN + VD − VCESAT The switching frequency of the SC4524A is set with an external resistor from the ROSC pin to ground. ( V + VD ) ⋅ ( − D) DIL On O Minimum = Time Consideration FSW ⋅ L  The operating duty cycle of a non-synchronous step( V + V ) ⋅ ( − D) L = O D 20 % ⋅ IO ⋅ FSW   .0  AC = − 20 ⋅ log ⋅ ⋅   = 5 −3 3 −6 3 .3  2 π ⋅ 80 ⋅ 0 ⋅ 22 ⋅ 0  28 ⋅ 6 .  ⋅ 0 Figure 4. Variation of Minimum On Time with Ambient Temperature 5 . 9 0 20 R7 = = 22 . 3 k 0 . 28 ⋅ 0 −3 To allow for transient headroom, the minimum operating switch on time should be at least 20% to 30% higher than  C5 = = 0 . 45 nF 3 the worst-case minimum0 3time. 2 π ⋅ 6 ⋅ 0 ⋅ 22 .  ⋅ on C8 =  = 2pF 2 π⋅ 600 ⋅ 0 3 ⋅ 22 .  ⋅ 0 3 0 L = O D 20 % ⋅ IO ⋅ FS W SW SC4524A IRMS _ CIN = I O ⋅ D ⋅ ( − D) Vo = Vc Applications Information (Cont.) Minimum Off Time Limitation The PWM latch in Figure 2 is reset every cycle by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. The measured minimum off time is 00ns typically. If the required duty cycle is higher than the attainable maximum, then the output voltage will not V  be able toRreachOits−set value in continuous-conduction R4 = 6     .0 V  mode. Inductor Selection D VO + V D= VIN + VD − VCESAT The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is     DV = DIL ⋅  ESR + The inputOcapacitance must also be high enough to keep  8 ⋅ FSW ⋅ C O   within specification. This is important  input ripple voltage in reducing the conductive EMI from the regulator. The input capacitance can be estimated from GPWM R7 = AC = ( V V V ) ⋅ ( − D) + D R R 4IL== 6 O O D−    FV   . 0SW ⋅ L  (3) where FSW is the switching frequency and L is the ( + +V inductance. VO VOVD ) ⋅D( − D) L == D VIN 20VD ⋅−OVCESAT + % I ⋅ FSW An inductor ripple current between 20% to 50% of the maximum load current gives a good compromise among IRMS CINV= + V size. − D) ( D) O⋅ efficiency,_ cost Iand )D (⋅−Re-arranging Equation (3) and ( D⋅ DIL = O inductor ripple current, the inductor is assuming 35% F ⋅ L SW  given by   ( V + V ) ⋅ ( − D)   L  O = DIL ⋅  ESR + DV = O  D (4) 35V ⋅ IO ⋅ FSW ⋅ FSW ⋅ C O  % 8   O −  R4 = R6   If the input voltage varies over a wide range, then choose   .0 V  L based on the nominal input voltage. Always verify IRMS = I ⋅ D ⋅ ( − D) converter _ CIN V O+ Vat the input voltage extremes. operation OI D D= C IN > + V O V VIN ⋅ DV − ⋅ F CESAT 4D The peak current IN SW SC4524A power transistor is at limit of least 2.6A. The maximum deliverable load current for the    DV = DIL ⋅  ESR + SC4524AOis 2.6A minus one half of the inductor ripple  ( V +VD ) ⋅ ( 8 D)SW ⋅ C O  − ⋅F current.IL = O D FSW ⋅ L  Input Decoupling Capacitor ( V + VD ) ⋅ ( − D) L  = O IO C IN > 20 % ⋅ I should be chosen to handle the RMS The input capacitorO FFSW 4 ⋅ DVIN ⋅ ⋅ SW ripple current of a buck converter. This value is given by IRMS _ CIN = I O ⋅ D ⋅ ( − D) (5) I C R  VO (6) C5 = R 4IN=> 6  O −    4⋅ .VIN ⋅ FSW D0 V  AC =  V  where DV logthe  ⋅ AC = − 20 ⋅IN is  allowable input ripple voltage. ⋅ FB   G R 2 πF C C8 = VO  CA S CO  VO + VD  D= Multi-layerVceramic capacitors, which have very low ESR IN + VD − VCESAT    (a few mW) and can easily handle high RMS ripple current,. 0  AC = − 20 ⋅ log ⋅ ⋅ ==  R 5 −3 3 −6 are the ideal choicefor input π ⋅ 80 ⋅ 0 A ⋅ single 4.7µF. 3  7 3 28 ⋅ 6 . ⋅ 0 2 filtering. 22 ⋅ 0 X5R ceramic( V + V ) ⋅ ( − D) capacitor is adequate for 500kHz or higher O D DIL frequency applications, and 0µF is adequate C 5 = switching = 5 . 9 FSW ⋅ L  for 200kHz to 500kHz switching frequency. For high 0 20  VFB  R7 = =22 . 3 k  AColtage applications, a small ceramic  − 20 ⋅ log v = 0 . 28 ⋅ 0 −3 (µF or 2.2µF) can be  G R ⋅ 2 πF C ⋅ V  ( VO +CAwith a low ESR electrolytic capacitor to C 8 = C O  VD )S⋅ ( − D) O placedLin = parallel   20 % ⋅ I and bulk capacitance Cs5atisfy both the3ESRO ⋅ FSW 3 = 0 . 45 nF requirements. = 2 π ⋅ 6 ⋅ 0 ⋅ 22 . ⋅ 0    .0  AC = − 20 ⋅ log ⋅ ⋅   = 5 28 ⋅ 6 .  ⋅ 0 − 3 2 π ⋅ 80 ⋅ 0 3 ⋅ 22 ⋅ 0 −6 3 . 3  Vo  Output Capacitor = C8 = I = 2pF Vc 2 πRMS _ CIN 0I O ⋅ 22 .⋅ (0D) ⋅ 600 ⋅ = 3 ⋅ D  ⋅ − 3 The output .9ripple voltage DVO of a buck converter can be 5 0 20 expressed as = 22 . 3 k R7 = G −3 Vo 0 . 28 ⋅ 0PWM ( + s R ESR C O ) GPWM =   2 Vc ( DVO/ = D)I(L⋅ +ESR + Q + s 2 / ωn )  + s ωp   s / ωn (7)  8 ⋅3FSW0⋅.C O nF C5 = = 45   3 2 π ⋅ 6 ⋅ 0 ⋅ 22 .  ⋅ 0 where CO is the output capacitance. R7 = R     VFB  GPWM − 20 ⋅ log, 3 ωZ = , C8 = ≈ =,  AC = G ⋅ R  ⋅ ωp ≈ 3R C⋅ 2pF R as 2 the S⋅ G R ripple current 600 0 ⋅  ⋅ 0 Since π⋅CA inductor22 .2 πFC C O OVO DIL increasesESR C OD  CAO S  I C IN decreases >(Equation (3)), the output ripple voltage is C 5 = AC 4 ⋅ DV ⋅ F therefore the  IN SW VIN is at its maximum. highest when 0 20   .0  R 7C = − 20 ⋅ log ( + s R ESR C O ) ⋅ GPWM Vo A ⋅  = 5 −3 3 −6 = gm 3 .3 28 ⋅ 6 .  ⋅ 0 2 π ⋅280 ⋅ 0 ⋅ 22 ⋅ 0 Vc 0µF+to / ωp)( + s ceramic scapacitor is found adequate C 8 = ( s 47µF X5R / ωn Q + 2 / ωn ) A  or Cf5 =output filtering in most applications. Ripple current 2 FZ 5 .9 R in theπ0 20 7 capacitor is not a concern because the output R   Ri7 = GPWM ≈  current= of a3 kωp ≈ converter directly=feeds C ,, , ωZ nductor ⋅ 0 −,3 22 . buck 0 . 28 ⋅ R S CO R ESR C OO Cr8 = GCAin very low rippleRcurrent. Avoid using Z5U esulting R 2 πFP 7  Cand Y5VC ceramic capacitors for output filtering because = 0 . 45 nF A 5= 3 2π ⋅ 0 3 ⋅ 22 .  ⋅ have 0 206 ⋅of capacitors0 high temperature and high Rt7hese types = gm voltage coefficients.  C8 = = 2pF 2 π⋅ 600 ⋅ 0 3 ⋅ 22 .  ⋅ 0 3  CFreewheeling Diode 5= 2 πFZ R 7 G  + s R diodes Vo of Schottky (barrierESR C O ) as freewheeling rectifiers Use  PWM Cr8 = ( + sdiode(reverse Q + s 2 / ω2input current spikes, = educes Vc 2 πF /R p ) + s / ωn recovery n ) ω P 7 easing high-side current sensing in the SC4524A. These GPWM ≈ R , GCA ⋅ R S ωp ≈  , RCO ωZ =   , R ESR C O  DV = DI ⋅  ESR +    Fig.5 Applications Information (Cont.) diodes should have an average forward current rating at least 2A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diode should be placed close to the SW pin of the SC4524A to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B230A (Diodes Inc.), SS3, SS23 (Vishay), CMSH-40M, CMSH40ML and CMSH2-40M (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4524A on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor The typical minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about .96V at room temperature. The BST-SW voltage is supplied by a bootstrap D1 circuit powered from either the input or the output of the BST C1 converter (Figure 6). To maximize efficiency, tie the bootstrap diode toVIN the converter output if VO>2.5V. VOUT SW IN Since the bootstrap supply current is proportional to the SC4524A D converter load current, using a lower voltage2 to power GND the bootstrap circuit reduces driving loss and improves efficiency. (a) D3 SC4524A SS270 REV 6-7 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -50 Minimum Bootstrap Voltage vs Temperature Voltage (V) ISW = -2.6A Fig.6 -25 0 25 50 75 100 125 Temperature (o C) Figure 5. Typical Minimum Bootstrap Voltage required to Saturate Transistor (ISW= -2.6A). D1 D3 BST VIN C1 SW VOUT VIN Fig.6 IN SC4524A GND D2 (a) D1 BST VIN C1 SW VOUT IN SC4524A GND D 2 (b) For the bootstrap circuit, a fast switching PN diode (such as N448 or N94) and a small (0.µF – 0.47µF) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D. When bootstrapping from high input voltages (>20V), reduce the maximum BST voltage by connecting a Zener diode (D3) in series with D. Figure 6. Methods of Bootstrapping the SC4524A Loop Compensation The goal of compensation is to shape the frequency response of the converter so as to achieve high DC accuracy and fast transient response while maintaining loop stability. 2 SC4524A Applications Information (Cont.) CONTROLLER AND SCHOTTKY DIODE Io CA Rs REF Including the voltage divider (R4 and R6), the control to feedback transfer function is found and plotted in Figure 8 as the converter gain. SW L1 Vo + EA Vc Vramp FB - PWM MODULATOR COMP C5 R7 C8 Co R4 Resr R6 Figure 7. Block diagram of controlFig.8 loops  VFB      AC diagram in  ⋅ VFB  The block= − 20 ⋅ logFigure 7⋅shows the control loops of a AC = − 20 ⋅ log G R ⋅ 2 πF C ⋅ V  CA S CO O  G CAR S 2 πFC C O innerloop (current VO   buck converter with the SC4524A. The loop) consists of a current sensing resistor (Rs=6.mW)      AC = − amplifier ⋅  VFB  and a current 20 ⋅ log (CA) with gain (GCA=28). The outer −6 AC = − 20 ⋅ log −3 ⋅ 3 2 π ⋅ 80 ⋅ 0 3 ⋅ 22 0  28 ⋅ 6 ⋅ an 2 π ⋅ 80 ⋅ 0 3 ⋅ 22 ⋅ a −6  loop (voltage loop) consistsof0 − error amplifier (EA),⋅ 0 ⋅  28 ⋅ 6 ..  ⋅ 0  VO  PWM modulator, and a LC filter.  0 Since the = 0 ⋅ loopis internally closed, the remaining current  . 0 ⋅ R 7 = −6 FB  −3 = 5 ..9 dB 22 3 k V 3 R 7 3 . = 22 3 k  2 π 0 .. 28 compensation is to design the voltage log⋅ 80t⋅ 0⋅for22 ⋅ 028 ⋅ 033 ⋅ ask ⋅ the0loop⋅ 0 −   G CAR S 2 πFC C O (CV,OR, and C ).  compensator 5 7  8 C5 = = 0 45 nF C5 = = 0 ..45 nF 3 2 π ⋅ 6 ⋅ 0 ⋅ 22  ⋅ 0 3 ⋅ 2 π ⋅ 6 ⋅ 0 3  22 .. ⋅ 0 3  . 0   = F output log For a converter with switching frequency 5 .,9 dB ⋅ ⋅   SW 3  3 .2pF 3  28 i⋅ 6 .  ⋅ 0 −= L 2 π ⋅ 80 ⋅ 03 ⋅ 22 ⋅ 0 −6 = ndloading R, the nductance , output capacitance CO = 2pF a C8 = C8 3 3 3 2 π⋅ 600 ⋅ 0 3 ⋅ transfer function in Figure 7 is control (VC) 2 π⋅output (VO)⋅ 22 .. ⋅ 0 to 600 ⋅ 0 22  ⋅ 0 0 . 45 nF given by: 5 . 9 = 22 . 3 k V G ( + s R ESR C O ) GPWM ( + s R ESR C O ) o Vo = 0 −3 pF = 2 = ( + s / ωPWM + s / ω Q + s 2 / ω2 ) 2 2 Vc p )( n n Vc ( + s / ωp )( + s / ωn Q + s / ωn )  = 0 . 45 nF 6 ⋅ 0 3 ⋅This ⋅ 0 3 function has a finite DC gain 22 . transfer R   GPWM ≈ R ωp ≈  GPWM 3≈= 2pF ,, ωp ≈ R C ,, 2 G ⋅R RCO / ⋅ 2) 00 ω0 3 ⋅ 22 .  ⋅ 0 GCA ⋅ R S n CA S O 20 5 . 9 5 . 9 20 20 Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ, and a high frequency pole at FP. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). The high frequency pole nulls the ESR zero and attenuates high frequency noise. 60  .0  ⋅  . 0  = 5 9 dB  ⋅ 3 . 3  = 5 ..9 dB  3 .3  30 GAIN (dB) Fz1 Fp1 CO MP EN SA TO 0 Fp CO NV ER T ER RG AIN Fc GA IN LO OP G AIN -30 Fz -60 1K Fsw/2 10K 100K FREQUENCY (Hz) 1M 10M (8) Figure 8. Bode plots for voltage loop design Therefore, the procedure of the voltage loop design for  the SC4524A can be summarized as: ωZ =  ωZ = R C ,, ESR O R ESR C O () Plot the converter gain, i.e. control to feedback transfer function. (2) Select the open loop crossover frequency, FC, between 0% and 20% of the switching frequency. At FC, find the required compensator gain, AC. In typical applications with ceramic output capacitors, the ESR zero is neglected and the required compensator gain at FC can be estimated by A an ESR zero FZ aCt AC 20 0 20 0  R=  PWM ( + s R ESR7C= ) R7 = g G, ωZ O gm , 2m 2 /C Op )( + s / ωn Q + sR ESR CnO) ω /ω   C5 = C 5 = low-frequency pole FP at a dominant 2 πF R Z 7 2 πFZ R 7   , ωp ≈ , ωZ = ,  C 8 = R C O = ⋅RS R ESR C O C 8 2 πF R P 7 2 πFP R 7 and double poles at half the switching frequency. V R4 = R6  O −       .0 V   VFB   AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   CO O  CA S (9)    .0 3 AC = − 20 ⋅ log ⋅ ⋅  −3 3 −6 3. 2 π ⋅ 80 ⋅ 0 ⋅ 22 ⋅ 0  28 ⋅ 6 .  ⋅ 0 C5 = C8 =  2 π ⋅ 6 ⋅ 0 ⋅ 22 .  ⋅ 0 3 3 = 0 . 45 nF SC4524A  = 2pF 2 π⋅ 600 ⋅ 0 3 ⋅ 22 .  ⋅ 0 3 Applications Information (Cont.) GPWM ( + s R ESR C O ) Vo (3) Place = compensator zero, FZ,2 between 0% and the Thermal Considerations 2 Vc ( + s / ωp )( + s / ωn Q + s / ωn ) 20% of the crossover frequency, FC. (4) Use the compensator pole, FP, to cancel the ESR zero, For the power transistor inside the SC4524A, the FZ. R   conduction loss PC, the switching loss PSW, and bootstrap GPWM ≈ , ω≈ , ωZ = , (5) Then, the parameters of the p R C compensation network Circuit PTOTAL BST,PCan PSWestimated as follows: loss P = c + be + PBST + PQ GCA ⋅ R S R ESR c O O can be calculated by 0 20 R7 = gm AC PC = D ⋅ VCESAT ⋅ IO PSW =  ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW 2 IO 40 PQ = VIN ⋅ 2mA  C5 = 2 πFZ R 7  C8 = 2 πFP R 7 where gm=0.28mA/V is the EA gain of the SC4524A. Example: Determine the voltage compensator for an 800kHz, 2V to 3.3V/2A converter with 22uF ceramic output capacitor. Choose a loop gain crossover frequency of 80kHz, and place voltage compensator zero  and pole  FZ=6kHz  VFB at  AC F ), 20 ⋅ log = − and F  =600kHz. From ⋅Equation (9), the ⋅ (20% of C   V  AC = − 20 ⋅ log ⋅ P G CAR SFB 2 πFC C O VO  F C ⋅ V   G R 2π required compensatorCgain atFC is O O  CA S (0) PBST = D ⋅ VBST ⋅ where P BST is − D) ⋅ V ⋅ I voltage and tS is the equivalent V = ( the BST supply D DO switching time of the NPN transistor (see Table 3). Table  Typical ⋅ I2 ⋅ R DC PIND = (3.. ~  .3 )switching time O Input Voltage 12V 24V 28V Load Current 1A 2A 12.5ns 15.3ns 22ns 25ns 25.3ns 28ns   .0     .0  + AC = −AC ⋅= − 20 ⋅ log − 3 ⋅ 20 log ⋅= P  = 5 . 9 dB PBST +⋅ PQ  = 5 the quiescent current loss is ⋅P   +P In addition, . 9 dB 80 0 3 ⋅TOTAL 3 3C 0 ⋅  28 ⋅ 6 .  ⋅ 0 28 2 π ⋅.  ⋅⋅03− ⋅ 22 2 π −680 .⋅ 0 3 ⋅SW ⋅ 0 − 6 3 . 3  ⋅6 22  Then the compensator parameters are = D ⋅ V PC CESAT ⋅ IO 0 R7 = 5 . 9 20 PQ = VIN ⋅ 2mA () 0 20 The total power loss of the SC4524A is therefore = 22 . 3 k  PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW 0 . 28 ⋅ 0 −3 3 = 0 . 45 nF C5 = 3 2 π ⋅ 6 ⋅ 0 ⋅ 22 .  ⋅ 0 2  PTOTAL = PC + PSW + PBST + PQ (2) C5 =  = 0 . 45 nF C8 = 20 3 6 .⋅ ⋅ 0 3 ⋅ = 2.pF ⋅ 0 3 P = D ⋅ V ⋅ IO π ⋅ ⋅ 22 0 3 22  2 π⋅ 600 ⋅ BST BST 40 The temperature rise⋅ of the SC4524A PQtheVproduct of the is = IN ⋅ 2mA PC = D ⋅ VCESAT IO  C 8 = ( + s R C )3 = 2pF total power dissipation (Equation (2)) and qJA (36oC/W), GPWM Vo 2 π⋅ 600ESR0 2 ⋅ 22 .  ⋅ 0 3 ⋅O = 2 which is the thermal impedance from junction to ambient Vc ( + s / ωp )( + s / ωn Q + s / ωn ) PD = ( − D) ⋅ VD ⋅ IO  Select R7=22.k, C5=0.47nF, and C8=0pF for the design. for thePSW = 2 EDP⋅package. SW SOIC-8 ⋅ t S VIN ⋅ I O ⋅ F R GPWM (+ ,s R ESR C O )Z =  , GPWM ≈ Vo , ωp ≈ ω 2 I P R ESR= ( applications GCA=R S parameters for various 2typical . ~  .3 ) ⋅ IO ⋅ R DCt is not recommended to operate the SC4524A above ⋅ RC C Compensator I PBST = D ⋅ VBST ⋅ O Vc ( + s / ωp )( + O / ωn Q + s IND n )O s / ω2 o 40 are listed in Table 4. A MathCAD program is also available 25 C junction temperature. In the applications with high 0 uR 7 = request for detailed calculation of the compensator pon input voltage and high output current, the switching gm parameters. R   frequency may D) ⋅ VD toObe reduced to meet the thermal PD = ( − need ⋅ I GPWM ≈ , ωp ≈ , ωZ = ,  r C5 = G ⋅R RC R Cequirement. 0 . 28 ⋅ 0 −3 = 22539k .. R7 =  AC 20 2 πFZ R 7 CA S O ESR O C8 =  AC 2 πFP R 7 20 0 PIND = ( . ~  .3 ) ⋅ I2 ⋅ R DC O 4 R7 = gm  2 πF R C5 = SC4524A PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4524A, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. 12 12 V IN VOUT ZL Figure 9. Heavy lines indicate the critical pulse current loop. The inductance of this loop should be minimized. Vin C urre nts in Power Section 5 SC4524A Recommended Component Parameters in Typical Applications Table 4 lists the recommended inductance (L) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/0. Table 4. Recommended inductance (L1) and compensator (R7, C5, C8) Vin(V) Typical Applications Vo(V) Io(A) Fsw(kHz) 1 500 1.5 2 500 500 1 1000 2.5 500 2 1000 500 1 1000 3.3 500 2 1000 500 1 1000 5 500 2 1000 500 1 1000 7.5 500 2 1000 500 1 1000 10 500 2 1000 1 1.5 300 2 1 2.5 2 500 1 3.3 2 500 1 1000 5 500 2 1000 500 1 1000 7.5 500 2 1000 500 1 1000 10 500 2 1000 C2(uF) L1(uH) 8.2 4.7 15 6.8 6.8 3.3 15 8.2 8.2 4.7 15 10 8.2 4.7 15 8.2 8.2 4.7 10 4.7 4.7 2.2 15 8.2 15 8.2 22 10 22 15 15 6.8 33 15 15 8.2 33 22 15 10 Recommended Parameters R7(k) C5(nF) C8(pF) 7.15 2.2 7.15 2.2 11.3 1 20 0.68 11.3 1 20 0.47 15 0.82 30.9 0.47 15 0.82 30.9 0.47 23.7 0.68 41.2 0.47 23.7 0.68 45.3 0.47 35.7 0.68 63.4 0.47 35.7 0.68 63.4 0.47 42.2 0.68 84.5 0.47 10 42.2 0.68 84.5 0.47 4.32 12.4 15 20 43.2 20 43.2 35.7 63.4 35.7 63.4 43.2 84.5 43.2 84.5 2.2 1.0 0.82 0.68 0.47 0.68 0.47 0.68 0.47 0.68 0.47 0.68 0.47 0.68 0.47 SC4524A Compensator Parameters 12 22 24 6 SC4524A Typical Application Schematics D3 D1 V IN 24V C4 4.7mF 18V Zener 1N4148 IN BST SW SS/EN C1 0.33mF L1 8.2mH R4 33.2k OUT 1.5V/2A SC4524A FB COMP C7 10nF R7 4.32k ROSC GND D2 20BQ030 R6 66.5k C2 22mF C8 22pF R5 90.9k C5 2.2nF L1: Coiltronics DR73-8R2 C2: Murata GRM31CR60J226K C4: Murata GRM32ER71H475K Figure 10. 300kHz 24V to 1.5V/2A Step-down Converter EVB#d: 300kHz 24V to 1.5V/2A Step-Down Converter V IN 10V – 26V D1 1N4148 C1 0.1mF L1 8.2mH R4 3.65k Fig.10 C4 4.7mF IN SS/EN BST SW OUT 3.3V/2A SC4524A FB COMP C7 10nF R7 13.0k ROSC GND D2 SS23 R6 1.58k C2 22mF C8 22pF R5 23.7k C5 2.2nF L1: Coiltronics DR73-8R2 C2: Murata GRM31CR60J226M C4: Murata GRM32ER71H475K Figure 11. 800kHz 10V-26V to 3.3V/2A Step-down Converter 800kHz 10V-26V to 3.3V/2A Step-Down Converter 7 Fig.12(b) SS Typical Performance Characteristics SS270 REV 6-7 SC4524A (For A 24V to 5V/2A Step-down Converter with 1MHz Switching Frequency) Load Characteristic 6 5 Output Voltage (V) 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 24V Input (10V/DIV) 5V Output (2V/DIV) SS Voltage (1V/DIV) R Load Current (A) Figure 12(a). Load Characteristic Fig.12(d) OCP 10ms/DIV Figure 12(b). VIN Start up Transient (IO=2A) 5V Output Short (5V/DIV) 5V Output Response (500mV/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV 20ms/DIV Figure 12(c). Load Transient Response (IO= 0.3A to 2A) Figure 12(d). Output Short Circuit (Hiccup) 8 SC4524A SO-8 EDP2 Outline Outline Drawing - SOIC-8 EDP A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A A1 C A-B D e D DIM A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .053 .069 .000 .005 .049 .065 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 1.35 1.75 0.00 0.13 1.25 1.65 0.31 0.51 0.17 0.25 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0° 8° 0.10 0.25 0.20 C bxN bbb F h EXPOSED PAD H H GAGE PLANE 0.25 h c L (L1) 01 SEE DETAIL SIDE VIEW NOTES: 1. A DETAIL A CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION BA. Land Pattern - SOIC-8 EDP SO-8 EDP2 Landing Pattern E D SOLDER MASK DIM (C) F G Z C D E F G P X Y Z DIMENSIONS INCHES MILLIMETERS (.205) .134 .201 .101 .118 .050 .024 .087 .291 (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40 Y THERMAL VIA Ø 0.36mm NOTES: P X 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR F UNCTIONAL PERFORMANCE OF THE DEVICE. Contact Information Semtech Corporation Power Mangement Products Division 200 Flynn Road, Camarillo, CA 9302 Phone: (805) 498-2 Fax: (805) 498-3804 9