SC4524D

SC4524D 18V 2A Step-Down Switching Regulator POWER MANAGEMENT Features            Description The SC4524D is a constant frequency peak current-mode step-down switching regulator capable of producing 2A output current from an input ranging from 3V to 18V. The switching frequency of the SC4524D is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4524D is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4524D achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4524D is available in SOIC-8 EDP package. Wide input range: 3V to 18V 2A Output Current 200kHz to 2MHz Programmable Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications       XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs Typical Application Circuit 10V – 16V C4 2.2 F D1 1N4148 C1 0.33 F L1 6.8 H R4 102k SS270 REV 4 Efficiency V IN 90 85 OUT 5V/2A IN BST SW 80 Efficiency (%) 75 70 65 60 55 50 45 40 VIN = 12V SS/EN SC4524D FB COMP C7 10nF R7 30.1k C5 1nF ROSC GND D2 20BQ030 R6 25.5k C2 22 F C8 10pF R5 15.8k L1: Wurth 744 778 9006 C2: Murata GRM31CR60J226K C4: Murata GRM31CR61E225K 0 0.5 1 1.5 2 Load Current (A) Figure 1. 1MHz 10V-16V to 5V/2A Step-down Converter Dec. 9, 2010 SC4524D Pin Configuration Ordering Information Device SC4524DSETRT(1)(2) SW IN ROSC GND 1 2 3 4 9 8 7 6 5 BST FB COMP SS/EN Package SOIC-8 EDP Evaluation Board SC4524DEVB Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) 2 SC4524D Absolute Maximum Ratings VIN Supply Voltage ……………………………… -0.3 to 24V BST Voltage ……………………………………………… 40V BST Voltage above SW …………………………………… 36V SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to VIN SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Peak IR Reflow Temperature …………………………. (2) Thermal Information Junction to Ambient (1) ……………………………… 36°C/W Junction to Case (1) ………………………………… 5.5°C/W Maximum Junction Temperature……………………… 150°C Storage Temperature ………………………… -65 to +150°C Lead Temperature (Soldering) 10 sec ………………… 300°C Recommended Operating Conditions Input Voltage Range ……………………………… 3V to 18V Maximum Output Current ……………………………… 2A Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C 260°C ESD Protection Level ………………………………… 2000V Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ. Parameter Input Supply Input Voltage Range VIN Start Voltage VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown Conditions Min 3 Typ Max 18 Units V V mV VIN Rising 2.70 2.82 225 2.95 VCOMP = 0 (Not Switching) VSS/EN = 0, VIN = 12V 2 40 2.6 52 mA µA Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Pin to Switch Current Gain COMP Maximum Voltage COMP Source Current COMP Sink Current VIN = 3V to 18V VFB = 1V, VCOMP = 0.8V 0.980 1.000 0.005 -170 300 60 10 -340 1.020 V %/V nA µΩ-1 dB A/V V µA VFB = 0.9V VFB = 0.8V, VCOMP = 0.8V VFB = 1.2V, VCOMP = 0.8V (Note 1) ISW = -2.6A 2.6 2.4 17 25 Internal Power Switch Switch Current Limit Switch Saturation Voltage 3.3 250 4.3 400 A mV 3 SC4524D Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ. Parameter Minimum Switch On-time Minimum Switch Off-time Switch Leakage Current Minimum Bootstrap Voltage BST Pin Current Conditions Min Typ 135 100 Max Units ns ns 10 ISW = -2.6A ISW = -2.6A 1.8 60 2.3 95 µA V mA Oscillator Switching Frequency ROSC = 12.1kΩ ROSC = 73.2kΩ ROSC = 12.1kΩ, VFB = 0 ROSC = 73.2kΩ, VFB = 0 1.04 230 100 35 60 1.3 300 1.56 370 250 90 MHz kHz kHz Foldback Frequency Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current Soft-start Discharging Current Hiccup Arming SS/EN Voltage Hiccup SS/EN Overload Threshold Hiccup Retry SS/EN Voltage 0.2 0.3 1.2 1.9 1.6 2.4 1.5 3.2 0.4 1.4 V V µA µA V V 1.2 V VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V VSS/EN Rising VSS/EN Falling VSS/EN Falling 0.95 2.15 1.9 0.6 1.0 Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: Switch current limit does not vary with duty cycle. 165 10 °C °C 4 SC4524D Pin Descriptions SO-8 1 2 3 4 Pin Name SW IN ROSC GND Pin Function Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. An external resistor from this pin to ground sets the oscillator frequency. Ground pin Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. 5 SS/EN 6 7 8 9 COMP FB BST Exposed Pad 5 SC4524D Block Diagram IN COMP 6 SLOPE COMP 2 + + + EA + OC + ILIM - + ISEN 5.5m 18mV BST FB 7 V1 + PWM FREQUENCY FOLDBACK 8 S R Q POWER TRANSISTOR ROSC 3 OSCILLATOR CLK 1.2V - R R SS/EN 5 1V 1.9V FAULT REFERENCE & THERMAL SHUTDOWN SOFT START AND OVERLOAD HICCUP CONTROL OVERLOAD A1 + 1 SW PWM GND 4 Figure 2. SC4524D Block Diagram 1.9V 2.4 A IC B4 + B1 S Q R OVERLOAD SS/EN 1V/2.15V B2 FAULT ID 3.9 A _ Q S R OC PWM B3 Figure 3. Soft-start and Overload Hiccup Control Circuit 6 (2) SC4524A/B Curve 3 SC4524A/B SC4524D Typical Characteristics Efficiency V O=5V V O=3.3V V O=2.5V SS270 REV 6-7 Efficiency 90 85 80 75 70 65 60 55 50 40 V O=3.3V V O=2.5V V O=1.5V Feedback Voltage vs Temperature 1.02 VIN = 12V 1.01 1.00 0.99 0.98 0.97 -50 -25 0 25 50 75 o 90 85 80 75 70 65 60 55 50 40 0 0.5 Efficiency (%) Efficiency (%) V O=1.5V VO=1.0V Curve 5 45 SS270 REV 6-7 1MHz, VIN =12V D2 =20BQ030 Curve 6 45 1.5 2 SS270 REV 6-7 0 0.5 1MHz, VIN=5V D2 =20BQ030 1 1 1.5 2 VFB (V) Load Current (A) Load Current (A) 100 125 Temperature ( C) SS270 REV 6-7 1000 Frequency Setting Resistor vs Frequency VIN =12V Frequency vs Temperature 1.2 Foldback Frequency vs VFB 1.25 1 0.75 0.5 TA=25oC 0.25 ROSC =12.1k 0 0.00 ROSC =73.2k Normalized Frequency 1.1 ROSC =73.2k 1.0 ROSC =12.1k 100 10 Curve 8 1 0 SS270 REV 6-7 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0.9 Curve 9 -50 -25 0 25 50 75 100 125 Temperature (OC) 0.8 Normalized Frequency ROSC (k ) 0.20 0.40 0.60 0.80 1.00 Frequency (MHz) SS270 REV 6-7 VFB (V) SS270 REV 6-7 300 250 Switch Saturation Voltage v s Switch Current Switch Current Limit vs Temperature 4.5 100.0 BST Pin Current vs Switch Current VIN = 12V 125oC 25oC -40oC 200 150 100 50 0.0 0.5 3.5 BST Pin Current (mA) Current Limit (A) 4.0 75.0 VBST = 15V VCESAT (mV) 50.0 -40oC 125oC 3.0 25.0 1.0 1.5 2.0 2.5 2.5 -50 -25 0 25 50 75 100 125 Temperature (OC) 0.0 0 0.5 1 1.5 2 2.5 3 Switch Current (A) Switch Current (A) 7 Curve 11 SS270 REV 6-7 Curve 12 SS270 REV 6-7 SC4524D Typical Characteristics (Cont.) SS270 REV 6-7 VIN T hresholds vs Temperature 3.0 2.9 Start 2.5 2.0 VIN Supply Current vs Soft-Start Voltage 125oC -40oC 50 40 VIN Shutdown Current vs VIN VSS = 0 -40oC VIN Threshold (V) Current (mA) Current (uA) 2.8 2.7 2.6 1.5 1.0 0.5 0.0 30 20 10 0 125oC Curve 14 2.5 2.4 -50 -25 0 UVLO Curve 15 0 0.5 1 VSS (V) 1.5 2 SS270 REV 6-7 25 50 o 75 100 125 0 2 4 6 8 10 12 14 16 18 Temperature ( C) SS270 REV 6-7 SS270 REV 6-7 VIN (V) VIN Quiescent Current vs VIN 2.5 2.0 125oC o 0.40 SS Shutdown Threshold vs Temperature Soft-Start Charging Current vs Soft-Start Voltage 0.0 -0.5 SS Threshold (V) Current (mA) Current (uA) -40 C 1.5 1.0 0.5 VCOMP = 0 0.0 0 2 4 6 8 10 12 14 16 18 VIN (V) 0.35 -1.0 -1.5 -2.0 -2.5 0.20 -50 -25 0 25 50 o 125oC 0.30 -40oC 0.25 -3.0 75 100 125 0 0.5 1 VSS (V) 1.5 2 Temperature ( C) 8 SC4524D Applications Information Operation The SC4524D is a constant-frequency, peak currentmode, step-down switching regulator with an integrated 18V, 2.6A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 5.5mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. Shutdown and Soft-Start Table 2: Fault conditions and protections The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4524D is summarized in Table 1. Table 1: SS/EN operation modes SS/EN SS/EN 2.15V Mode Shutdown Not switching Switching & hiccup disabled Switching & hiccup armed Supply Current 18uA @ 5Vin 2mA Load dependent When the SS/EN pin is released, the soft-start capacitor is charged with an internal 1.9µA current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, the internal bias circuit of the SC4524D turns on and the SC4524D draws 2mA from VIN. The 1.9µA charging current turns off and the 2.4µA current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision 1V reference and the other non-inverting input is tied to the output of the amplifier A1. Amplifier A1 produces an output V1 = 2(VSS/EN -1.2V). V1 is zero and COMP is forced low when VSS/EN is below 1.2V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above 1.2V. Once VSS/ exceeds 1.2V, COMP is released. The regulator starts to EN switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V1 during start up. VSS/EN must be at least 1.83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4524D. Condition Condition IL>ILimit, V FB>0.8V IL>ILimit, V FB 4 ⋅ DV ⋅ F The peak current IN SW SC4524D power transistor is at limit of   1  DVO = DIL ⋅  ESR +  8 ⋅ FSW ⋅ C O    I R7 = C R  VO (6) C5 = R 4IN=> 6  O − 1   4⋅1 .VIN ⋅ FSW D0 V  AC =  IO V 1 whereC IN > the 1 ⋅ DV log AC = − 20 ⋅IN is  allowable input ripple voltage. ⋅ FB  C5 = C8 = 4⋅ V CARVFSW πFC C O VO  D IN S  GOV+ ⋅ D 2  D= Multi-layerVceramic capacitors, which have very low ESR IN + VD − VCESAT 1 1 1 (a few mW) and can easily handle high RMS ripple current,. 0 C 8 = AC = − 20 ⋅ log ⋅ ⋅ ==  R 15 −3 3 −6 are the ideal choice1for input π ⋅ 80 ⋅ 10 A ⋅ single 4.7µF. 3  7 3 28 ⋅ 6 . ⋅ 10 2 filtering. 22 ⋅ 10 X5R ceramic( V + V ) ⋅ (1 − D) capacitor is adequate for 500kHz or higher D DIL = O switching frequency applications, and 10µF is adequate C 5 = 15 . 9 FSW ⋅ L 1 for 200kHz to 500kHz switching frequency. For high 10 20  VFB  R7 = =122 . 3 k 1 AColtage applications, a small ceramic  − 20 ⋅ log v = 0 . 28 ⋅ 10 −3 (1µF or 2.2µF) can be C =  G R ⋅ 2 πF C ⋅ V  8 C O  placedLin = ( VO +CAwith a low ESR electrolytic capacitor to parallelVD )S⋅ (1 − D) O 1 1 20 % ⋅ I and bulk capacitance Cs5atisfy both the3ESRO ⋅ FSW 3 = 0 . 45 nF requirements. = 2 π ⋅ 16 ⋅ 10 ⋅ 22 .1 ⋅ 10 1 1 1 .0  AC = − 20 ⋅ log ⋅ ⋅   = 15 −3 3 −6 3 . 3  Vo 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10  28 ⋅ 1 Output Capacitor 6 . 1 ⋅ 10 = C8 = I = 12pF Vc 2 πRMS _ CIN 10I O ⋅ 22 .⋅ (110D) ⋅ 600 ⋅ = 3 ⋅ D 1 ⋅ − 3 The output .9ripple voltage DVO of a buck converter can be 15 10 20 expressed as = 22 . 3 k R7 = G −3 Vo 0 . 28 ⋅ 10PWM (1 + s R ESR C O ) GPWM =  1 2 Vc (1 DVO/ = D)I(L1⋅ +ESR + Q + s 2 / ωn )  + s ωp 1  s / ωn (7)  8 ⋅ FSW0⋅.C O nF C5 = = 45    2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 where CO is the output capacitance. R7 = R 1 1 1 GPWM ≈ ,3 ωp ≈ 3 = 12pF , ωZ = , C8 = R as 2 G 600 Since π⋅CA ⋅ R S⋅ 10 I ⋅ 22 . 1 ⋅ 10 current DIL increasesESR C OD the inductor ripple R C O O C IN decreases >(Equation (3)), the output ripple voltage is C 5 = AC 4 ⋅ DVIN ⋅ FSW therefore the highest when VIN is at its maximum. 10 20 R7 = GPWM (1 + s R ESR C O ) Vo = gm 2 2 Vc 10µF+to / ωp )(1 + s ceramic scapacitor is found adequate C 8 = A (1 s 47µF X5R / ωn Q + / ωn ) 1 or Cf5 =output filtering in most applications. Ripple current 2 output in theπFZ1 R 7 capacitor is not a concern because the R 1 1 GPWM ≈ 1 , ωp ≈ , ωZ = , RCO R ESR C O C 8 = GCA ⋅ R S 11 2 πFP1 R 7 AC SC4524D Applications Information (Cont.) inductor current of a buck converter directly feeds CO, resulting in very low ripple current. Avoid using Z5U and Y5V ceramic capacitors for output filtering because these types of capacitors have high temperature and high voltage coefficients. Freewheeling Diode For the bootstrap circuit, a fast switching PN diode (such as 1N4148 or 1N914) and a small (0.33µF – 0.47µF) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D1. If VOUT > 8V, then a protection diode D4 between the SW and the BST pins will be required as shown in Figure 6 (c). D4 can be a small PN diode such as 1N4148 or 1N914 if the operating temperature does not exceed 85 ºC. Use a small Schottky diode (BAT54 or similar) if the converter is to operate up to 125 ºC. .SS270 REV 6-7 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -50 -25 0 25 50 75 100 125 Temperature (o C) ISW = -2.6A Fig.5 Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC4524D. These diodes should have an average forward current rating at least 2A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diode should be placed close to the SW pin of the SC4524D to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B230A (Diodes Inc.), SS13, SS23 (Vishay), CMSH1-40M, CMSH140ML and CMSH2-40M (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4524D on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor The typical minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about 1.96V at room temperature. The BST-SW voltage is supplied by a bootstrap circuit powered from either the input or the output of the converter (Figure 6(a), 6(b) and 6(c)). To maximize efficiency, tie the bootstrap diode to the converter output if VO>2.5V as shown in Figure 6(a). Since the bootstrap supply current is proportional to the converter load current, using a lower voltage to power the bootstrap circuit reduces driving loss and improves efficiency. Minimum Bootstrap Voltage vs Temperature Figure 5. Typical Minimum Bootstrap Voltage required to Saturate Transistor (ISW= -2.6A). Voltage (V) D1 BST VIN IN SW C1 VOUT SC4524D GND D2 (a) Figure 6(a). Bootstrapping the SC4524D from the converter output 12 SC4524D Applications Information (Cont.) D1 1 VFB  1 1   AC diagram in 1 ⋅ VFB  The block= − 20 ⋅ logFigure 7⋅shows the control loops of a AC = − 20 ⋅ log G R ⋅ 2 πF C ⋅ V  C1 BST CA S CO O  G CAR S 2 πFC C O innerloop (current VO   buck converter with the SC4524D. The VO  VO  VIN R = R  VOUT −1  1 loop) consists of a current sensing resistor (Rs=5.5mW) and 4 R 4 =IN 6  1 . 0 V −  R6  SW   1 1 1 .0  1 .0 V   1 1 a current = − 20 ⋅ log with gain (GCA=18.5). The outer AC amplifier (CA) ⋅ ⋅ 1 .0  SC4524D AC = − 20 ⋅ log −3 ⋅ 3 3 −6 ⋅ 6 D2 3  28 ⋅ 6 ⋅ an 2 π ⋅ 80 ⋅ 10 ⋅ 22 10  28 ⋅ 6 .. 1 ⋅ 10 − 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ a − 3 ..3 GND VFB  loop (voltage loop) consists1of10 error amplifier (EA),⋅ 10 1 VAC = D− 20 ⋅ log 1 ⋅ +V V  O VO + D D=  G R 2 πF C ⋅ V  PWM modulator, and a LC filter.  D= V +V −V CO O  CA S IN D CESAT CESAT VIN + VD − VCESAT 15 . 9 20 10 15 .9 (b) 10 20 Since the = R 7 current loop is internally closed, the remaining = 22 . 3 k R7 = 1 1 . −3 = 22 . 3 k D4  D1 28 compensation task1 the0loop⋅⋅100 3 = 15 . 9 dB is to design the voltage for 1 0 ..28 ⋅ 10 −  AC = − 20 ⋅ log ⋅1 V −3 2 π 10⋅3 ⋅ 22 ⋅ 10⋅−6 FB 3 and A ⋅− ( VO + VD ) ⋅ (1 − D)  28 ⋅ 6 .C1= 1020 ⋅ log⋅ 80c⋅ompensator (C5, R,. 3 1 C8). V + V ) ⋅ (1 − D) 1 7 πF C C5 = = 0 45 nF DIL = ( BST  G CAR S 2C 5 C= O VO  3 = 0 ..45 nF DIL = O F D ⋅ L C1 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 ..1 ⋅ 10 3 π ⋅ 16 ⋅ 10 ⋅ 22 1 ⋅ 10 3 VO 2 SW ⋅ L 1 1 FSW R6  − 1  VIN VOUT>8V   For a converter with switching frequency FSW, output 15 . 9 SW IN  1 .0 V  1 1 1 10 10 20 1 C ⋅ = .12 = 15 . 9 dB a 12pF C8 = pF AC. 3 k − 20 ⋅ log inductance L1, output capacitance−6 3O = ndloading R, the = R7  C 8 −= ⋅ (SC4524D= ⋅ (1 − D) −3 = 22 VO + VD) ⋅ (1 − D) +V ) 3 ( VO D 0 . 28 ⋅ 10 2 2 π600 ⋅⋅10 33 )⋅⋅22 ..110 function in Figure 7 is π⋅output10 3 ⋅ transfer 3 3 . 3  ⋅ 600 ⋅ 10 22 1 ⋅ 10 ⋅ 10 ⋅ 6 . 1 ⋅ 10 to  28 control (V ) 2 π ⋅ 80 (V 22 ⋅ D2 L1 = = L1 C O GND 20 % ⋅ IO ⋅ FSW VO + VD 20 % ⋅ IO ⋅ FSW given by: 1 C5 = = 0 . 45 nF VIN + VD − VCESAT 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 15 .9 G (1 + s R ESR C O ) V GPWM (1 + s R ESR C O ) Vo = 10 20 (8) R7 = 22 . 3 k Vo = (1 + s / ωPWM + s / ω Q + s 2 / ω2 ) 2 2 D4 is either a I juntion diode or aD) pn ⋅ D ⋅ (1 − Schottky diode = IRMS _ CIN = I O the operating temperature IRMS _dCIN =CO ⋅= D ⋅ (1 − D) 1. c p )(1 n n Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) epending on 0 . 28 ⋅ 10 −3 pF = 12 8 (C) π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 2 1 This transfer function has a finite DC gain ( VO + VD ) ⋅ (1 − D) C5 = = 0 . 45 nF = 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 FSW ⋅ L 1 R 1 1 GPWM ≈ R ωp ≈ 1 ωZ = 1 GPWM ≈ G ⋅ R ,, ωp ≈ R C ,, ωZ = R C ,, Figures 6(b) and 6(c). Methods of 1Bootstrapping the   1 (1 +s R C )  1 CA S O ESR O GCA ⋅ R S RCO R ESR C O DVO = DIL ⋅  ESR + ⋅ =  ESR O DVO = DIL Vo ESR + 8 ⋅GPWM⋅ C C = SC4524D  2 ( VO + VD ) ⋅ (1 − D) O  (1 + s /⋅ FSW (1C Os8 ωn2 π⋅ 600 ω10 3 ⋅ 22 . 1 ⋅ 10 3 = 12pF 8 FSW ⋅ + / Q + s 2 / ⋅ n ) Vc ωp ) AC AC 20 20 % ⋅ IO ⋅ FSW 10 20 10 at Loop Compensation an ESRRzero FZ 7= R7 = g m gm R 1 G Vo ω ≈ 1 PWM GPWM ≈is to shape the=frequency , (1 + s R ESRZC= ) , ωO , p of IO  The goal D) compensation G ⋅ R 2 12 IO C Vc 1 + sR C Op ω S C IN > _ CIN = I ⋅ D ⋅ (1 − O C5 = R / ω = C IN >converterF so CA to achieve (high /DC )(1 + s / ωn Q + s ESR1nO)  response of the 4 ⋅ DV ⋅ C 5 2 πF R as IN SW 4 ⋅ DVIN ⋅ FSW W ⋅ CO  Z1 7 2 πFZ1 R 7 accuracy and fast transient response while maintaining a dominant low-frequency pole FP at AC 20 10 1 loop stability. 1 R7 = R 1 C8 = = C 8 ≈ 21 F , R GPWM ≈ , ωp ωZ = , gm π   1 2 C FP1 R 7 π P1 7 GCA ⋅ R S RO R ESR C O  = DIL ⋅  ESR + CONTROLLER AND SCHOTTKY DIODE  8 ⋅ FSW ⋅ C O  1   C= Io 5 AC and double poles at half the switching frequency. Rs CA 2 πFZ1 R 7 10 20 R7 = gm 1 Including the voltage divider (R4 and R6), the control to REF C8 = + Vc PWM 2 πF R7 feedback transfer function is found and plotted in Figure EA IO P1 MODULATOR 1 FB > L1 Vo C5 = SW 8 as the converter gain. 4 ⋅ DVIN ⋅ FSW 2 πFZ1 R 7 12 Vramp COMP C5 R7 C8 Co C8 = Resr 1R4 2 πFP1 R 7 R6 Figure 7. Block diagram of control loops Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole at FP1. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the 13 SC4524D Applications Information (Cont.) integrator pole (-90deg) and the dominant pole (-90deg). The high frequency pole nulls the ESR zero and attenuates high frequency noise. 60 where gm=0.3mA/V is the EA gain of the SC4524D. Example: Determine the voltage compensator for an 800kHz, 12V to 3.3V/2A converter with 22uF ceramic output capacitor. Choose a loop gain crossover frequency of 80kHz, and place voltage compensator zero and pole at FZ1=16kHz (20% of FC), and FP1=600kHz. From Equation (9), the required compensator gain at FC is AC 20 log 1 18.5 5.5 10 3 30 GAIN (dB) Fz1 Fp1 CO MP EN SA TO 0 Fp CO NV ER T ER RG AIN Fc GA IN LO OP G AIN -30 1 2 80 103 22 10 6 Fz -60 1K Fsw/2 1.0 3.3 11.4dB Then the compensator parameters are 10K 100K FREQUENCY (Hz) 1M 10M 1 VFB 1 AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V CO O  CA S Figure 8. Bode plots for voltage loop design     R7 10 11.4 20 0.3 10 3 12.4k 2 . 016 103 12.4 103 1 1 1 AC = − of ⋅ log ⋅  = 15 . 9 dB Therefore, the procedure 20 the  voltage loop − 3 ⋅ design for 3 −6 3 .3  2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10  28 ⋅ 6 . 1 ⋅ 10 the SC4524D can be summarized as: 1 C8 2 600 103 12.4 103 C5 1 0.8nF 21pF    O (1) Plot the converter gain, i.e. 15 .9 control to feedback transfer 10 20 R7 = = 22 . 3 k function. Select R7=12.4k, C5=1nF, and C8=22pF for the design. 0 . 28 ⋅ 10 −3 (2) Select the open loop crossover frequency, FC, between 1 10% and 20% of the switching frequency. At FC, = 0 . 45 nF Compensator parameters for various typical applications find the C5 = 3 2 π ⋅AC. In typical applications with 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 required compensator gain, are listed in Table 5. A MathCAD program is also available ceramic output capacitors, the ESR zero is neglected and upon request for detailed calculation of the compensator 1 C 8 = gain at F 3 an be estimated by = 12pF the required compensator c parameters. C 2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 1 VFB  1 (9) Thermal Considerations AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   O O  CA S G C (1 + s R  C ) Vo PWM ESR O = (3) Place the compensator s / ω )F1 ,+between 10%ω2 ) zero, (Z1 s / ω Q + s 2 / and For the power transistor inside the SC4524D, the Vc (1 + n n 1p 1 1 .0  20% of the crossoverfrequency, FC. ⋅ c⋅onduction .loss PC, the switching loss PSW, and bootstrap AC = − 20 ⋅ log  = 15 9 dB −3 3 −6 3 . 3 loss P = c + be + PBST + PQ 2 π ⋅ 80 ⋅ 10 ⋅ zero, (4) Use the compensator pole,⋅FP1, to cancel the ESR 22 ⋅ 10 circuitPTOTAL BST,PCan PSWestimated as follows:  28 ⋅ 6 . 1 10 FZ. R 1 1 GPWM ≈ , ωp ≈ , ωZ = , (5) Then, the parameters GCAtheS compensation network of ⋅ R RCO PQ = VIN ⋅ 2mA 15 . 9 PR ESR C⋅OVCESAT ⋅ IO =D C 10 by can be calculated 20 R7 = = 22 . 3 k 0 . 28 ⋅ 10 −3 10 AC 20 1 PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW R 7 =1 (10) 2 gm C5 = = 0 . 45 nF 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 I 1 PBST = D ⋅ VBST ⋅ O C5 = 1 40 2 πFZ1 R 7 C8 = = 12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 1 where P BST is1 − D) ⋅ V ⋅ I voltage and tS is the equivalent V = ( the BST supply C8 = D DO 2 πFP1 R 7 GPWM (1 + s R ESR C O ) Vo = 2 Vc (1 + s / ωp )(1 + s / ωn Q + s 2 / ωn ) 14 P = (1 .1 ~ 1 .3 ) ⋅ I2 ⋅ R IND O DC SC4524D switching time of the NPN transistor (see Table 4). Table 4. Typical switching time Input Voltage 12V Load Current 1A 2A 12.5ns 15.3ns PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4524D, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. V IN + PBST + Paddition, the quiescent current loss is In Q PQ = VIN ⋅ 2mA (11) The total power loss of the SC4524D is therefore ⋅ I O ⋅ FSW PTOTAL = PC + PSW + PBST + PQ O (12) 0 IO The temperature rise⋅ of the SC4524D PQtheVproduct of the is Fig.9 mA = IN ⋅ 2 PC = D ⋅ VCESAT IO total power dissipation (Equation (12)) and qJA (36oC/W), which is the thermal impedance from junction to ambient 1 for thePSW = 2 EDP⋅package. SW SOIC-8 ⋅ t S VIN ⋅ I O ⋅ F I ) ⋅ I2 ⋅ R DCt is not recommended to operate the SC4524D above I O PBST = D ⋅ VBST ⋅ O o 40 125 C junction temperature. In the applications with high input voltage and high output current, the switching frequency may D) ⋅ VD toObe reduced to meet the thermal PD = (1 − need ⋅ I requirement. PIND = (1 .1 ~ 1 .3 ) ⋅ I2 ⋅ R DC O VOUT ZL Figure 9. Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized. Vin 15 Cu SC4524D Recommended Component Parameters in Typical Applications Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 5. Recommended inductance (L1) and compensator (R7, C5, C8) Vin (V) Typical Applications Vo (V) Io (A) Fsw (KHz) 500 1 1000 1.5 500 2 1000 500 1 1000 2.5 500 2 1000 500 1 1000 1.5 500 2 1000 500 1 1000 2.5 500 2 1000 500 1 1000 3.3 500 2 1000 1 500 1.5 2 500 500 1 1000 2.5 500 2 1000 500 1 1000 3.3 500 2 1000 500 1 1000 5 500 2 1000 500 1 1000 7.5 500 2 1000 500 1 1000 10 500 2 1000 C2 (uF) Recommended Parameters L1 (uH) R7 (K) C5 (nF) 6.8 4.02 3.3 3.3 7.5 0.82 3.3 4.02 3.3 1.5 7.5 0.82 4.7 13.3 0.82 2.2 21.5 0.68 2.2 11 0.82 1.5 21.5 0.68 6.8 4.02 3.3 3.3 7.68 0.82 3.3 4.02 3.3 2.2 7.68 0.82 8.2 6.81 2.2 4.7 14.3 0.68 4.7 6.81 1.5 2.2 12.1 0.68 6.8 9.09 1 3.3 16.2 0.68 3.3 9.09 1 2.2 17.8 0.68 8.2 4.32 3.3 4.7 4.32 3.3 15 6.81 1.5 6.8 12.1 0.82 6.8 6.81 1.5 3.3 12.1 0.68 15 9.09 1 8.2 18.7 0.68 8.2 9.09 1 4.7 18.7 0.68 15 14.3 0.82 10 24.9 0.68 8.2 14.3 0.82 4.7 27.4 0.68 15 21.5 0.82 8.2 38.3 0.68 8.2 21.5 0.82 4.7 38.3 0.68 10 25.5 0.82 4.7 51.1 0.68 4.7 25.5 0.82 2.2 51.1 0.68 C8 (pF) 3.3 10 5 22 22 22 10 22 10 22 10 22 12 10 16 SC4524D Typical Application Schematics 5V C4 4.7 F D1 1N4148 C1 0.33 F L1 2.2 H R4 33.2k V IN IN BST SW OUT 3.3V/2A SS/EN SC4524D FB COMP C7 10nF R7 17.8k ROSC GND D2 20BQ030 R6 14.3k C2 22 F C8 10pF R5 15.8k C5 0.68nF L1: Coiltronics LD1-2R2 C2: Murata GRM31CR60J226K C4: Murata GRM31CR60J475K Figure 10. 1MHz 5V to 3.3V/2A Step-down Converter V IN 10V – 16V C4 4.7 F D1 1N4148 IN BST SW C1 0.33 F L1 4.7 H R4 33.2k OUT 1.5V/2A SS/EN SC4524D FB COMP C7 10nF R7 4.32k ROSC GND D2 20BQ030 R6 66.5k C2 22 F C8 33pF R5 38.3k C5 3.3nF L1: Coiltronics DR73-4R7 C2: Murata GRM31CR60J226K C4: Murata GRM31CR60J475K Figure 11. 500kHz 10V-16V to 1.5V/2A Step-down Converter 17 SC4524D SS Typical Performance Characteristics SS270 REV 6-7 (For A 12V to 5V/2A Step-down Converter with 1MHz Switching Frequency) Load Characteristic 6 5 Output Voltage (V) 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 12V Input (5V/DIV) 5V Output (2V/DIV) SS Voltage (1V/DIV) Load Current (A) 10ms/DIV Figure 12(a). Load Characteristic OCP Figure 12(b). VIN Start up Transient (IO=2A) 5V Output Short (5V/DIV) 5V Output Response (500mV/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV 20ms/DIV Figure 12(c). Load Transient Response (IO= 0.3A to 2A) Figure 12(d). Output Short Circuit (Hiccup) 18 SC4524D Outline Drawing - SOIC-8 EDP A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A A1 C A-B D e D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .069 .005 .065 .020 .010 .193 .197 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 .053 .000 .049 .012 .007 .189 .150 1.35 0.00 1.25 0.31 0.17 4.80 3.80 C bxN bbb F 1.75 0.13 1.65 0.51 0.25 4.90 5.00 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0° 8° 0.10 0.25 0.20 h EXPOSED PAD H H GAGE PLANE 0.25 h c L (L1) 01 SEE DETAIL SIDE VIEW NOTES: 1. 2. 3. 4. A DETAIL A CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES ). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS . REFERENCE JEDEC STD MS -012, VARIATION BA . 19 SC4524D Land Pattern - SOIC-8 EDP E D SOLDER MASK DIMENSIONS DIM (C) F G Z Y THERMAL VIA Ø 0.36mm NOTES: 1. P X C D E F G P X Y Z INCHES (.205) .134 .201 .101 .118 .050 .024 .087 .291 MILLIMETERS (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 2. 3. 20 SC4524D © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. 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