SC4525C

SC4525C 28V 3A Step-Down Switching Regulator POWER MANAGEMENT Features            Description The SC4525C is a constant frequency peak current-mode step-down switching regulator capable of producing 3A output current from an input ranging from 3V to 28V. The switching frequency of the SC4525C is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4525C is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4525C achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4525C is available in SOIC-8 EDP package. Wide input range: 3V to 28V 3A Output Current 200kHz to 2MHz Programmable Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications       XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs SC4525A Typical Application Circuit Efficiency V IN 10V– 28V C4 4.7mF D1 1N4148 C1 0.33 mF L1 90 80 SW SS/EN Efficiency (%) IN BST OUT R4 33.2k VIN = 12V 70 60 50 40 0.0 0.5 1.0 1.5 VIN = 24V 5.2mH SC4525C FB 5V/3A COMP C7 R7 12.7k ROSC GND D2 20BQ030 R6 8.25k C2 10m FX3 22nF C8 22pF R5 15.8k C5 2.2nF 2.0 2.5 3.0 L1: Coiltronics CD1- 5R2 C2: Murata GRM31CR60J106K C4: Murata GRM32ER71H475K Load Current (A) Figure 1. 1MHz 10V -28V to 5V/3A Step-down Converter Jan. 13, 2011 1 Efficiency of the 1MHz 10V-28V to 5V/3A Step-Down Conve SC4525C Pin Configuration Ordering Information Device SC4525CSETRT(1)(2) SW IN ROSC GND 1 2 3 4 9 8 7 6 5 BST FB COMP SS/EN Package SOIC-8 EDP Evaluation Board SC4525CEVB Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) 2 SC4525C Absolute Maximum Ratings VIN Supply Voltage ……………………………… -0.3 to 32V BST Voltage ……………………………………………… 42V BST Voltage above SW …………………………………… 34V SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to VIN SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Peak IR Reflow Temperature …………………………. (2) Thermal Information Junction to Ambient (1) ……………………………… 36°C/W Junction to Case (1) ………………………………… 5.5°C/W Maximum Junction Temperature……………………… 150°C Storage Temperature ………………………… -65 to +150°C Lead Temperature (Soldering) 10 sec ………………… 300°C Recommended Operating Conditions Input Voltage Range ……………………………… 3V to 28V Maximum Output Current ……………………………… 3A Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C 260°C ESD Protection Level ………………………………… 2000V Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ. Parameter Input Supply Input Voltage Range VIN Start Voltage VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown Conditions Min 3 Typ Max 28 Units V V mV VIN Rising 2.70 2.82 225 2.95 VCOMP = 0 (Not Switching) VSS/EN = 0, VIN = 12V 2 40 2.6 52 mA µA Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Pin to Switch Current Gain COMP Maximum Voltage COMP Source Current COMP Sink Current VIN = 8V to 28V VFB = 1V, VCOMP = 0.8V 0.980 1.000 0.005 -170 300 60 15.2 -340 1.020 V %/V nA µΩ-1 dB A/V V µA VFB = 0.9V VFB = 0.8V, VCOMP = 0.8V VFB = 1.2V, VCOMP = 0.8V (Note 1) ISW = -3.9A 3.9 2.35 17 25 Internal Power Switch Switch Current Limit Switch Saturation Voltage 5.1 380 6.6 600 A mV 3 SC4525C Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ. Parameter Minimum Switch On-time Minimum Switch Off-time Switch Leakage Current Minimum Bootstrap Voltage BST Pin Current Conditions Min Typ 150 100 Max 150 10 Units ns ns µA V mA ISW = -3.9A ISW = -3.9A 1.8 100 2.3 150 Oscillator Switching Frequency ROSC = 12.1kΩ ROSC = 73.2kΩ ROSC = 12.1kΩ, VFB = 0 ROSC = 73.2kΩ, VFB = 0 1.04 230 100 35 60 1.3 300 1.56 370 250 90 MHz kHz kHz Foldback Frequency Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current Soft-start Discharging Current Hiccup Arming SS/EN Voltage Hiccup SS/EN Overload Threshold Hiccup Retry SS/EN Voltage 0.2 0.3 1.2 1.9 1.6 2.4 1.5 3.2 0.4 1.4 V V µA µA V V 1.2 V VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V VSS/EN Rising VSS/EN Falling VSS/EN Falling 0.95 2.15 1.9 0.6 1.0 Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: Switch current limit does not vary with duty cycle. 165 10 °C °C 4 SC4525C Pin Descriptions SO-8 1 2 3 4 Pin Name SW IN ROSC GND Pin Function Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. An external resistor from this pin to ground sets the oscillator frequency. Ground pin Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. 5 SS/EN 6 7 8 9 COMP FB BST Exposed Pad 5 SC4525C Block Diagram IN COMP 6 SLOPE COMP 2 + + EA + S + + ISEN 3.53m W OC + ILIM 18mV BST FB 7 V1 + PWM FREQUENCY FOLDBACK 8 S R Q POWER TRANSISTOR ROSC 3 OSCILLATOR CLK 1.2V OVERLOAD A1 R + PWM 1 SW R SS/EN 5 1V 1.9V FAULT REFERENCE & THERMAL SHUTDOWN SOFT START AND OVERLOAD HICCUP CONTROL GND 4 Figure 2. SC4525C Block Diagram 1.9V IC 2.4mA B4 + B1 S Q R OVERLOAD SS/EN 1V/2.15V B2 FAULT ID 3.9mA _ Q S R OC PWM B3 Figure 3. Soft-start and Overload Hiccup Control Circuit 6 f (2) 24Vin Eff Typical Characteristics Efficiency VO=5V V O=3.3V V O=2.5V Curve 3 SC4525A SC4525C SC4525A SS270 REV 6-7 90 85 80 75 70 65 60 55 50 40 0 0.5 1 90 85 80 75 70 65 60 55 50 40 Efficiency V O=5V V O=3.3V V O=2.5V Feedback Voltage vs Temperature 1.02 VIN = 12V 1.01 1.00 0.99 0.98 0.97 Efficiency (%) Efficiency (%) V O=1.5V Curve 5 45 SS270 REV 6-7 1MHz, VIN=12V D2 =B320A Curve 6 45 2.5 3 0 0.5 1 1MHz, VIN=24V D 2 =B330A 1.5 2 1.5 2 2.5 3 VFB (V) -50 -25 0 25 50 75 o 100 125 Load Current (A) Load Current (A) Temperature ( C) SS270 REV 6-7 SS270 REV 6-7 1000 Frequency Setting Resistor vs Frequency VIN =12V Frequency vs Temperature 1.2 Foldback Frequency vs VFB 1.25 1 0.75 0.5 TA=25oC 0.25 ROSC =12.1k 0 0.00 0.20 0.40 0.60 0.80 1.00 ROSC =73.2k 100 Normalized Frequency 1.1 ROSC =73.2k 1.0 ROSC =12.1k 10 (8) OCP current 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0.9 (9) BST Pin current -50 -25 0 25 50 75 100 125 Temperature (OC) 0.8 Frequency (MHz) SS270 REV 6-7 Normalized Frequency ROSC (k ) VFB (V) SS270 REV 6-7 500 450 Switch Saturation Voltage v s Switch Current Switch Current Limit vs Temperature 5.2 4.8 100.0 BST Pin Current vs Switch Current VIN = 12V V BST-SW =5V VCESAT (mV) 350 300 250 200 150 100 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Switch Current (A) 25oC -40 C o 4.4 4.0 3.6 3.2 -50 -25 0 25 50 75 100 125 BST Pin Current (mA) 400 125oC Current Limit (A) 75.0 50.0 -40oC 125oC 25.0 0.0 0 0.5 1 1.5 2 2.5 3 3.5 4 Temperature (oC) Switch Current (A) 7 Curve 11 SS270 REV 6-7 Curve 12 SS270 REV 6-7 SC4525C Typical Characteristics (Cont.) SS270 REV 6-7 VIN T hresholds vs Temperature 3.0 2.9 Start 2.5 2.0 VIN Supply Current vs Soft-Start Voltage 125oC 100 80 VIN Shutdown Current vs VIN VSS = 0 VIN Threshold (V) Current (mA) 2.8 2.7 2.6 Current (uA) -40oC 1.5 1.0 0.5 0.0 60 -40oC 40 20 0 125oC Curve 14 2.5 2.4 -50 -25 0 UVLO Curve 15 0 0.5 1 VSS (V) 1.5 2 SS270 REV 6-7 25 50 o 75 100 125 0 5 10 15 VIN (V) 20 25 30 Temperature ( C) SS270 REV 6-7 SS270 REV 6-7 VIN Quiescent Current vs VIN 2.5 2.0 125oC -40 C o 0.40 SS Shutdown Threshold vs Temperature Soft-Start Charging Current vs Soft-Start Voltage 0.0 -0.5 SS Threshold (V) 0.35 Current (mA) Current (uA) 1.5 1.0 0.5 0.0 0 5 10 15 VIN (V) 20 25 30 -1.0 -1.5 -2.0 -2.5 125oC 0.30 -40oC 0.25 VCOMP = 0 0.20 -50 -25 0 25 50 o -3.0 75 100 125 0 0.5 1 VSS (V) 1.5 2 Temperature ( C) 8 SC4525C Applications Information Operation The SC4525C is a constant-frequency, peak current-mode, step-down switching regulator with an integrated 28V, 3.9A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 3.53mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. Shutdown and Soft-Start Table 2: Fault conditions and protections The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4525C is summarized in Table 1. Table 1: SS/EN operation modes SS/EN SS/EN 2.15V Mode Shutdown Not switching Switching & hiccup disabled Switching & hiccup armed Supply Current 18uA @ 5Vin 2mA Load dependent Condition Condition IL>ILimit, V FB>0.8V IL>ILimit, V FB 4 ⋅ DV ⋅ F The peak current IN SW SC4525C power transistor is at limit of least 3.9A. The maximum deliverable load current for the   1  DVO = DIL ⋅  ESR +  8 ⋅ FSW ⋅ C O    I R7 = C R  VO (6) C5 = R 4IN=> 6  O − 1   4⋅1 .VIN ⋅ FSW D0 V  AC =  IO V 1 whereC IN > the 1 ⋅ DV log AC = − 20 ⋅IN is  allowable input ripple voltage. ⋅ FB  C5 = C8 = 4⋅ V CARVFSW πFC C O VO  D IN S  GOV+ ⋅ D 2  D= Multi-layerVceramic capacitors, which have very low ESR IN + VD − VCESAT 1 1 1 (a few mW) and can easily handle high RMS ripple current,. 0 C 8 = AC = − 20 ⋅ log ⋅ ⋅ ==  R 15 −3 3 −6 are the ideal choice1for input π ⋅ 80 ⋅ 10 A ⋅ single 4.7µF. 3  7 3 28 ⋅ 6 . ⋅ 10 2 filtering. 22 ⋅ 10 X5R ceramic( V + V ) ⋅ (1 − D) capacitor is adequate for 500kHz or higher O D DIL frequency applications, and 10µF is adequate C 5 = switching = 15 . 9 FSW ⋅ L 1 for 200kHz to 500kHz switching frequency. For high 10 20  VFB  R7 = =122 . 3 k 1 AColtage applications, a small ceramic  − 20 ⋅ log v = 0 . 28 ⋅ 10 −3 (1µF or 2.2µF) can be  G R ⋅ 2 πF C ⋅ V  ( VO +CAwith a low ESR electrolytic capacitor to C 8 = C O  VD )S⋅ (1 − D) O placedLin = parallel 1 1 20 % ⋅ I and bulk capacitance Cs5atisfy both the3ESRO ⋅ FSW 3 = 0 . 45 nF requirements. = 2 π ⋅ 16 ⋅ 10 ⋅ 22 .1 ⋅ 10 1 1 1 .0  AC = − 20 ⋅ log ⋅ ⋅   = 15 28 ⋅ 6 . 1 ⋅ 10 − 3 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 3 . 3  Vo 1 Output Capacitor = C8 = I = 12pF Vc 2 πRMS _ CIN 10I O ⋅ 22 .⋅ (110D) ⋅ 600 ⋅ = 3 ⋅ D 1 ⋅ − 3 The output .9ripple voltage DVO of a buck converter can be 15 10 20 expressed as = 22 . 3 k R7 = G −3 Vo 0 . 28 ⋅ 10PWM (1 + s R ESR C O ) GPWM =  1 2 Vc (1 DVO/ = D)I(L1⋅ +ESR + Q + s 2 / ωn )  + s ωp 1  s / ωn (7)  8 ⋅3FSW0⋅.C O nF C5 = = 45   3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 where CO is the output capacitance. R7 = R 1 1 1 GPWM ≈ ,3 ωp ≈ 3 = 12pF , ωZ = , C8 = R as 2 G 600 Since π⋅CA ⋅ R S⋅ 10 I ⋅ 22 . 1 ⋅ 10 current DIL increasesESR C OD the inductor ripple R C O O C IN decreases >(Equation (3)), the output ripple voltage is C 5 = AC 4 ⋅ DVIN ⋅ FSW therefore the highest when VIN is at its maximum. 10 20 R7 = GPWM (1 + s R ESR C O ) Vo =g 2 2 Vc 22µFmto / ωp )(1 + s ceramic scapacitor is found adequate C 8 = A (1 + s 47µF X5R / ωn Q + / ωn ) 1 or Cf5 =output filtering in most applications. Ripple current 2 output in theπFZ1 R 7 capacitor is not a concern because the R 1 1 GPWM ≈ 1 current of a buck converter directly=feeds C ,, , ωp ≈ , ωZ inductor RCO R ESR C OO C 8 = GCA ⋅ R S 2 πFP1 R 7 R= 10 20 AC 11 SC4525C Applications Information (Cont.) resulting in very low ripple current. Avoid using Z5U and Y5V ceramic capacitors for output filtering because these types of capacitors have high temperature and high voltage coefficients. Freewheeling Diode Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC4525C. These diodes should have an average forward current rating at least 3A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. For the bootstrap circuit, a fast switching PN diode (such as 1N4148 or 1N914) and a small (0.33µF – 0.47µF) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D1. When bootstrapping from high input voltages (>20V), reduce the maximum BST voltage by connecting a Zener diode (D3) in series with D1 as shown in Figure 6 (b). If VOUT > 8V, then a protection diode D4 between the SW and the BST pins will be required as shown in Figure 6 (c). D4 can be a small PN diode such as 1N4148 or 1N914 if the operating temperature does not exceed 85 ºC. Use a small Schottky diode (BAT54 or similar) if the converter is to SS270 REV 6-7 operate up to 125 ºC. 2.2 2.1 2.0 1.9 1.8 1.7 1.6 ISW =-3.9A Fig 5 Minimum Bootstrap Voltage vs Temperature The freewheeling diode should be placed close to the SW pin of the SC4525C to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B320A, B330A (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and CMSH3-40MA (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4525C on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor The minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about 2V at room temperature. The BST-SW voltage is supplied by a bootstrap circuit powered from either the input or the output of the converter (Figure 6(a), 6(b) and 6(c)). To maximize efficiency, tie the bootstrap diode to the converter output if VO>2.5V as shown in Figure 6(a). Since the bootstrap supply current is proportional to the converter load current (Equation (10), page 14), using a lower voltage to power the bootstrap circuit reduces driving loss and improves efficiency. Voltage (V) -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 5. Typical Minimum Bootstrap Voltage required to Saturate the Transistor (ISW= -3.9A) D1 BST VIN IN SW C1 VOUT SC4525C GND D2 (a) Figure 6(a). Bootstrapping the SC4525C from the Converter Output 12 SC4525C Applications Information (Cont.) D3 D1 1 VFB  1 1   AC diagram in 1 ⋅ VFB  The block= − 20 ⋅ logFigure 7⋅shows the control loops of a AC = − 20 ⋅ log G R ⋅ 2 πF C ⋅ V  CA S CO O  G CAR S 2 πFC C O innerloop (current VO   buck converter with the SC4525C. The V  R 4 = R 6BST VO − 1  C1 = R  O −1    loop) consists of a current sensing resistor (Rs=3.53mW) R4 6  1 .0 V   1 1 1 .0  1 .0 V   1 1 VIN VOUT and a A C = − 20 ⋅ log current amplifier (CA) with gain (GCA=18.5). The A = − 20 ⋅ log ⋅ ⋅ 1 .0  SW IN −3 ⋅ 3 −6 ⋅ C −3 3 ⋅ 22 ⋅ 10 − 6 3 2 π ⋅ 80 ⋅ 10 π error amplifier  28 ⋅ 6 ..1 ⋅ 10 3 ..3 loop) 1 ⋅ 10 VFB  outer loop (voltage  28 ⋅ 6consists of2an⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 1 SC4525C VAC = D− 20D⋅2log 1 ⋅ +V V   (EA), a PWM modulator, and a LC filter. VO + D D=  G R 2 πF C ⋅ V  D = V GNDO − V CO O  CA S + VD − VCESAT V IN CESAT VIN + D 15 . 9 CESAT 20 10 15 .9 Since the = 10 20 current loop is internally closed, the remaining R7 = = 22 . 3 k R − 1 1 . − 3 = 22 . 3 k  b 28 compensation t 1 71 0 ..28 ⋅ 100 3 for AC (=) − 20 ⋅ logD1 ⋅  1ask 3 the0loop⋅⋅10  = 15 . 9 dB is to design the voltage  V −3 D4 2 π 10⋅ ⋅ 22 ⋅ 10⋅−6 FB 3 and A ⋅− ( VO + VD ) ⋅ (1 − D)  28 ⋅ 6 .C1= 1020 ⋅ log⋅ 80c⋅ompensator (C5, R,. 3 1 C8). 1 7 ( VO + VD ) ⋅ (1 − D) πF C C5 = = 0 45 nF DIL =  G CAR S 2C 5 C= O VO  3 = 0 ..45 nF DIL = 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 ..1 ⋅ 10 3 π ⋅ 16 ⋅ 10 ⋅ 22 1 ⋅ 10 3 FSW ⋅ L 1 ⋅L 2 BST FSW  VO − 1  1 C1 R6   For a converter with switching frequency FSW, output 15 . 9  1 .0 V VIN 20 1 1 1 1 .0 VOUT>8V 10  inductance L , output capacitance C ⋅ = ndloading R, the 1 a 12pF 15 . 9 dB C8 = pF A= = R VD ) = 22C. 3 k − 20 ⋅ log IN ( V + SW= ⋅ (1 − D) C 8 −= ⋅ 1 3 3 3 3 − 6 3O = 12 7 ) ⋅ (1 − D) −3 O π ⋅ 80 (V 22 ⋅ ⋅ 10 ⋅ 6 . 1 ⋅ 10 2 π⋅output10 ⋅ transfer  28 control (V ) 2 2 π600 ⋅⋅10 3 )⋅⋅22 ..110 function in Figure 7 is . L 1 = ( VO + V to ⋅ 600 ⋅ 10 O 22 1 ⋅ 10 3 . 3  L 1 = 4525C DI 0F28 ⋅ 10 C SC 20 % ⋅ ⋅ VO + VD O SW 20 % ⋅ IO ⋅ FSWD2 given by: 1 GND C5 = = 0 . 45 nF VIN + VD − VCESAT 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 15 .9 GPWM (1 + s R ESR C O ) Vo GPWM (1 + s R ESR C O ) Vo = 10 20 (8) 2 IRMS _ CIN = I O ⋅ D ⋅ (1 − D) 1 R 7 = 0 . 28 ⋅ 10 −3 = 22 . 3 k Vc = (1 + s / ωp )(1 + s / ωn Q + s 2 / ωn ) = I ⋅ D ⋅ (1 − D) V (1 + s / ω )(1 + s / ω Q + s 2 / ω2 ) I 4 is either a juntion c p n n = 12pF DRMS _ CIN pnCO = diode or a Schottky diode 8 depending on the operating 600 ⋅ 10 2 π⋅ temperature. 3 ⋅ 22 . 1 ⋅ 10 3 1 This transfer function has a finite DC gain ( VO + VD ) ⋅ (1 − D) (C) C5 = = 0 . 45 nF = 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 FSW ⋅ L 1 R 1 1 GPWM ≈ R ωp ≈ 1 ωZ = 1 GPWM ≈ G ⋅ R ,, ωp ≈ R C ,, ωZ = R C ,,   1 (1 +s R C ) 1  CA O ESR O GCA ⋅ R S RCO R ESR C O DVO (c). ⋅  ESR + ⋅ =  ESR O DVO = DIL Vo ESR + ⋅G Bootstrapping the 1 Figure 6(b) and = DIL Methods8 of PWM⋅ C C 8 = = 12pFS  FSW(1C Os/ ω Q + s 2 / ω2 ) 3 ( VO + VD ) ⋅ (1 − D)  8 ωp ) O  Vc (1 + s /⋅ FSW ⋅ +  n2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 A n SC4525C C AC 20 20 % ⋅ IO ⋅ FSW 10 20 an ESRRzero10 at FZ 7= R7 = g Loop Compensation gm R 1 G, Vo ω ≈ 1 PWM (1 + s R ESR C= ) m GPWM ≈ , ωZ O , =p IO  ⋅ D ⋅ (1 − D) 2 1 IO GCA ⋅ R S R/C Op )(1 + s / ωn Q + sR ESR1nO) C Vc (1 + s ω / ω2 C IN > > _ CIN = I O C5 =  The goal of C IN 4 ⋅ DV ⋅ F is to shape the frequency C 5 = 2 πF R compensation IN SW 4 ⋅ DVIN ⋅ FSW W ⋅ CO  Z1 7 2 πFZ1 R 7 response of the converter so C as to achieve high DC a dominant low-frequency pole FP at A 20 1 accuracy and fast transient10 1 R 7 = response while maintaining R 1 C8 = = C 8 ≈ 21 F , R GPWM ≈ , ωp ωZ = , gm π l oop stability.  1 2 πFP1 7 GCA ⋅ R S R C O P1 R 7 R ESR C O  = DIL ⋅  ESR +  8 ⋅ FSW ⋅ C O  1   C= 5 AC and double poles at half the switching frequency. 2 πFZ1 R 7 CONTROLLER AND SCHOTTKY DIODE 10 20 R7 = gm 1 Io Including the voltage divider (R4 and R6), the control to C 8 = Rs CA 2 πFP1 R 7 feedback transfer function is found and plotted in Figure IO 1 > C5 = 8 as the converter gain. REF 4 ⋅ DVIN ⋅ FSW + 2 πFZ1 R 7 12 EA FB - Vc PWM MODULATOR Vramp SW L1 C8 = Co COMP C5 R7 C8 1 2 πFP1 R 7 Vo R4 Resr R6 Figure 7. Block diagram of control loops Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole at FP1. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). 13 SC4525C Applications Information (Cont.) The high frequency pole nulls the ESR zero and attenuates high frequency noise. 60 Example: Determine the voltage compensator for an 800kHz, 12V to 3.3V/3A converter with 47uF ceramic output capacitor. Choose a loop gain crossover frequency of 80kHz, and place voltage compensator zero and pole at FZ1=16kHz (20% of FC), and FP1=600kHz. From Equation (9), the required compensator gain at FC is AC 20 log 1 18.5 3. 53 10 3 30 GAIN (dB) Fz1 Fp1 CO MP EN SA TO 0 Fp CO NV ER T ER RG AIN Fc GA IN LO OP G AIN 1 2 80 103 47 10 6 -30 1.0 3.3 14.1 dB Fz -60 1K Fsw/2 Then the compensator parameters are 10M 10K 1 VFB  1 AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   CO O  CA S Figure 8. Bode plots for voltage loop design 100K FREQUENCY (Hz) 1M 10 20 R7 = = 16.9 k 0.3⋅ 10− 3 1 C5 = = 0. 589 nF 3 2π ⋅ 16 ⋅ 10 ⋅ 16.9 ⋅ 10 3 14.1 1 1 1 .0  C8 = =15.7 pF  AC − procedure of the voltage loop design for −6 ⋅ ⋅ Therefore,=the20 ⋅ log 2  = 15 . 9 dB π⋅ 600 ⋅ 103 ⋅ 16.9 ⋅ 10 3 −3 3 3 .3  2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10  28 ⋅ 6 . 1 ⋅ 10 the SC4525C can be summarized as: Select R7=16.9k, C5=0.68nF, and C8=22pF for the design. 15 . 9 (1) Plot the converter gain, i.e. control to feedback transfer 10 20 function. = Compensator parameters for various typical applications R7 = 22 . 3 k 0 28 ⋅ 10 −3 (2) Select the .open loop crossover frequency, FC, between are listed in Table 5. A MathCAD program is also available 1 10% and 20% of the switching frequency. At FC, find the upon request for detailed calculation of the compensator C5 = = 0 . 45 nF 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . C ⋅ 10 3 required compensator gain, A1. In typical applications with parameters. ceramic output capacitors, the ESR zero is neglected and 1 C8 = = be estimated by the required compensator gain at FC 3can12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 Thermal Considerations 1 V 1 (9) AC = − 20 ⋅ log ⋅ ⋅ FB   G R 2 πF C VO  C  (1  For the power transistor inside the SC4525C, the GPWM CA +S s R ESR C O )O Vo = compensator zero, F ,2 between 10% and (3) Place the conduction loss PC, the switching loss PSW, and bootstrap 2 Vc (1 + s / ωp )(1 + s / ωn Q +Z1 / ωn ) s 1 1 1 . 0 loss P = c + be + P + P frequency, FC. ⋅ 20% of the crossover c⋅ircuitP= 15 .BST,PCan PSWestimated as follows: BST Q AC = − 20 ⋅ log  TOTAL 9 dB −3 3 −6 3 .3  2 π ⋅ 80 ⋅ 10 ⋅ zero, (4) Use the compensator pole,⋅FP1, to cancel the ESR 22 ⋅ 10  28 ⋅ 6 . 1 10 FZ. R 1 1 PQ = VIN ⋅ 2mA GPWM ≈ , ω≈ , ωZ = , PC = D ⋅ VCESAT ⋅ IO (5) Then, the parameters of the p R C compensation network C GCA15⋅.9 S R R ESR O O 10 by can be calculated 20 1 R7 = = 22 . 3 k AC PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW (10) 0 . 28 ⋅ 10 −3 20 2 10 R7 = 1 C 5 = gm = 0 . 45 nF I 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 PBST = D ⋅ VBST ⋅ O 1 40 C5 = 1 C 8 = 2 πFZ1 R 7 3 = 12pF 2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 where P BST is1 − D) ⋅ V ⋅ I voltage and tS is the equivalent V = ( the BST supply D DO 1 switching time of the NPN transistor (see Table 4). C8 = 2 πFP1 R 7 GPWM (1 + s gain of Vo =0.3mA/V is the EA R ESR C O )the SC4525C. where gm= PIND = (1 .1 ~ 1 .3 ) ⋅ I2 ⋅ R DC O 2 2 Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) 14 1 SC4525C Applications Information (Cont.) Table 4. Typical switching time Input Voltage 12V 24V 28V 1A 1A 12.5ns 22ns 25.3ns Load Current 2A 3A 15.3ns 18ns 25ns 28ns 28ns 31ns PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4525C, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. V IN + PBST + Paddition, the quiescent current loss is In Q PQ = VIN ⋅ 2mA (11) The total power loss of the SC4525C is therefore ⋅ I O ⋅ FSW PTOTAL = PC + PSW + PBST + PQ O (12) 0 IO The temperature rise⋅ of the SC4525C PQtheVIN ⋅ 2mA of the is = product PC = D ⋅ VCESAT IO total power dissipation (Equation (12)) and qJA (36oC/W), which is the thermal impedance from junction to ambient 1 for thePSW = 2 EDP⋅package. SW SOIC-8 ⋅ t S VIN ⋅ I O ⋅ F I ) ⋅ I2 ⋅ R DCt is not recommended to operate the SC4525C above I O PBST = D ⋅ VBST ⋅ O 40 125oC junction temperature. PD = (1 − D) ⋅ VD ⋅ IO PIND = (1 .1 ~ 1 .3 ) ⋅ I2 ⋅ R DC O VOUT ZL Figure 9. Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized. 15 SC4525C Recommended Component Parameters in Typical Applications Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 5. Recommended inductance (L1) and compensator (R7, C5, C8) Vin(V) Typical Applications Vo(V) Io(A) Fsw(kHz) 1.5 2.5 12 3.3 5 7.5 10 1.5 2.5 3.3 24 5 7.5 10 3 3 500 500 1000 500 1000 500 1000 500 1000 500 300 500 500 1000 500 1000 500 1000 500 C2(uF) L1(uH) 47 47 3.3 4.7 2.2 6.8 3.3 6.8 3.3 6.8 3.3 3.3 6.8 6.8 6.8 3.3 8.2 4.7 10 4.7 15 Recommended Parameters R7(k) C5(nF) C8(pF) 5.23 8.45 15.4 12.1 20.5 15.4 36.5 22.6 47.5 36.5 3.57 6.49 12.1 22.6 15.4 30.9 26.1 52.3 30.9 3.9 3.9 0.82 3.9 0.82 3.9 0.82 3.9 0.82 3.9 3.9 3.9 3.9 0.82 3.9 0.82 3.9 0.82 3.9 Snubber no 22 1 +220pF no 16 SC4525C Typical Application Schematics V 24V C4 4. 7m F D3 18 V Zener IN BST SW SS/ EN D1 1N 4148 IN C1 0. 33 m F L1 6. 8 m H R4 33. 2k OUT 1. 5V/ 3 A SC 4525C FB COMP C7 22 nF R7 3. 57k ROSC GND D2 B 330A R6 66. 5k C2 47 m F C8 22 pF R5 69. 8k C5 3. 9 nF L1 : Coiltronics DR74 - 6R8 C2 : Murata GRM 31 CR60J 476 M C4 : Murata GRM 32 ER71H 475 K Figure 10. 300kHz 24V to 1.5V/3A Step-down Converter V IN 10 V – 26V C4 4. 7m F C1 0. 33 m F D1 1 N 4148 L1 OUT IN BST SW Fig10 : 300 kHz24 V to .35mV/ 3R4 A StepA Down Conv 1 .3 H -3.3 V/ 3 SS/ EN SC 4525 C R0 1 33.2k FB COMP C7 22 nF R7 22.6 k C5 0.82 nF ROSC GND D2 B330 A R6 14.3 k C2 47mF C8 22 pF R5 15. 8 k C0 220pF L1 : Coiltronics DR74 - 3 R3 C2 : C4 : Murata GRM 31 CR60J 476 M Murata GRM 32 ER71H 475 K Figure 11. 1MHz 10V-26V to 3.3V/3A Step-down Converter 17 SC4525C SS Typical Performance Characteristics SS270 REV 6-7 (For A 12V to 5V/3A Step-down Converter with 1MHz Switching Frequency) Load Characteristic 6 5 Output Voltage (V) 4 3 12V Input (5V/DIV) 5V Output (2V/DIV) 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 SS Voltage (1V/DIV) Load Current (A) 10ms/DIV Figure 12(a). Load Characteristic OCP Figure 12(b). VIN Start up Transient (IO=3A) 5V Output Short (5V/DIV) 5V Output Response (500mV/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV 20ms/DIV Figure 12(c). Load Transient Response (IO= 0.3A to 3A) Figure 12(d). Output Short Circuit (Hiccup) 18 SC4525C Outline Drawing - SOIC-8 EDP A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A A1 C A-B D e D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .069 .005 .065 .020 .010 .193 .197 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 .053 .000 .049 .012 .007 .189 .150 1.35 0.00 1.25 0.31 0.17 4.80 3.80 C bxN bbb F 1.75 0.13 1.65 0.51 0.25 4.90 5.00 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0° 8° 0.10 0.25 0.20 h EXPOSED PAD H H GAGE PLANE 0.25 h c L (L1) 01 SEE DETAIL SIDE VIEW NOTES: 1. 2. 3. 4. A DETAIL A CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES ). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS . REFERENCE JEDEC STD MS -012, VARIATION BA . 19 SC4525C Land Pattern - SOIC-8 EDP E D SOLDER MASK DIMENSIONS DIM (C) F G Z Y THERMAL VIA Ø 0.36mm NOTES: 1. P X C D E F G P X Y Z INCHES (.205) .134 .201 .101 .118 .050 .024 .087 .291 MILLIMETERS (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 2. 3. 20 SC4525C © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. 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