SC4525D

SC4525D POWER MANAGEMENT Features            18V, 3A, 350kHz Step-Down Switching Regulator Description The SC4525D is a 350kHz constant frequency peak current-mode step-down switching regulator capable of producing 3A output current from an input ranging from 3V to 18V. The SC4525D is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4525D achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4525D is available in SOIC-8 EDP package. Input range: 3V to 18V 3A Output Current 350kHz Fixed Switching Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications       XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs 12 Fig.1b: 350kHz 10-16V to 5V/3A Step-Down Converter (Front Page Efficien SC4525A Typical Application Circuit 10 V – 16V C4 10m F D1 1 N 4148 C1 0. 33 m F L1 10 m H R4 33. 2k V IN 90 85 OUT 5V/ 3A Efficiency IN BST SW 80 VIN =12V Efficiency (%) 75 70 65 60 55 50 45 40 SS / EN SC4525D FB COMP C7 22 nF C8 47pF R7 11. 5k RSET GND D2 20 BQ 030 R6 8. 25k C2 47m F R5 60.4 k C5 2. 2 nF L 1 : Coiltronics CD1 - 100 C2 : Murata GRM 31 CR60J 476 M C4 : Murata GRM 31 CR61E 106 K 0 0.5 1 1.5 2 2.5 3 Load Current (A) Figure 1. 350kHz 10V -16V to 5V/3A Step-down Converter Jan. 13, 2011 www.semtech.com 1 Efficiency of the 1MHz 10V-28V to 5V/3A Step-Down Converter (Front Pag Fig. 1a : 350 kHz10- 16 V to5V/ 3 A Step V - Down Converter Front Page Schematic ( ) SC4525D Pin Configuration Ordering Information Device SC4525DSETRT(1)(2) SW IN RSET GND 1 2 3 4 9 8 7 6 5 BST FB COMP SS/EN Package SOIC-8 EDP Evaluation Board SC4525DEVB Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) © 2011 Semtech Corp. www.semtech.com 2 SC4525D Absolute Maximum Ratings VIN Supply Voltage ……………………………… -0.3 to 24V BST Voltage ……………………………………………… 40V BST Voltage above SW …………………………………… 24V SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to VIN SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Peak IR Reflow Temperature …………………………. 260°C ESD Protection Level(2) ………………………………… 2000V Thermal Information Junction to Ambient (1) ……………………………… 36°C/W Junction to Case (1) ………………………………… 5.5°C/W Maximum Junction Temperature……………………… 150°C Storage Temperature ………………………… -65 to +150°C Lead Temperature (Soldering) 10 sec ………………… 300°C Recommended Operating Conditions Input Voltage Range ……………………………… 3V to 18V Maximum Output Current ……………………………… 3A Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, RSET = 60.4kΩ. Parameter Input Supply Input Voltage Range VIN Start Voltage VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown Conditions Min 3 Typ Max 18 Units V V mV VIN Rising 2.70 2.82 225 2.95 VCOMP = 0 (Not Switching) VSS/EN = 0, VIN = 12V 2 40 2.6 52 mA µA Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Pin to Switch Current Gain COMP Maximum Voltage COMP Source Current COMP Sink Current VIN = 3V to 18V VFB = 1V, VCOMP = 0.8V 0.980 1.000 0.005 -170 300 60 15.2 -340 1.020 V %/V nA µΩ-1 dB A/V V µA VFB = 0.9V VFB = 0.8V, VCOMP = 0.8V VFB = 1.2V, VCOMP = 0.8V (Note 1) ISW = -3.9A 3.9 2.35 17 25 Internal Power Switch Switch Current Limit Switch Saturation Voltage 5.1 380 6.6 600 A mV © 2011 Semtech Corp. www.semtech.com 3 SC4525D Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, RSET = 60.4kΩ. Parameter Minimum Switch On-time Minimum Switch Off-time Switch Leakage Current Minimum Bootstrap Voltage BST Pin Current Conditions Min Typ 150 100 Max 150 10 Units ns ns µA V mA ISW = -3.9A ISW = -3.9A 1.8 100 2.3 150 Oscillator Switching Frequency Foldback Frequency RSET = 60.4kΩ RSET = 60.4kΩ, VFB = 0 275 35 350 65 425 100 kHz kHz Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current Soft-start Discharging Current Hiccup Arming SS/EN Voltage Hiccup SS/EN Overload Threshold Hiccup Retry SS/EN Voltage 0.2 0.3 1.2 1.9 1.6 2.4 1.5 3.2 0.4 1.4 V V µA µA V V 1.2 V VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V VSS/EN Rising VSS/EN Falling VSS/EN Falling 0.95 2.15 1.9 0.6 1.0 Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: Switch current limit does not vary with duty cycle. 165 10 °C °C © 2011 Semtech Corp. www.semtech.com 4 SC4525D Pin Descriptions SO-8 1 2 3 4 Pin Name SW IN RSET GND Pin Function Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. Connect a 60.4kW resistor from this pin to ground. Ground pin Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. 5 SS/EN 6 7 8 9 COMP FB BST Exposed Pad © 2011 Semtech Corp. www.semtech.com 5 SC4525D Block Diagram IN COMP 6 SLOPE COMP 2 + + EA + S + + ISEN 3.53m W OC + ILIM 18mV BST FB 7 V1 + PWM FREQUENCY FOLDBACK 8 S R Q POWER TRANSISTOR ROSC 3 OSCILLATOR CLK 1.2V - R R SS/EN 5 1V 1.9V FAULT REFERENCE & THERMAL SHUTDOWN SOFT START AND OVERLOAD HICCUP CONTROL OVERLOAD A1 + 1 SW PWM GND 4 Figure 2. SC4525D Block Diagram 1.9V IC 2.4mA B4 + B1 S Q R OVERLOAD SS/EN 1V/2.15V B2 FAULT ID 3.9mA _ Q S R OC PWM B3 Figure 3. Soft-start and Overload Hiccup Control Circuit © 2011 Semtech Corp. www.semtech.com 6 f (2) 5Vin Eff Typical Characteristics Efficiency V O=3.3V V O=2.5V (3) 3.3Vin Eff SC4525D SC4525B SC4525B 90 85 80 75 70 65 60 55 50 45 40 0 0.5 1 90 85 80 75 70 65 60 55 50 45 40 3 Efficiency V O=3.3V V O=2.5V V O=1.5V 90 85 80 Efficiency V O=2V Efficiency (%) Efficiency (%) Efficiency (%) 75 70 65 60 55 50 40 VIN=3.3V D2 =B320A V O=1V V O=1.5V emp (5) Freq vs Temp 1.5 2 2.5 Load Current (A) SS270 REV 6-7 VIN=12V D2 =B320A (6) Foldback Freq vs Temp 45 0 0.5 1 1.5 2 2.5 3 0 0.5 1 Load Current (A) SS270 REV 6-7 VIN=5V D2 =B320A 1.5 2 2.5 3 Load Current (A) SS270 REV 6-7 Feedback Voltage vs Temperature 1.02 VIN = 12V 1.01 1.00 0.99 0.98 0.97 -50 SS270 REV 6-7 -25 0 25 50 75 o Frequency vs Temperature 1.2 Foldback Frequency vs VFB 1.25 1 0.75 0.5 TA=25oC 0.25 0 0.00 Normalized Frequency 1.1 1.0 (8) OCP current 100 125 0.9 (9) BST Pin current -50 -25 0 25 50 75 100 125 Temperature (OC) 0.8 Normalized Frequency VFB (V) 0.20 0.40 0.60 0.80 1.00 Temperature ( C) VFB (V) SS270 REV 6-7 500 450 Switch Saturation Voltage v s Switch Current Switch Current Limit vs Temperature 5.2 4.8 100.0 BST Pin Current vs Switch Current VIN = 12V VBST =15V VCESAT (mV) 350 300 250 200 150 100 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Switch Current (A) 25oC -40oC 4.4 4.0 3.6 3.2 -50 -25 0 25 50 o BST Pin Current (mA) 400 125 C o Current Limit (A) 75.0 50.0 -40oC 125oC 25.0 0.0 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4 Temperature ( C) Switch Current (A) © 2011 Semtech Corp. www.semtech.com 7 shold vs temp Vin Sup Cur vs SS volt 12 (11) Curve Typical Characteristics (Cont.) SS270 REV 6-7 SC4525D SS270 REV 6-7 SS270 REV 6-7 VIN T hresholds vs Temperature 3.0 2.9 Start 2.5 2.0 VIN Supply Current vs Soft-Start Voltage 125oC -40oC 50 40 VIN Shutdown Current vs VIN VSS = 0 -40oC VIN Threshold (V) Current (mA) Current (uA) 2.8 2.7 2.6 2.5 2.4 -50 -25 0 25 50 75 100 125 Temperature (o C) 1.5 1.0 30 20 125oC 0.5 (14) SS shutdown threshold vSS charge cur vs 10 volt (15) s temp SS 0.0 0 0.5 1 VSS (V) SS270 REV 6-7 SS270 REV 6-7 UVLO 0 1.5 2 0 2 4 6 8 10 12 14 16 18 VIN (V) SS270 REV 6-7 VIN Quiescent Current vs VIN 2.5 2.0 125oC 0.40 SS Shutdown Threshold vs Temperature Soft-Start Charging Current vs Soft-Start Voltage 0.0 -0.5 Current (mA) Current (uA) -40 C 1.5 1.0 0.5 VCOMP = 0 0.0 0 2 4 6 8 10 12 14 16 18 VIN (V) SS Threshold (V) o 0.35 -1.0 -1.5 -2.0 -2.5 0.20 -50 -25 0 25 50 o 125oC 0.30 -40oC 0.25 -3.0 75 100 125 0 0.5 1 VSS (V) 1.5 2 Temperature ( C) © 2011 Semtech Corp. www.semtech.com 8 SC4525D Applications Information Operation The SC4525D is a 350kHz fixed frequency, peak currentmode, step-down switching regulator with an integrated 3.9A power NPN transistor. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 3.53mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. Shutdown and Soft-Start Table 2: Fault conditions and protections The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4525D is summarized in Table 1. Table 1: SS/EN operation modes SS/EN SS/EN 2.15V Mode Shutdown Not switching Switching & hiccup disabled Switching & hiccup armed Supply Current 18uA @ 5Vin 2mA Load dependent Condition Condition IL>ILimit, V FB>0.8V IL>ILimit, V FB O IO C IN =capacitor should be chosen to handle the RMS The input 4 20 % ⋅ I⋅ F⋅ FSW DI SW IRMS _ CIN⋅ = VIN⋅ O D ⋅ (1 − D) O ripple current of a buck converter. This value is given by IRMS _ CIN = I O ⋅ D ⋅ (1 − D) (5)   1 DV = DIL ⋅  ESR + The inputOcapacitance must F ⋅ be high enough to keep also C   8 ⋅ SW O    input ripple voltage within specification. This is important   1 in reducing the ⋅conductive EMI from the regulator. The  DVO = DIL  ESR +    input capacitance can be8 ⋅ FSW ⋅ C O from estimated  C IN > IN IO 4 ⋅ DVIN ⋅ FSW 4 ⋅ DVIN ⋅ FSW (6) + VFB  1 where DV logthe 1 VD ⋅ AC = − 20=⋅IN is  VO allowable input ripple voltage. D  G R 2 πF C ⋅ V   O VIN  VD − SVCESAT C O + CA CESAT Multi-layer ceramic capacitors, which have very low ESR (a R= 1 1 1 few mW) and can easily handle high RMS ripple current, are. 0  7 AC = − 20 ⋅ log ⋅ ⋅   = 15 3 6 the ideal choice + ⋅ 6input− − 3) 2 π ⋅ A single 4.7µF10 −10µF. 3  3  28 V ⋅ 10 D ( VO forD .)1 (⋅1 filtering. 80 ⋅ 10 ⋅ 22 ⋅ to DIL = capacitor is adequate for most applications. C 5 = X5R ceramic F ⋅L For high voltage SW 1 applications, a small ceramic (1µF or 15 . 9 20 2.2µF) can beplaced in parallel with  low ESR electrolytic C = 10 VFB a 1 R7 = 8 ( − = 22 . 3 k 1 O  Acapacitor⋅=10  3+ VD ) ⋅bothD) ESR and bulk capacitance toVsatisfy (⋅1 − the ⋅ C = − .20 ⋅log 0 28 L1  VO   G CAR O 2 πF C 20 % requirements. 1 ⋅ IS ⋅ FSW C O C5 = = 0 . 45 nF 2 π ⋅ 16 ⋅ 10 3 ⋅ 2211 ⋅ 10 3 . 1 1 . 0  Vo  AOutput Capacitor ⋅ ⋅ =  = 15 C = − 20 ⋅ log IRMS _ CIN = I1⋅ ⋅6 . 1 ⋅⋅10 −3D)2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 3 . 3  Vc 28O D (1 −  C8 = = 12pF The output ripple voltage10 3O of a buck converter can be 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ DV expressed as 15 . 9 10 20 GPWM R7 = =  . 3k 22  1 G− Vo 0 . 28 ⋅ 10PWM (⋅1 ESR ESR C O )  DVO = D3IL  + s R + (7)  = 8 ⋅ F 2 ⋅ C2   Vc (1 + s / ωp )(1 + s / ωn Q + sSW/ ωnO)  VFB 1 = 0 . 45  C 5 = − 20 ⋅ log 3 1 ⋅  AC = 2 πC16s ⋅the output capacitance. nF where ⋅ O i 10 ⋅ 22 . 1 ⋅ 10 3  G R 2 πF C ⋅ V   R7 = CO O  CA S R 1V 1 1 G8 = − the inductor ⋅ ωp1 =⋅12pF ,FB  ωZ = , CSince 20 ⋅ log, 31 ripple≈3current DIL increases as D APWM ≈ G ⋅ R  IO 1 C = 2 π⋅ 600 ⋅   ripple voltage Ois . 0 C = R ESR C 1  G CAR S 2 ⋅ 10 O C IN ⋅>(Equation .(3)),FC CR Coutput 1 CA S10 ⋅ 22 1 π the OV d = − 20 O ACecreases log⋅ DV ⋅ F ⋅ 5  = 15 3 −6 4  28 IN6 SW − 3 ⋅ 3 .3  ⋅ when  therefore the highest. 1 ⋅ 10 VIN i2 π ⋅ 80 maximum. 10 s at its ⋅ 10 ⋅ 22 ⋅ AC 10 20 1 1 .0 RoC = − 20 ⋅ log (1 + s 1 ESR C O ) ⋅ G R V7 = A 22µF to 47µF X5R ceramic capacitor is found adequate C 815 A = gm 15 .9PWM ⋅ 6 . 1 ⋅ 10 − 3 2 2 π 2 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 ⋅ 3 . 3  = 28 ⋅ Vfor output 20 p(1 + s inωn Q + s / ωn ) (1 +10/ ω ) s filtering / most applications. Ripple current  c R7 = = 22 . 3 k −3 1 n the output Ci5 = 0 . 28 ⋅ 10 capacitor is not a concern because the 2 πF 115 .9 R inductorZR 20 7 1 of a buck converter directly feeds CO, current 1 1 C = 10 RPWM Gr75 = ≈ π ⋅1 in⋅ 10 3=⋅ 22 ..3 k⋅ 10≈ =current. AvoidZ using Z5U ω 3 0 .,45 nF ω= , esulting16 very 22 1 ripple 2 28 R , 0 .GCA⋅⋅10 −3 low p R C O S Cand Y5V ceramic capacitors for output filtering R ESR C O 8= because 2 πFP1 R 7 11 Ct5 = types of capacitors have=high temperature and high 0 .12pF 45 nF hese AC = 3 3 8= 2 π⋅ 600 ⋅ 10 ⋅ ⋅ 22 ⋅ ⋅ 10 10π20 16 ⋅ 10 3 22 . 1. 110 3 2 R voltage coefficients. = 7 gm 1 C8 = = 12pF Freewheeling Diode . 1 ⋅ 10 3 2 π⋅ 600 ⋅ 10(3 ⋅+ s R C ) GPWM 1 22 ESR O Vo 1 = C5 = 2 Vc 21 + s / ωp )(1barrier n Q + s 2 / ωn ) ( πF R Use of Schottky + s / ω diodes as freewheeling rectifiers Z1 7 GPWM reverse recovery input current spikes, Vo reduces1 diode (1 + s R ESR C O ) = Ceasing + s / ω )(1 + s / ω Q + s 2 / ωin the SC4525D. These = (1 high-side current sensing 2 ) 8 Vc n Rp 1n 1 R GPWM2≈πFshould, have an ωp ≈ ωZ = , diodes P1 7 average ,forward current rating GCA ⋅ R S RCO R ESR C O at least 3A and a reverse blocking voltage of at least a 1 1 few ≈ AC R , GPWM volts higher than the ≈ ωp input ,voltage. For = ωZ switching , 20 10 RCO egulators R S ESR C O Rr7 = GCA ⋅operating at low duty cycles (i.e. lowRoutput gm voltage to input voltage conversion ratios), it is beneficial AC to use 201 10 freewheeling diodes with somewhat higher Ra5 = C7verage current ratings (thus lower forward voltages). This = gm 2 πFZ1 R 7 C5 = 8= 1 2 πFZ1 R 7 2 πFP1 7 www.semtech.com 11 IO © 2011 C > Semtech Corp. SC4525D Applications Information (Cont.) is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diode should be placed close to the SW pin of the SC4525D to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B320A, B330A (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and CMSH3-40MA (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4525D on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor For the bootstrap circuit, a fast switching PN diode (such as 1N4148 or 1N914) and a small (0.33µF – 0.47µF) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D1. If VOUT > 8V, then a protection diode D4 between the SW and the BST pins will be required as shown in Figure 6 (c). D4 can be a small PN diode such as 1N4148 or 1N914 if the operating temperature does not exceed 85 ºC. Use a small Schottky diode (BAT54 or similar) if the converter is to operate up to 125 ºC. D1 Fig.6: Methods of BST The minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about 2V at room temperature. The BST-SW voltage is supplied by a bootstrap circuit powered from either the input or the output D1 the of converter (Figure 6(a), 6(b) and 6(c)). To maximize efficiency, tie the bootstrap diodeBST the converter output to C1 if VO>2.5V as shown in Figure 6 (a). Since the bootstrap VIN VOUT SW supply current is proportional to the converter load IN to power the bootstrap s Temp current, using a lower voltageSC4525D D2 GND circuit reduces driving loss (Equation (11), page 14) and iSS270 REV 6-7 mproves efficiency. 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -50 -25 0 25 50 75 100 125 Temperature (o C) ISW =-3.9A BST VIN IN SW C1 VOUT SC4525D 12 D1 GND D2 (a) BST VIN C1 VOUT IN SW SC4525D GND D2 Minimum Bootstrap Voltage (a) vs Temperature (b) D4 D1 BST VIN IN SW C1 VOUT>8V Voltage (V) SC4525D GND D2 D4 is either a pn juntion diode or a Schottky diode depending on the operating temperature. (C) Figure 6. Methods of Bootstrapping the SC4525D Figure 5. Typical Minimum Bootstrap Voltage required to Saturate the Transistor (ISW= -3.9A) © 2011 Semtech Corp. www.semtech.com 12 = ( VO + VD ) ⋅ (1 − D) FSW ⋅ L 1 10 1 R 7 = 0 . 28 ⋅ 10 −3 = 22 . 3 k C8 = = 12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 1 C5 = = 0 . 45 nF 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 SC4525D GPWM (1 + s R ESR C O ) Vo 1 = C= = 12pF 2 ( VO + VD ) ⋅ (1 − D) Vc (1 + s / ωp )(1 + s 8 ωn2 π⋅ 600 ω10 3 ⋅ 22 . 1 ⋅ 10 3 / Q+ s2 / ⋅ n ) 20 %Applications Information (Cont.) ⋅ IO ⋅ FSW Loop Compensation R G, Vo ωp ≈ 1 PWM (1 + s R ESRZC= ) 1 , GPWM ≈ , ωO  = 2 GCA ⋅ R S R/C O )(1 + s / ω Q + sR ESR C2O) Vc (1 + s ωp / ωn _ CIN = I ⋅ D ⋅ (1 − D) O n ⋅ C O  The goal of compensation is to shape the frequency W  A response of the converter so C as to achieve high DC a dominant low-frequency pole FP at 10 20 accuracy and fast transient response while maintaining R7 = R 1 1 gm GPWM ≈ , ωp ≈ , ωZ = , l oop stability.  1 GCA ⋅ R S RCO R ESR C O  = DIL ⋅  ESR +  1 8 ⋅ FSW ⋅ C O    C= 5 AC The block diagram in Figure 7 shows the control loops of a and double poles at half the switching frequency. 2 πFZ1 R 7 10 20 buck converter with the SC4525D. The inner 7 = (current R loop 1 gm loop) consists of a current sensing resistor (Rs=3.53mW) Including the voltage divider (R4 and R6), the control to C8 = of control loop 2 πwith 7 FP1 R gain (G =18.5). The feedback transfer function is found and plotted in Figure Iand a current amplifier (CA) CA 1 O > C 5 = amplifier outer loop (voltage loop) consists of an error 2 πF R 8 as the converter gain. 4 ⋅ DVIN ⋅ FSW Z1 7 (EA), a PWM modulator, and a LC filter. 1 Since the converter gain has only one dominant pole at C8 = 2 πFP1 R 7 Since the current loop is internally closed, the remaining low frequency, a simple Type-2 compensation network task for the loop compensation is to design the voltage is sufficient for voltage loop compensation. As shown in compensator (C5, R7, and C8). Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole CONTROLLER AND SCHOTTKY DIODE at FP1. The integrator is used to boost the gain at low Io frequency. The zero is introduced to compensate the Rs CA Fig.8: Bode plot of loop gains phase lag at the loop gain crossover due to the excessive integrator pole (-90deg) and the dominant pole (-90deg). REF 1 VFB  1 + 1  Vc  AC = −EA20 ⋅ log MODULATOR⋅ = − 20 ⋅ log 1 ⋅ ⋅ VFB  PWM The high frequency pole nulls the ESR zero and attenuates AC  G CAR S 2 πFC C O ⋅ VO  FB  G R 2 πFC C O VO  L1  Vo  CA S  SW high frequency noise. 12 Vramp 1 1  1 1 R4 Co AC = − 20 ⋅ log ⋅  C5 AC = − 20 ⋅ log −3 ⋅ −3 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6  28 ⋅ 6 1 ⋅ 10 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6  28 ⋅ 6 ..1 ⋅ 10 C8 COMP R7 Resr R6 1 .0  ⋅ 1 . 0  = 15 9 dB  ⋅ 3 . 3  = 15 ..9 dB 60  3 .3  30 GAIN (dB) Fz1 Fp1 20 10 15 .9 20 R 7 = 10 = = 22 3 k R7 = 22 ..3 k 0 28 ⋅ 10 −3 0 ..28 ⋅ 10 −3 1 Figure 7. Block1 diagram of control loops C5 = = 0 45 nF C5 = = 0 ..45 nF 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 1 ⋅ 10 3 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 ..1 ⋅ 10 3 For a converter with switching frequency FSW, output 1 1 inductance L1, output capacitance CO = nd pF a 12 loading R, the C8 = = 12 pF C8 = 3 3 3 2 π⋅ 600 ⋅ 10 3 ⋅ transfer function in Figure 7 is control (VC) 2 π⋅output (VO)⋅ 22 ..1 ⋅ 10 to 600 ⋅ 10 22 1 ⋅ 10 given by: 15 . 9 CO MP EN SA TO 0 Fp CO NV ER T ER RG AIN Fc GA IN LO OP G AIN -30 Fz -60 0.2K Fsw/2 2K G (1 + s R ESR C O ) Vo GPWM (1 + s R ESR C O ) Vo = = (1 + s / ωPWM + s / ω Q + s 2 / ω2 ) 2 2 Vc p )(1 n n Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) This transfer function has a finite DC gain 20K FREQUENCY (Hz) 200K 2M (8) Figure 8. Bode plots for voltage loop design R GPWM ≈ R GPWM ≈ G ⋅ R ,, CA S GCA ⋅ R S A an ESR zero FZ aCt AC 10 20 10 20 R7 = R7 = g m gm 1 ωp ≈ 1 ωp ≈ R C ,, O RCO 1 Therefore, the procedure of the voltage loop design for ωZ = 1 the SC4525D can be summarized as: = ωZ R C ,, ESR O R ESR C O (1) Plot the converter gain, i.e. control to feedback transfer function. www.semtech.com 13 © 2011 Semtech Corp. C5 = C5 = 1 1 1 VFB  1 AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   CO O  CA S 1 Applications⋅ Information −(Cont.) AC = − 20 log ⋅  3 SC4525D 1 1 .0  ⋅  = 15 . 9 dB 3 −6 3 .3  2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10  28 ⋅ 6 . 1 ⋅ 10 (2) Select the open loop crossover frequency, FC, between 10% and 20% of the switching frequency. At FC, find the 7 15 . 9 10 20 20 required compensator gain, AC. In typical applications with 10 R7 = = 7. 4 k R= = 22 . 3 k 0. 3 ⋅ 10 − 3 −3 ceramic 7output capacitors, the ESR zero is neglected and 0 . 28 ⋅ 10 the required compensator gain at FC can be estimated by 1 1 C5 = = 3.1 nF C5 = = 0 . 45 nF 3 3 3 2π ⋅ 7 ⋅ 10 ⋅ 7. 4 ⋅ 10 3 2 π ⋅ 16 ⋅ 10 122 . 1 ⋅ 10 ⋅ VFB  1 (9) AC = − 20 ⋅ log  G R ⋅ 2 πF C ⋅ V   1 1 CO O  CA S C8 = = 32 pF C8 = = 12pF 2 π ⋅ 677⋅ 10 3 ⋅ 7. 4 ⋅ 10 3 3 3 2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 1 1 1 .0  (3) Place = − 20 ⋅ log the compensator zero, FZ1,⋅ between 10% and AC ⋅   = 15 . 9 dB −3 3 −6 3 .3 28 ⋅ 6 . 1 ⋅ 10 20% of the crossoverfrequency, FC. 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 SelectR7=7.32k, C5=3.3nF, and C8= 33pF for the design. GPWM (1 + s R ESR C O ) Vo = 2 2 / (4) UseVc compensator + s / ωFP1, + s cancel the ESR zero, the (1 + s 15 .9ωp )(1 pole, n Q to / ωn ) Compensator parameters for various typical applications 10 20 FZ. are listed in Table 4. A MathCAD program is also available R7 = = 22 . 3 k −3 upon request for detailed calculation of the compensator 0 . 28 ⋅ 10 R 1 1 (5) Then, the parameters of the p ≈ parameters. GPWM ≈ ,1 ω compensation network , ωZ = , GCA ⋅ R R 0. R ESR C O Ccalculated byS 3 = C O45 nF 5= can be 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 Thermal Considerations AC 1 20 C 8 = 10 = 12pF R7 = 2g ⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 π For the power transistor inside the SC4525D, the m conduction loss PC, the switching loss PSW, and bootstrap 1 circuit PT OT ALBST,Pcan PS W + PB S T + Pas follows: loss P = C + be estimated Q C5 = GPWM Vo 2 πFZ1 R 7 (1 + s R ESR C O ) (10) = 2 Vc (1 + s / ωp )(1 + s / ωn Q + s 2 / ωn ) 1 PQ = VIN ⋅ 2mA PC = D ⋅ VC E S AT⋅ IO C8 = 2 πFP1 R 7 1 R 1 1 GPWM ≈ , ωp ≈ , ωZ = , PS W = ⋅ t S ⋅ VIN ⋅ I O ⋅ FS W (11) 2 GCA ⋅ R S RC R ESR C O where gm=0.3mA/V is the EA gain of theOSC4525D. I AC PB S T = D ⋅ VB S T ⋅ O 20 10 Example: Determine the voltage compensator for an 40 R7 = 350kHz, 12Vgm 3.3V/3A converter with 47uF ceramic to output capacitor. where P BST is1 − D) ⋅ V ⋅ I voltage and tS is the equivalent V = ( the BST supply 1 D DO C5 = switching time of the NPN transistor (see Table 3). 2 π gain Table Table 3: Typical Switching Time Choose a loopFZ1 R 7 crossover frequency of 35kHz, and place voltage compensator zero and pole at FZ1=7kHz Table 1 1 ~ 1 . 3 ⋅ I2 ⋅ R DC PIND = (3.. Typical)switching time 1 O C8 = (20% of FC), πFP1 R 7 = 677kHz. From Equation (9), the and FP1 2 Load Current Input Voltage 1A 2A 3A required compensator gain at FC is 1 1 1. 0   A C = − 20⋅ log  ⋅ ⋅  = 7 dB 18.5 ⋅ 3. 53 ⋅10 −3 2π ⋅ 35 ⋅ 103 ⋅ 47 ⋅ 10− 6 3. 3   5V 12V 6.86ns 12.5ns 9.71ns 15.3ns 12.5ns 18ns PT OT AL = PC + PS W + PB S T + PQ In addition, the quiescent current loss is Then the compensator parameters are PQ = VIN ⋅ 2mA P =D⋅ V ⋅I C C E S AT O (12) PS W = © 2011 Semtech Corp. The total power loss of the SC4525D is therefore 1 ⋅ t S ⋅ VIN ⋅ I O ⋅ FS W 2 www.semtech.com 14 IO SC4525D Applications Information (Cont.) PT OT AL = PC + PS W + PB S T + PQ (13) The temperature rise⋅of the SC4525D PQtheVproduct of the is = IN ⋅ 2mA PC = D ⋅ VC E S AT IO total power dissipation (Equation (13)) and qJA (36oC/W), which is the thermal impedance from junction to ambient 1 for thePS W = 2 EDP⋅package. S W SOIC-8 ⋅ t S VIN ⋅ I O ⋅ F V IN I It is not recommended to operate the SC4525D above PB S T = D ⋅ VB S T ⋅ O o 40 125 C junction temperature. PCB Layout1Considerations PD = ( − D) ⋅ VD ⋅ IO In a step-down switching regulator, the input bypass PIND = (1 . 1 ~ 1 3 ) ⋅ I2 switch and the freewheeling capacitor, the main .power⋅ R DC O diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4525D, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. VO UT ZL Figure 9. Heavy lines indicate the critical pulse current loop. Thes stray inductance of this loop should be minimized. Vin Vin C + + © 2011 Semtech Corp. www.semtech.com 15 SC4525D Recommended Component Parameters in Typical Applications Table 4 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 4: SC4525D Compensator Parameters Typical Applications Vo(V) Io(A) Table 4. Recommended inductance (L1) and compensator (R7, C5, C8) Vin(V) 3.3 5 12 1.0 2.0 1.5 2.5 3.3 1.5 2.5 3.3 5 7.5 C2(uF) L1(uH) 3 47 3.3 2.2 3.3 4.7 4.7 4.7 6.8 8.2 10 10 Recommended Parameters R7(k) C5(nF) C8(pF) 3.74 6.49 3.74 6.49 7.5 3.74 6.98 8.66 11.5 18.2 6.8 3.3 6.8 4.7 3.3 6.8 4.7 3.3 2.2 2.2 47 68 82 68 47 7.15 12.4 7.15 12.4 14.3 7.15 13.3 16.5 22.1 34.8 R7 © 2011 Semtech Corp. www.semtech.com 16 SC4525D Typical Application Schematics V IN 5V C4 4.7m F D1 BAT- 54 C1 0. 33m F L1 4.7m H R4 33.2k IN BST SW OUT 2.5V/3A SS / EN SC 4525 D FB COMP C7 22 nF C8 47 pF R7 6. 49 k RSET GND D2 CMSH3-20M R6 22 .1k C2 47m F R5 60.4k C5 4.7nF L1 : Coiltronics DR73 - 4R7 C2 : Murata GRM 31CR60J 476 M C4 : Murata GRM 31CR60J 475 K Figure 10. 350kHz 5V to 2.5V/3A Step-down Converter V IN 3.3V C4 4.7m F D1 BAT- 54 IN BST SW C1 0. 33 mF L1 1.5 A Fig . 10 : 350 kHz5 V to23.5V/3RA StepV/3Down Converte . 3 mH 4 SS/ EN OUT SC 4525 D 33.2k FB COMP C7 22nF C8 47pF R7 3. 74k C5 6.8nF RSET GND D2 B 320A R6 66.5 k C2 47m F R5 60.4k L1 : Coiltronics DR73 - 3R3 C2 : Murata GRM 31CR60J 476 M C4 : Murata GRM 32ER71H 475 K Figure 11. 350kHz 3.3V to 1.5V/3A Step-down Converter © 2011 Semtech Corp. www.semtech.com 17 Fig.12b: SS SC4525D Typical Performance Characteristics Load Characteristic 6 5 SS270 REV 6-7 (For A 12V to 5V/3A Step-down Converter with 350kHz Switching Frequency) Output Voltage (V) 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 12V Input (5V/DIV) 5V Output (2V/DIV) SS Voltage (1V/DIV) Load Current (A) Fig.12d: OCP Figure 12(a). Load Characteristic 5ms/DIV Figure 12(b). VIN Start up Transient (IO=3A) 5V Output Short (5V/DIV) 5V Output Response (1V/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV 10ms/DIV Figure 12(c). Load Transient Response (IO= 0.3A to 3A) Figure 12(d). Output Short Circuit (Hiccup) © 2011 Semtech Corp. www.semtech.com 18 SC4525D Outline Drawing - SOIC-8 EDP A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A A1 C A-B D e D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .069 .005 .065 .020 .010 .193 .197 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 .053 .000 .049 .012 .007 .189 .150 1.35 0.00 1.25 0.31 0.17 4.80 3.80 C bxN bbb F 1.75 0.13 1.65 0.51 0.25 4.90 5.00 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0° 8° 0.10 0.25 0.20 h EXPOSED PAD H H GAGE PLANE 0.25 h c L (L1) 01 SEE DETAIL SIDE VIEW NOTES: 1. 2. 3. 4. A DETAIL A CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES ). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS . REFERENCE JEDEC STD MS -012, VARIATION BA . © 2011 Semtech Corp. www.semtech.com 19 SC4525D Land Pattern - SOIC-8 EDP E D SOLDER MASK DIMENSIONS DIM (C) F G Z Y THERMAL VIA Ø 0.36mm NOTES: 1. P X C D E F G P X Y Z INCHES (.205) .134 .201 .101 .118 .050 .024 .087 .291 MILLIMETERS (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 2. 3. © 2011 Semtech Corp. www.semtech.com 20 SC4525D © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. 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