SC4612HEVB

SC4612H 40V Synchronous Buck Controller POWER MANAGEMENT Features           Description The SC462H is a high performance synchronous buck controller that can be configured for a wide range of applications. The SC462H utilizes synchronous rectified buck topology where high efficiency is the primary consideration. SC462H can be used over a wide input voltage range with output voltage adjustable within limits set by the duty cycle boundaries. SC462H comes with a rich set of features such as regulated DRV supply, programmable soft-start, high current gate drivers, shoot through protection, RDS(ON) sensing with hiccup over current protection. Wide input voltage range, 4.75V to 40V Internally regulated DRV .7A gate drive capability Low side RDS-ON sensing with hiccup OCP Programmable current limit Programmable frequency up to .2 MHz Overtemperature protected Pre-bias startup Reference accuracy ±% Available in MLPD-2 4 x 3 and SOIC-4 Pb-free packages. This product is fully WEEE and RoHS compliant Applications       Distributed power architectures Telecommunication equipment Servers/work stations Mixed signal applications Base station power management Point of use low voltage high current applications Typical Application Circuit March 24, 2009 © 2008 Semtech Corporation  SC4612H Ordering Information Part Number(3) SC462HMLTRT SC462HSTRT SC462HEVB() Package(2) MLPD-2 4 x3 SOIC-4 Temp. Range (TJ) -40°C to +25°C EVALUATION BOARD Notes: () When ordering please specify MLPD or SOIC package. (2) Only available in tape and reel packaging. A reel contains 3000 devices for MLPD package and 2500 for SOIC package.. (3) Pb-free product. This product is fully WEEE and RoHS compliant. Pin Configuration Marking Information 2 SC4612H Absolute Maximum Ratings VDD (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +45 PHASE to GND(V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +55 EAO, SS/EN, FB, OSC(V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5 Pin Voltage - All Other Pins (V) . . . . . . . . . . . . . . . -0.3 to +0 DRV Source Current (peak) (mA) . . . . . . . . . . . . . . . . . . . . . 00 ESD Protection Level() (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  Recommended Operating Conditions Supply Voltage Range (VDD) (V) . . . . . . . . . . . . . . . . 5 to +40 Thermal Information Rqja (SOIC)(2) (°C/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Rqja (MLPD)(2) (°C/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.3 Rqjc (SOIC) (°C/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Rqjc (MLPD) (°C/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +25 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +50 Ambient Temperature Range (°C) . . . . . . . . . . . -40 to +05 Peak IR Reflow Temperature (0s to 30s) (°C) . . . . . . . +260 Exceeding the Absolute Maximum Ratings may result in permanent damage to the device or device malfunction. Operation outside of the Recommended Operating Conditions is not recommended. NOTES: () Tested according to JEDEC standard JESD22-A4-B. (2) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. Electrical Characteristics Parameter Bias Supply Quiescent Current VDD Undervoltage Lockout Start Threshold UVLO Hysteresis Drive Regulator DRV Output Voltage Load Regulation Oscillator Operating Frequency Range Initial Accuracy() Maximum Duty Cycle Ramp Peak to Valley () Oscillator Charge Current Unless otherwise specified, TA = TJ = +25°C, VIN = VVDD=2V Symbol Conditions Min Typ Max Units IQ VVDD = 40V, No load, VSS/EN = 0V 5 7 mA VUVLO VUVLO-HYST 4.20 4.50 400 4.75 V mV VDRV 0V≤ VVDD ≤ 40V, IDRV ≤ mA mA≤ IDRV ≤ 70mA 7.3 7.8 8.3 00 V mV fOSC COSC=60pF (Ref only) VVDD=VDRV=8V; VOUT_NOM=5V; IOUT=0A; VVDD adjusted down to VOUT=0.99*VOUT_NOM VRAMP IOSC VOSC=V 00 540 82 850 90 600 200 660 kHz kHz % mV 0 mA 3 SC4612H Electrical Characteristics (continued) Parameter Current Limit - Low Side RDS(ON) Current Limit Threshold Voltage Error Amplifier TJ=0 to +70OC Feedback Voltage VFB TJ=-40 to + 85 C O Symbol Conditions Min Typ Max Units VCL 00 mV 0.495 0.492 0.488 0.500 0.500 0.500 0.505 0.508 0.52 200 V V V nA dB MHz mA mA V/ms TJ=-40 to +25OC Input Bias Current Open Loop Gain() Unity Gain Bandwidth Output Sink Current Output Source Current Slew Rate() SS/EN Disable Threshold Voltage Soft Start Charge Current Soft Start Discharge Current() Disable Low to Shut Down Hiccup Hiccup Duty Cycle Gate Drive Gate Drive On Resistance (H)(2) Gate Drive On Resistance (H)(2) DL/DH Source/Sink Peak Current DL/DH Rise/Fall Time(2) Minimum Non-Overlap Minimum On Time(2) Thermal Shutdown Shutdown Temperature(2) Thermal Shutdown Hysteresis (2) () (2) () IFB VFB=0.5V 60 7 Open Loop; VFB=0V Open Loop; VFB=0.6V 0 900 00  VSS-DIS ISS ISSD 25  50 500 mV mA mA ns CSS=0.uF; current limit condition  % ISOURCE=00mA ISINK=00mA C=2000pF C=2000pF tDEAD tON-MIN .4 3 3 .7 20 30 4 4 W W A ns ns 0 ns 65 5 O O C C NOTES: () Guaranteed by design, not production tested. (2) Guaranteed by characterization. (2) This device is ESD sensitive, use of standard ESD handling precautions is required. 4 SC4612H Typical Characteristics 5 SC4612H Typical Characteristics Startup from VOUT=0V Startup from VOUT=2.5V Startup from VOUT=2.5V, first DH/DL Pulses Short Circuit Applied Steady State, no load 6 SC4612H Pin Descriptions Pin # MLPD Pin # SOIC ,7 Pin Name NC Pin Function No Connection This pin can be used to modify the current limit threshold for the low side MOSFET RDS(ON) sensing. Once the voltage drop across the bottom MOSFET is larger than the programmed value, current limit condition occurs, and the hiccup current limit protection is activated. Oscillator Frequency set pin. An external capacitor to GND will program the oscillator frequency. See Table  “Frequency vs. C OSC “ to determine oscillator frequency. Soft Start pin. Internal current source connected to a single external capacitor will determine the soft-start duration for the output. Inhibits the chip if pulled down. Error Amplifier Output. A compensation network is connected from this pin to FB. The inverting input of the error amplifier, used to sense the output voltage via a resistive divider. Main IC supply. Ground. Drive Low. Gate drive for the bottom MOSFET. DRV supplies the external MOSFETs gate drive and the some internal circuitry. This pin should be bypassed with a ceramic capacitor to GND. DRV is internally regulated from the external supply connected to VDD. If VDD is below0V, the supply should be directly connected to the DRV pin. Supply for high side driver; can be directly connected to an external supply or to a bootstrap circuit. Drive High. Gate drive for the top MOSFET. The return path for the high side gate drive, also used to sense the voltage at the phase node for adaptive gate drive protection and the low-side RDS(ON) current sensing. Pad for heatsinking purposes. Connect to ground plane using multiple vias.  2 ILIM 2 3 4 5 6 7 8 3 4 5 8 6 9 0 OSC SS/EN EAO FB VDD GND DL 9  DRV 0  2 X 2 3 4 N/A BST DH PHASE THERMAL PAD (GND) 7 SC4612H Block Diagram 8 SC4612H Applications Information General Description The SC462H is a versatile voltage mode synchronous rectified buck PWM convertor, with an input supply ( VIN) ranging from 4.5V to 40V designed to control and drive N-channel MOSFETs. The power dissipation is controlled by allowing high speed and integration with the high drive currents to ensure low MOSFET switching loss. The synchronous buck configuration also allows converter sinking current from load without losing output regulation. The internal reference is trimmed to 500mV with ± % accuracy, and the output voltage can be adjusted by an external resistor divider. A fixed oscillator frequency (up to .2MHz) can be programmed by an external capacitor for design optimization. Other features of the SC462H include: Wide input power voltage range (from 4.5V to 40V), low output voltages, externally programmable softstart, hiccup over current protection, wide duty cycle range, thermal shutdown, and -40 to 25°C junction operating temperature range. Theory of Operation Supplies: Two pins (VDD and DRV) are used to power up the SC462H. If input supply (Vin) is less than 0V, tie DRV and VDD together. This DRV supply should be bypassed with a low ESR 2.2uF (or greater) ceramic capacitor directly at the DRV to GND pins of the SC462H. The DRV supply also provides the bias for the low and the high side MOSFET gate drive. The maximum rating for DRV supply is 0V and for applications where input supply is below 0V, it should be connected directly to VDD. The internal pass transistor will regulate the DRV from an external supply connected to VDD to produce 7.8V typical at the DRV pin. Soft Start / Shut down: The SC462H performs a “pre-bias” type startup. This ensures that a pre-charged output capacitor will not cause the SC462H to turn on the bottom FET during startup to discharge it, as a normal synchronous buck controller would do. An external capacitor on the SS/ EN pin is used to set the Soft Start duration. t SS ≈ 0.5 ⋅ C SS 25 ⋅ 10 −6 . . . . . . . . . . . . . . . . . . . . . () Startup is inhibited until VDD input reaches the UVLO threshold (typically 4.5V). Once VDD rises above UVLO, the external soft start capacitor begins to charge from an internal 25uA current source. When the SS/EN pin reaches approximately 0.8V, top side switching is enabled. However, a top side pulse will not occur until SS/EN has charged up to the level appropriate for the existing output voltage (a pre bias condition). Once the first top side gate pulse actually occurs, the bottom side driver is enabled and the remainder of the startup is fully synchronous. In the event of an over current during startup, the SC462H behaves in the same manner as an over current in steady state (see Over Current Protection). Oscillator Frequency Selection: The internal oscillator sawtooth signal is generated by charging an external capacitor with an internal 00μA current source. Under Voltage Lock Out Under Voltage Lock Out (UVLO) circuitry senses the VDD through a voltage divider. If this signal falls below 4.5V (typical) with a 400mV hysteresis (typical), the output drivers are disabled. During the thermal shutdown, the output drivers are disabled. 9 SC4612H Applications Information (continued) Over Current Protection The SC462H features low side MOSFET RDS(ON) current sensing and hiccup mode over current protection. The voltage across the bottom FET is sampled approximately 50ns after it is turned on to prevent false tripping due to ringing of the phase node. The internally set over current threshold is 00mV typical. This can be adjusted up or down by connecting a resistor between ILIM and DRV or GND respectively. When programming with an external resistor, threshold set point accuracy will be degraded to 30%. The FET RDS(ON) at temperature will typically be 50% or more of the room temperature value. Allowance should be made for these sources of error when programming a threshold value. When an over current event occurs, the SC462H immediately disables both gate drives. The SS ramp continues to its final value, if not already there. Once at final value, the SS capacitor is discharged at approximately uA until SS low value is reached (approx 0.8V). The SS/ Hiccup cycle will then repeat until the fault condition is removed and the SC462H starts up normally on the next SS cycle. Gate Drive/Control The SC462H provides integrated high current drivers for fast switching of large MOSFETs. The higher gate current will reduce switching losses of the larger MOSFETs. The low side gate drive is supplied directly from the DRV. The high side gate drive is bootstraped from the DRV pin. Cross conduction prevention circuitry ensures a non overlapping (30ns typical) gate drive between the top and bottom MOSFETs. This prevents shoot through losses which provides higher efficiency. Typical total minimum off time for the SC462H is about 30ns. Error Amplifer Design The SC462H is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate the output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below.     V 1 + sCR ESR  G VD (s) = IN   L VR  + s 2LC   1+ s RL   where, VIN = Input voltage . . . . . . . . . (2) L = Output inductance R ESR = Output capacitor ESR VR = Peak to peak ramp voltage R L = Load resistance C = Output capacitance The classical Type III compensation network can be built around the error amplifier as shown below: Fig 1. Type III compensation network The transfer function of the compensation network is as follows:  s  s 1 +  ω 1 + ω    ω Z1  Z2  G COMP (s) = 1 ⋅  s s  s 1 +  ω 1 + ω    P1  P2   where, ω Z1 = ω1 = 1 1 , ω Z2 = (R1 + R 3 )C 2 R 2 C1 . . . . . . . . . (3) 1 1 , ωP1 = R1 (C1 + C 3 ) R3C2 1  C1C 3 R2  C +C 3 1     ωP 2 = The design guidelines are as following: . Set the loop gain crossover frequency wC for given switching frequency. 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select wZ and wZ2 such that they are placed near wO to dampen peaking; the loop gain should cross 0 SC4612H Applications Information (continued) 0dB at a rate of -20dB/dec. 4. Cancel wESR with compensation pole wP (wP=wESR). 5. Place a high frequency compensation pole wP2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with adequate phase lag at wC. Technology Each Capacitor C (mF) Ceramic SP Cap POS-CAP Low ESR Aluminum 22 220 680 500 ESR (mW) 2-0 7 8 44   2 5 Qty Rqd. C (mF) 22 220 360 7500 Total ESR (mW) 2-0 7.0 9.0 8.8 The choice of which to use is simply a cost/ performance issue, with low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from: R ⋅C (VIN − VO ) L ≤ ESR . . . . . . . . . (5) It The calculated maximum inductor value assumes 00% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 0%-20% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: VIN ILRIPPLE = . . . . . . . . . (6) 4 ⋅ L ⋅ fOSC Ripple current allowance will define the minimum permitted inductor value.  Fig2. Power stage and compensated loop gain. COMPONENT SELECTION: SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from. R ESR ≤ Vt It . . . . . . . . . (4) where, Vt = Maximum transient voltage excursion I t = Transient current step For example, to meet a 00mV transient limit with a 0A load step, the output capacitor ESR must be less than 0mW. To meet this kind of ESR level, there are four available capacitor technologies. SC4612H Applications Information (continued) POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as: 2 PCOND = IO ⋅ R DS( ON) ⋅ D circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. Low Side RDS(ON) Current Limit . . . . . . . . . (7) where D = Duty cycle ≈ VO VIN Fig3: Current Limit circuitry b) Switching losses can be estimated if the switching time is known or assumed: PSW = IO ⋅ VIN ⋅ (t r + t f ) ⋅ fOSC 2 . . . . . . . . . (8) . Programming resistors Ra and Rb - Not installed: 2.75 V − 100mV 100mV − VPH = R3 R2 . . . . . . () c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: PRR = Q RR ⋅ VIN ⋅ fOSC . . . . . . . . . (9) solving for: VPH = -00mV, the circuit will trip at RDS(ON) x ILOAD = 00mV 2. To increase trip voltage - install Ra. Ra = − 772 − 20 ⋅ VPH 1 + 10 ⋅ VPH . . . . . . . . . (2) BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it resulting in very low switching losses. Conduction losses for the FET can be determined by: solving for double the current limit: VPH = -200mV. Ra = 768kW. 3. To decrease trip voltage - install Rb Rb = 8 − 20 ⋅ VPH 1 + 10 ⋅ VPH . . . . . . . . . (3) PCOND = I2 ⋅ R DS( ON) ⋅ (1 − D) O . . . . . . . . . (0) INPUT CAPACITORS - Since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter solving for half the current limit: VPH = -50mV. Rb = 8kW. NOTE: Allow for tempco and RDS(ON) variation of the MOSFET- see the “Over Current Protection” section of the datasheet. 2 SC4612H Applications Information (continued) PCB Layout Guidelines Careful attention to layout is necessary for successful implementation of the SC462H PWM controller. High switching currents are present in the application and their effect on ground plane voltage differentials must be understood and minimized. ) The high power section of the circuit should be laid out first. A ground plane should be used. The number and position of ground plane interruptions should not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas; for example, the input capacitor and bottom FET ground. 2) The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q), and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) The connection between the junction of Q, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. Top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and therefore, connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC462H is best placed over a quiet ground plane area. Avoid pulse currents in the Cin, Q, Q2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of ) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q, Q2 loop. 6) Allow adequate heat sinking area for the power components. If multiple layers will be used, provide sufficent vias for heat transfer. Fig4: Current waveforms of buck power stage. 3 SC4612H Applications Information (continued) 4 SC4612H Applications Information (continued) 5 SC4612H Applications Information (continued) Typical EVB Layout Top Copper Bottom Copper (viewed from top) Top Silk Screen Top Assembly 6 SC4612H Outline Drawing — MLPD-12 Land Pattern — MLPD-12 7 SC4612H Outline Drawing — SOIC-14 Land Pattern — SOIC-14 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 9302 Phone: (805) 498-2 Fax: (805) 498-3804 www.semtech.com 8