SC4624MLTRT

Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator POWER MANAGEMENT Description The SC4624 is a highly integrated synchronous step-down DC/DC regulator designed for low input voltage range of 2.3V to 5.5 Volts. It can deliver 4A continuous output current with the output voltage as low as 0.5 Volts. The internal low RDS(ON) synchronous power switches eliminate the need for external Schottky diode while delivering overall converter efficiency up to 95%. A power good pin is available to monitor the output voltage status. Operating frequency is adjustable from 200 kHz to 2MHz with a single resistor and it can be synchronized to an external clock. The SC4624 offers adjustable current limit, soft start and over temperature protection to safeguard the device under extreme operating conditions. The soft start provides a controlled output voltage ramp up at startup. When a logic low is applied to the Enable pin, the SC4624 enters the shutdown mode and it consumes less than 1.5µA of current. The SC4624 is available in 4x4 MLPQ-20 and SOIC-16EDP package, and it is rated over -40°C to +105°C ambient temperature range. SC4624 Features u VIN Range: 2.3 – 5.5V u 4A Continuous Output Current u Adjustable Output Voltage 0.5V to Vin u Low RDS(ON) integrated FETs: 74mΩ and 47mΩ u Up to 95% Efficiency u Synchronizable and Programmable Frequency: 200kHz – 2MHz u Power Good Monitor u V1) as shown in Figure 16, the SC4624 proceeds into the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases and the output voltage is monitored. If the over current and low output voltage (set at 60% of nominal output voltage) occur at the same time, the SS pin is pull low by an internal switch and the comp pin is pulled low and the devices stops switching. Assume start from FB = 0V, FB and SS voltage rise forward 0.5V. Once SS voltage exceeds 0.4V, the hiccup comparator becomes enabled. The hiccup period is around 217/FOSC. (Point C to Point D). For example, with a switching frequency application of 550kHz, the hiccup period is around 238ms. (refer to Figure 7). A poor layout will make OCP trip point shift and is not easily to calculate by RISET. This is because it is affected by ground bounce, spiker voltage between Vin pin and PH pin, and internal parameter tolerance. Users can refer to Figure 14, it shows how to set maximum output current by RISET. The inductor value can be determined according to its operating point and the switching frequency as follows: where fs = switching frequency. DI = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is: After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation and is given as follows: The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce any copper loss of the inductor, (the core loss can be found in the manufacturer’s datasheet). The inductor’s copper loss can be estimated as follows: Vout A B 0 0.6 * Vout Vo C where ILRMS is the RMS current in the inductor. This current can be calculated as follows: D Iout 0 Imax Figure 16. Over Current Protection Characteristic Inductor Selection For a typical SC4624 application, the inductor selection is mainly based on its value, saturation current and DC resistance. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss.  2008 Semtech Corp. 13 Output Capacitor Selection Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the www.semtech.com SC4624 POWER MANAGEMENT Opplication Information (Cont.) Application A peration SC4624 regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction mode, the RMS value of the input capacitor can be calculated from: network to meet the requirements for a specific application. The SC4624 has an internal error amplifier and requires the compensation network to connect among the COMP pin and FB pin, GND, and the output as shown in Figure 17. The compensation network includes C1, C2, R1, R7, R8 and C8. R9 is used to program the output voltage according to: 5 4 3 2 1 D C1 R1 C2 SC4624 D COMP FB Vout C L1 C8 PH C IN R B C4 R8 R7 This current gives the capacitor’s power loss as follows: B R9 This capacitor’s RMS loss can be a significant part of the total loss in the converter and reduces the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor’s ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by: ∆ A A 5 Figure 17. Compensation Network Provides 3 Poles and 2 Zeros 4 3 2 1 For voltage mode step down applications as shown in Figure 17, the power stage transfer function is: where D = VO/VI , duty ratio. DVI = the given input voltage ripple. Loop Compensation Design For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation  2008 Semtech Corp. 14 where R = load resistance RC = C4’s ESR. The compensation network will have these characteristics: w GCOMP (s) = I ⋅ s 1+ s s 1+ wZ1 wZ 2 ⋅ s s 1+ ⋅1+ wP1 wP 2 www.semtech.com SC4624 POWER MANAGEMENT Operation Information (Cont.) Application Application where ωI = 1 R 7 ⋅ (C1 + C 2 ) The design guidelines for the SC4624 applications are as follows: 1. Set the loop gain crossover corner frequency wC for given switching corner frequency wS = 2pfs, 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select wZ1 and wZ2 such that they are placed near wO to damp the peaking and the loop gain has a -20dB/ dec rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel the zero from C4’s ESR by a compensator pole wP1 (wP1 = wESR = 1/(RCC4)). 5. Place a high frequency compensator pole wP2 (wP2 = pfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at wC. The compensated loop gain will be as given as show in Figure 18. ω Z1 = 1 R1 ⋅ C2 1 ( R 7 + R 8 ) ⋅ C8 ωZ2 = ωP1 = C1 + C 2 R 1 ⋅ C1 ⋅ C 2 1 R 8 ⋅ C9 ωP 2 = 8 After the compensation, the converter will have the following loop gain: 1+ 1 1 s s ⋅ wI ⋅ VI 1 + 1+ RC ⋅ C4 VM wZ1 wZ 2 = (s) ⋅ G VD (s) = ⋅ ⋅ ⋅ s s L s 1+ ⋅1+ 1 + s 1 + s2L1C wP1 wP 2 R s 1+ 1 1 s s ⋅ wI ⋅ VI 1 + 1+ RC ⋅ C4 VM wZ1 wZ 2 T(s) = GPWM ⋅ GCOMP (s) ⋅ G VD (s) = ⋅ ⋅ ⋅ s s L s 1+ ⋅1+ 1 + s 1 + s2L1C wP1 wP 2 R s where GPWM = PWM gain. VM = 1.0V, ramp peak to valley voltage of SC4624. Figure 18. Asymptotic Diagrams of Power Stage and Loop Gain  2008 Semtech Corp. 15 www.semtech.com SC4624 POWER MANAGEMENT Operation Information (Cont.) Application Application Layout Guidelines In order to achieve optimal thermal and noise immunity for high frequency converters, special attention must be paid to the PCB layout. The goal of layout optimization is to minimize the high di/dt loops and reduce ground bounce. Output voltage setting, line regulation, stability , switching frequency and OCP trip point shifted are affected by a poor layout. The following guidelines should be used to ensure proper functions of the converters. 1. Both Power ground (PGND) and signal ground (AGND) are separated. 2. A ground plane is recommended to minimize noise and copper losses, and maximize heat dissipation. 3. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. 4. Minimize all high di/dt loops. These loops pass high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. Ground bounce happen to magnetic flux changed and it is proportional to a magnetic filed which goes through high di/dt loops. 5. The input ceramic capacitor (CIN) should be close to PVIN pins and PGND pins. 6. Both input ceramic capacitor gnd and output ceramic capacitor gnd are at same port. 7. A RC snubber circuit between PVIN and PH pins is helpful for stability operation. Be careful with power derating of snubber circuit. 8. The VCC bypass capacitor should be placed next to the VCC and AGND pins. 9. The OCP setting resistor (RISET) and filter capacitor (CISET) should be placed next to the ISET and AGND pins. 10. Feedback divider connects to output connector by Kelvin connection and far away from the noise sources such as switching node and switching components. 11. A multilayer chip beads between AGND and PGND will reduce the ground bounce injected to the “quiet” circuit. It’s helpful for stability operation. 12. A large copper area underneath the SC4624 IC is necessary for heat sinking purpose. And multiple layers of large copper area connected through vias can be used for better thermal performance. The size of the vias as the connection between multiple layers should not be too large or solder may seep through  2008 Semtech Corp. 16 www.semtech.com the big vias to the bottom layer during the re-flow process . SC4624 POWER MANAGEMENT Operation Information (Cont.) Application Application 5 4 3 2 5VIN, 1VOUT, 4A, all ceramic capacitors ( application circuit#1 ) 5Vin R5 10k R6 10k R2 10R C6 1nF C3 1uF 5 6 14 U1 VCC PGOOD SYNC/EN NC COMP FB PH1 PH2 PH3 VCC AGND FS SS NC ISET PVIN1 PVIN2 PGND1 12 13 4 3 9 2 1 20 15 16 C9 22uF R11 C7 47.5k 47nF C1 R1 20k 2.2pF C2 390pF 7 10 11 C5 R3 30k opt 1Vout@4A C8 270pF R8 2.32k R7 28.7k L1 1.8uH 17 18 19 8 C4 22uF R9 PAD NC PGND2 (2) R12 28.7k SC4624 MLB-160808-0600R-S2 C11 R4 opt VIN=5V; Vout=1V/4A (1) opt Switching Frequency=550kHz Note: (1,2) Option for stability L1: TOKO D104C(919AS-1R8N) R12: Multilayer chip inductors; MLB-160808-0600R-S2 Input(C9)/Output Capacitors(C4): Panasonic ECJ33YBOJ226M(22uF/6.3V) Title SC4624 Application Sheet Size Document Number Custom Date: 5 4 3 Monday, June 25, 2007 2  2008 Semtech Corp. 17 www.semtech.com SC4624 POWER MANAGEMENT Operation PCB PCB Layout Component Side (TOP) (TOP layer) (Bottom layer) (IN1 layer) (IN2 layer)  2008 Semtech Corp. 18 www.semtech.com SC4624 POWER MANAGEMENT Outline Drawing - MLPQ - 20 A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb SEATING PLANE A1 D1 LxN E/2 E1 2 1 C DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .031 .035 .039 .000 .001 .002 - (.008) .007 .010 .012 .154 .157 .161 .100 .106 .110 .154 .157 .161 .100 .106 .110 .020 BSC .012 .016 .020 20 .004 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 20 0.10 0.10 PIN 1 INDICATOR (LASER MARK) E A2 A aaa C N e D/2 bxN bbb CAB NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Land Pattern - MLPQ - 20 K DIMENSIONS DIM C G H K P X Y Z INCHES (.156) .122 .106 .106 .020 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80 (C) H G Z Y X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.  2008 Semtech Corp. 19 www.semtech.com SC4624 POWER MANAGEMENT Outline Drawing - SO-16 EDP A e N 2X E/2 E1 1 ccc C 2X N/2 TIPS 2 3 e/2 B E D DIM A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .053 .069 .000 .005 .049 .065 .012 .020 .007 .010 .386 .390 .394 .150 .154 .157 .236 BSC .050 BSC .100 .105 .110 .080 .085 .090 .010 .020 .016 .028 .041 (.041) 16 0° 8° .004 .010 .008 1.35 0.00 1.25 0.31 0.17 9.80 3.80 2.54 2.03 0.25 0.40 0° 1.75 0.13 1.65 0.51 0.25 9.90 10.00 3.90 4.00 6.00 BSC 1.27 BSC 2.67 2.79 2.16 2.29 0.50 0.72 1.04 (1.04) 16 8° 0.10 0.25 0.20 D aaa C SEATING PLANE A2 C A1 bbb C A-B D A bxN EXPOSED PAD F H GAUGE PLANE 0.25 DETAIL L (L1) c H 01 h h NOTES: 1. 2. 3. 4. DATUMS -AAND -B- A SEE DETAIL SIDE VIEW A CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). TO BE DETERMINED AT DATUM PLANE -H- DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-012, VARIATION AC. Land Pattern - SO-16 EDP THERMAL VIA Ø 0.36mm E D SOLDER MASK DIM (C) F G Z C D E F G P X Y Z DIMENSIONS INCHES MILLIMETERS (.205) .114 .201 .094 .118 .050 .024 .087 .291 (5.20) 2.90 5.10 2.40 3.00 1.27 0.60 2.20 7.40 Y P X NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 2. 3. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804  2008 Semtech Corp. www.semtech.com 20 www.semtech.com