SC561

SC561 Dual Output Low Noise LDO Linear Regulator POWER MANAGEMENT Features Input voltage range — 2.5V to 5.5V Output voltage — VLDOA = 3.1V; VLDOB = 2.85V Maximum output current — 300mA (each LDO) Dropout at 200mA load — 200mV max. Quiescent supply current — 40μA (both LDOs enabled) Shutdown current — 100nA (typ) Output noise < 50μVRMS PSRR >65dB at 1kHz Over-temperature protection Short-circuit protection Under-voltage lockout Power good monitor for output A MLPQ-UT8, 1.5mm x 1.5mm x 0.6mm package Description The SC561 is a dual output, ultra-low dropout linear voltage regulator designed for use in battery powered applications. The SC561 provides fixed output voltages of VLDOA = 3.1V and VLDOB = 2.85V, and up to 300mA of load current per channel. In applications where maximum battery life is essential, the SC561 can operate in an extremely low power state by setting the dynamic bias control. At very light loads, the LOAD pin can be pulled low so that the device consumes only 40μA of quiescent current. The SC561 provides superior low-noise performance by using an external bypass capacitor to filter the bandgap reference. The device also has a PGOOD output to hold a processor in reset when the voltage on OUTA is not in regulation. The device provides protection circuitry such as shortcircuit protection, under-voltage lockout, and thermal protection to prevent device failures. Stability is maintained by using 1μF capacitors on the output pins. The MLPQ-UT8 package and small ceramic bypass capacitors minimize the required PCB area. Applications PDAs and cellular phones GPS devices Palmtop computers and handheld instruments TFT/LCD applications Wireless handsets Digital cordless phones and PCS phones Personal communicators Wireless LAN Typical Application Circuit SC561 VIN EN LOAD CIN 2.2μF IN EN LOAD GND PGOOD OUTA OUTB BYP CBYP 22nF COUTA 1μF COUTB 1μF PGOOD OUTA OUTB November 21, 2007 1 SC561 Pin Configuration Ordering Information Device SC561ULTRT(1)(2) Package MLPQ-UT8 1.5×1.5 Evaluation Board PGOOD 8 OUTB IN OUTA 1 TOP VIEW SC561EVB 7 6 4 LOAD 5 BYP EN GND Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free package only. Device is WEEE and RoHS compliant. 2 3 MLPQ-UT-8; 1.5x1.5, 8 LEAD θJA = 157°C/W Marking Information Voltage Options Output Voltage Options VLDOA SC561 3.1 Device VLDOB 2.85 Part Number Code 0V nn yw nn = Part No. Code — See the Voltage Options Table for details yw = Datecode — See package marking design guidelines document #ALOW-693AQX 2 SC561 Absolute Maximum Ratings IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 EN, LOAD(V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3) PGOOD (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3) Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3) OUTA, OUTB, Short Circuit Duration . . . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Recommended Operating Conditions Ambient Temperature Range (°C) . . . . . . . . . -40 < TA < +85 VIN ( V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 to 5.5 Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W) . . . 157 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted VIN = 3.6V, CIN = 2.2μF, COUTA = COUTB = 1μF, VEN = VLOAD = VIN, TA = -40 to +85°C. Typical values are at TA = 25°C. All specifications apply to both LDOs unless otherwise noted. Parameter Input Supply Voltage Range Symbol VIN VOUTA Conditions Min 2.5 Typ Max 5.5 Units V 3.1 V 2.85 VIN = 2.5V to 5.5V, IOUTx = 0 to 300mA, VIN ≥ VOUTx + 0.3 Each LDO IOUTx = 250mA, VOUTx = 2.5V to 3.3V -3 300 150 50 0.1 55 40 250 100 1 85 60 20 -6 6 3 % mA mV mV μA μA μA mV mV Output Voltage VOUTB Output Voltage Accuracy Maximum Output Current ΔVOUTx IMAX Dropout Voltage(1) VD IOUTx = 50mA, VOUTx = 2.5V to 3.3V Shutdown Current ISD TA = 25°C IOUTA = IOUTB = 0mA, LOAD = VIN Quiescent Current IQ IOUTA = IOUTB = 1mA, LOAD = 0V Load Regulation Line Regulation ΔVLOAD ΔVLINE IOUTx = 1mA to IMAX IOUTx = 1mA 3 SC561 Electrical Characteristics (continued) Parameter Current Limit Noise Power Supply Rejection Ratio PGOOD Delay PGOOD Threshold PGOOD Threshold Hysteresis Start-Up Time Under Voltage Lockout UVLO Hysteresis Over Temperature Protection Threshold(3) Over Temperature Threshold Hysteresis Digital Inputs Logic Input High Threshold Logic Input Low Threshold Logic Input High Current Logic Input Low Current Digital Outputs PGOOD Output voltage Low VOL ISINK = 500μA,VIN=3.7V 7 20 mV VIH VIL IIH IIL VIN = 5.5V VIN = 2.5V VIN = 5.5V VIN = 5.5V 1.25 0.4 1 1 V V μA μA Symbol ILIMx eN PSRR tDELAY V TH-PGOOD VPGOOD-HYS tSU VUVLO VUVLO-HYS TOT VOT-HYS Conditions Min 350 Typ Max 850 Units mA μVRMS dB IOUTx = 50mA , 10Hz < f < 100kHz, CBYP = 22nF IOUTx = 50mA, f = 1kHz, CBYP = 22nF 50(2) 160 Percentage of nominal output, VOUTA falling 82 50 100(2) 65 200 87 3 240 92 ms % % ms From OFF to 87% VOUTx, IOUTx = 50mA, CBYP = 22nF VIN Rising 2.20 1 2.30 100 2.40 V mV °C Temperature Rising 160 20 °C Notes: (1) Dropout voltage is defined as VIN - VOUTx , when VOUTx is 100mV below the value of VOUTx at VIN = VOUTx + 0.5V. (2) Guaranteed by design (3) Thermal shutdown latches both LDOs off. Cycle EN or VIN pin to reset. 4 SC561 Typical Characteristics Load Regulation (LDOA) 8 7 VOUTA = 3.1V, VIN = 3.6V Load Regulation (LDOB) 8 7 VOUTB = 2.85V, VIN = 3.6V Output Voltage Variation (mV) 6 5 4 3 2 1 0 0 50 100 150 200 Output Current (mA) 250 300 TA=-40°C TA=85°C TA=25°C Output Voltage Variation (mV) 6 5 4 3 2 1 TA=-40°C 0 0 50 100 150 200 Output Current (mA) 250 300 TA=25°C TA=85°C Line Regulation (LDOA) 3 2.5 VOUTA = 3.1V, IOUTA = 1mA Line Regulation (LDOB) 3 2.5 Output Voltage Variation (mV) VOUTB = 2.85V, IOUTB = 1mA Output Voltage Variation (mV) 2 1.5 1 0.5 0 -0.5 2.9 TA=-40°C 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) 4.7 4.9 5.1 5.3 5.5 TA=25°C TA=85°C 2 1.5 1 TA=25°C 0.5 0 -0.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) 4.7 4.9 5.1 5.3 5.5 TA=-40°C TA=85°C Dropout Voltage (LDOA) 350 300 250 VOUTA = 3.1V, IOUTA = 250mA Dropout Voltage (LDOB) 350 300 250 VOUTB = 2.85V, IOUTB = 250mA TA=85°C VIN - VOUT (mV) 200 150 100 50 0 3.1 TA=25°C TA=85°C VIN - VOUT (mV) 200 150 100 50 0 TA=25°C TA=-40°C TA=-40°C 3.15 3.2 3.25 3.3 Input Voltage (V) 3.35 3.4 2.8 2.85 2.9 2.95 Input Voltage (V) 3 3.05 3.1 5 SC561 Typical Characteristics (continued) Dropout Voltage (LDOA) 350 300 250 VOUTA = 3.1V, IOUTA = 50mA 300 Dropout Voltage (LDOB) VOUTB = 2.85V, IOUTB = 50mA 250 VIN - VOUT (mV) 200 150 100 50 0 3.1 TA=25°C 3.15 3.2 3.25 3.3 Input Voltage (V) 3.35 3.4 TA=-40°C TA=85°C VIN - VOUT (mV) 200 150 TA=85°C 100 TA=-40°C TA=25°C 50 0 2.8 2.85 2.9 2.95 Input Voltage (V) 3 3.05 3.1 PSRR vs. Frequency (LDOA) 0 -10 -20 -30 -40 -50 -60 -70 -80 10 PSRR (dB) PSRR vs. Frequency (LDOB) 0 -10 -20 -30 -40 -50 -60 -70 -80 10 VOUTB = 2.85V, IOUTB = 50mA, CBYP = 22nF VOUTA = 3.1V, IOUTA = 50mA, CBYP = 22nF PSRR (dB) 100 1000 Frequency (Hz) 10000 100 Frequency (Hz) 1000 10000 Output Noise vs. Load Current (LDOA) 70 60 Output Voltage Noise (μV) Output Noise vs. Load Current (LDOB) 70 60 VOUTB = 2.85V, VIN = 3.6V, CBYP = 22nF VOUTA = 3.1V, VIN = 3.6V, CBYP = 22nF TA=85°C Output Voltage Noise (uV) 50 40 30 20 10 0 1 10 TA=25°C TA=-40°C 50 40 30 20 10 0 TA=85°C TA=25°C TA=-40°C 100 Output Current (mA) 1000 1 10 100 Output Current (mA) 1000 6 SC561 Typical Characteristics (continued) Load Transient Response Rising Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = H Load Transient Response Falling Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = H IOUT=1mA to 100mA IOUT=1mA to 100mA (50mA/div) (50mA/div) VOUT (20mV/div) VOUT (20mV/div) Time (50μs/div) Time (50μs/div) Load Transient Response Rising Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = H Load Transient Response Falling Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = H IOUT=1mA to 3mA (50mA/div) IOUT=1mA to 3mA (50mA/div) VOUT (10mV/div) VOUT (10mV/div) Time (50μs/div) Time (50μs/div) Load Transient Response Rising Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = L Load Transient Response Falling Edge (Both LDOs) VIN = 3.6V, VOUT = 3.1V, LOAD = L IOUT=1mA to 3mA (50mA/div) IOUT=1mA to 3mA (50mA/div) VOUT (10mV/div) VOUT (10mV/div) Time (50μs/div) Time (50μs/div) 7 SC561 Pin Configurations and Descriptions SC561 1 2 3 4 5 6 7 8 Pin Name Pin Function OUTB VIN OUTA LOAD GND EN BYP PGOOD Output for LDOB Input supply voltage terminal Output for LDOA Dynamic bias control — pull this pin high for normal operation at all load currents. Pull this pin low for lowest IQ at loads less than 2mA. This pin is a logic input and cannot be left unconnected. Analog and digital ground Logic input — active HIGH enables both LDOs LDO bypass output — bypass with a 22nF capacitor Power Good open-drain output — monitors the level of LDOA, switches low when the output drops out of regulation. Tie to VIN or OUTA via a 100k Ω resistor. Leave floating when function is not required. 8 SC561 Block Diagram SC561 7 VIN BYP PGOOD VIN 2 VREF 8 UVLO VIN PGOOD Logic GND 5 O/T PowerON Logic LDOA VIN 3 OUTA EN LOAD 6 4 LDOB 1 OUTB 9 SC561 Applications Information General Description The SC561 is a dual output linear regulator device intended for applications where low dropout voltage, low supply current, and low output noise are critical. The device provides a simple, low cost solution for two separate regulated outputs. Minimal PCB area is required due to the miniature package size and the need for only four external capacitors. The linear regulators LDOA and LDOB are powered from a single input supply rail, and each provides up to 300mA of output current. The SC561 provides output voltages in the range 1.2V to 3.3V. Available voltage values are shown in the Voltage Options table on page 2. Dynamic Bias Control The LOAD pin provides dynamic bias control which allows the device to be operated in a low quiescent current mode at light loads. At loads less than 2mA, the LOAD pin should be pulled low in order to force the device into an ultra-low quiescent current mode. When the load is increased above 2mA, the LOAD pin should be pulled high to ensure normal operation. This pin is a logic input, therefore it must never be left unconnected. Figure 2 shows the quiescent current versus load current with both LDOs enabled. 1.4 1.2 1 0.8 0.6 0.4 0.2 LOAD = H Power On Control The SC561 device has a single enable pin (EN) that controls both LDO outputs. Pulling this pin low causes the device to enter a low power shutdown mode where it typically draws 100nA from the input supply. The outputs of both LDOA and LDOB are enabled when EN transitions high. When the output voltage of LDOA reaches 87% of its regulation point, the delay timer starts and the PGOOD signal transitions high after a delay of 200ms. The power up/down sequence is shown in the timing diagram in Figure 1. Iq (mA) 0 0.01 0.1 1 Io (mA) 10 100 1000 Figure 2a - Quiescent Current versus Output Current 0.2 0.18 0.16 EN tSU 87% 87% 200ms 0.14 0.12 OUTA Iq (mA) 0.1 0.08 0.06 0.04 LOAD = L PGOOD OUTB 0.02 Figure 1 — Timing Diagram As PGOOD is an open-drain output, it can be left unconnected when it is not in use without affecting the performance of the device. 0 0.01 0.1 1 Io (mA) 10 100 1000 Figure 2b - Quiescent Current versus Output Current 10 SC561 Applications Information (continued) Protection Features The SC561 provides protection features to ensure that no damage is incurred in the event of a fault condition. These functions include: Short-Circuit Protection Each output has short-circuit protection. If the output current exceeds the current limit, the output voltage will drop and the output current will be limited until the load current returns to a specified level. • • • Under-Voltage Lockout Over-Temperature Protection Short-Circuit Protection Component Selection A minimum capacitance of 1μF on each output is required to ensure stability. This must be considered when choosing very small size capacitors as the dc bias must be included in their derating to ensure this required value. For example, a 1μF 0402 size capacitor may work at low output voltages, but the capacitance may be too low at higher output voltages. Although there is no maximum value of output capacitor specified, very large values may increase the rise time of the output voltages without affecting stability. It is recommended that the value of output capacitance be restricted to a maximum of 10μF. Ceramic capacitors of type X5R or X7R should be used because of their low ESR and stable temperature coefficients. It is also recommended that the input be bypassed with a 2.2μF, low ESR X5R or X7R capacitor to minimize noise and improve transient response. Note: Tantalum and Y5V capacitors are not recommended. The BYP pin on the SC561 must have a minimum of 22nF connected to ground to meet all noise-sensitive requirements. This value can be increased to a maximum of 1μF to improve noise and PSRR. However, larger values of bypass capacitor will increase the start-up time of the SC561. Under-Voltage Lockout The Under-Voltage Lockout (UVLO) circuit protects the device from operating in an unknown state if the input voltage supply is too low. When the VIN drops below the UVLO threshold, as defined in the Electrical Characteristics section, the LDOs are disabled and PGOOD is held low. The LDOs are re-enabled into their previous states when VIN is increased above the hysteresis level. When powering up with VIN below the UVLO threshold, the LDOs remain disabled and PGOOD is held low. Over-Temperature Protection An internal Over-Temperature (OT) protection circuit is provided that monitors the internal junction temperature. When the temperature exceeds the OT threshold as defined in the Electrical Characteristics section, the OT protection disables both LDO outputs and holds the PGOOD signal low. The LDOs can only be re-enabled by cycling the EN pin. 11 SC561 Applications Information (continued) Thermal Considerations Although each of the two LDOs in the SC561 can provide 300mA of output current, the maximum power dissipation in the device is restricted by the miniature package size. The graphs in Figures 3 and 4 can be used as a guideline to determine whether the input voltage, output voltages, output currents, and ambient temperature of the system result in power dissipation within the operating limits are met or if further thermal relief is required. 0.7 0.6 known operating conditions using the following equation: TJ = TA +(PD x θJA) where TJ = Junction Temperature (°C) TA = Ambient Temperature (°C) PD = Power Dissipation (W) θJA = Thermal Resistance Junction to Ambient (°C/W) Example A SC561 is used to provide outputs of 3.1V, 150mA from LDOA and 2.85V, 250mA from LDOB. The input voltage is 4.2V, and the ambient temperature of the system is 40°C. PD= 0.15(4.2 – 3.1) + 0.25(4.2 – 2.85) Maximum Total Output Current (A) Maximum Recommended Input Voltage 0.5 0.4 0.3 0.2 0.1 ______ 0 3 TA=+25°C, PD(MAX)= 0.8W - - - - TA=+85°C, PD(MAX)= 0.41W 3.5 4 4.5 Input Voltage (V) 5 5.5 6 = 0.503W and TJ = 40 + (0.503 x 157) = 118.9°C Figure 4 shows that the junction temperature would be within the maximum specification of 150°C for this power dissipation. This means that operation of the SC561 under these conditions is within the specified limits and the device would not require further thermal relief measures. Figure 3 — Safe Operating Limit 1.6 1.4 Maximum Power Dissipation (W) 1.2 1 0.8 0.6 TJ(Max)=125°C TJ(Max)=150°C 0.4 0.2 0 -40 -20 0 60 20 40 Ambient Temperature (oC) 80 100 Figure 4 — Maximum PD vs. TA The following procedure can be followed to determine if the thermal design of the system is adequate. The junction temperature of the SC561 can be determined in 12 SC561 Applications Information (continued) Layout Considerations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. The diagram below illustrates proper layout of a circuit. • • • Place the input, output, and bypass capacitors close to the device for optimal transient response and device behavior. Connect all ground connections directly to the ground plane whenever possible to minimize ground potential differences on the PCB. Attach the part to a large copper footprint, to enable better heat transfer from the device on PCBs where there are internal power and ground planes. COUTB SC561 CIN CBYP COUTA Layer 1 Layer 2 Scale = 20:1 (20mm = 1mm) Via between Layer 1 and Layer 2 13 SC561 Outline Drawing — MLPQ-UT8 A D B DIM A A1 A2 b D E e L N aaa bbb A2 DIMENSIONS INCHES MIN .020 .000 .006 NOM MAX .024 .002 MILLIMETERS MIN 0.50 0.00 0.15 NOM MAX 0.60 0.05 PIN 1 INDICATOR (LASER MARK) E (.006) .008 .010 .059 BSC .059 BSC .016 BSC 0.12 0.16 .014 8 .004 .004 (0.1524) 0.20 0.25 1.50 BSC 1.50 BSC 0.40 BSC 0.30 0.40 0.35 8 0.10 0.10 A SEATING aaa C C A1 LxN PLANE e 2 0.20 1 0.25 N bxN 0.17 bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 14 SC561 Land Pattern — MLPQ-UT8 Z G DIM C G 2X (C) P P (G) (Z) R X Y X R Y Z DIMENSIONS INCHES (.057) .028 .016 .004 .008 .030 .087 MILLIMETERS (1.45) 0.70 0.40 0.10 0.20 0.75 2.20 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 15