SC643EVB

SC643 Light Management Unit with 4 LDOs and SemPulse® Interface POWER MANAGEMENT Features Input supply voltage range — 2.9V to 5.5V Very high efficiency charge pump driver system with three modes — 1x, 1.5x, and 2x Five programmable current sinks with 29 increments from 0mA to 25mA Four programmable 200mA low-noise LDO regulators Programmable driver configurations for main and sub-display backlight Fade-in/fade-out feature for main and sub display backlight SemPulse single wire interface Backlight current accuracy — ±1.5% typical Backlight current matching — ±0.5% typical External enable pin for optional control of LDO4 Automatic sleep mode with LEDs off Shutdown current — 0.1μA typical Ultra-thin package — 3 x 3 x 0.6 (mm) Lead free and Halogen free WEEE and RoHS compliant Description The SC643 is a high efficiency charge pump LED driver using Semtech’s proprietary charge pump technology. Performance is optimized for use in single cell Li-ion battery applications. Display backlighting is provided through five matched current sinks with integrated fade-in and fade-out controls. The LEDs can be driven as a single set or as two different sets (for main and sub displays) with independent controls. Four low noise, low dropout (LDO) regulators are provided to supply power for camera module I/O and other peripheral circuits. An external enable pin is also provided for one LDO for added flexibility. The SC643 uses the proprietary SemPulse® single wire interface. This interface controls all functions of the device, including backlight currents and LDO voltage outputs. The single wire interface minimizes microcontroller and interface pin counts. The SC643 enters sleep mode when all the LED drivers are disabled. In this mode, the quiescent current is reduced while the device continues to monitor the SemPulse interface. Any combination of LDOs may be enabled when in sleep mode. Applications Cellular phones, smart phones, and PDAs LCD display modules Portable media players Digital cameras and GPS units Display backlighting and LED indicators Typical Application Circuit SC643 VBAT = 2.9V to 5.5V SemPulse Interface Motor Control IN SPIF 4.7μF ENL4 BYP 22nF BL1 BL2 BL3 BL4 BL5 LDO1 LDO2 LDO3 LDO4 OUT Main Backlight Sub Backlight 4.7μF AGND PGND VLDO1 = 1.5V to 3.3V VLDO2 = 1.2V to 1.8V VLDO3 = 1.5V to 3.3V C1+ C2+ C1- C2- 1.0μF 1.0μF 1.0μF 1.0μF Motor 2.2μF 2.2μF US Patents: 6,504,422; 6,794,926 October 8, 2009 © 2009 Semtech Corporation 1 SC643 Pin Configuration OUT C1+ C2+ C2C1- Ordering Information Device SC643ULTRT(1)(2) SC643EVB 15 TOP VIEW 14 13 12 T 11 Package MLPQ-UT-20 3×3 Evaluation Board 20 19 18 17 16 IN PGND BL3 BL2 BL1 1 2 3 4 5 LDO1 LDO2 BYP SPIF LDO3 Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. 6 7 8 9 10 MLPQ-UT-20; 3x3, 20 LEAD θJA = 35°C/W Marking Information 643 yyww xxxx yyww = Date Code xxxx = Semtech Lot No. AGND LDO4 ENL4 BL4 BL5 2 SC643 Absolute Maximum Ratings IN, OUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 C1+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3) Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3) OUT , LDOn Short Circuit Duration . . . . . . . . . .Continuous ESD Protection Level(2) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 (1) Recommended Operating Conditions Ambient Temperature Range (°C) . . . . . . . . -40 ≤ TA ≤ +85 Input Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 ≤ VIN ≤ 5.5 Output Voltage (V). . . . . . . . . . . . . . . . . . . . . . 2.5 ≤ VOUT ≤ 5.25 Voltage difference between any two LEDs (V) . . . ΔVF ≤ 1.0 Thermal Information Thermal Resistance, Junction to Ambient(3) (°C/W) . . . . 35 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) subscript n = 1, 2, 3, and 4. (2) Tested according to JEDEC standard JESD22-A114-B. (3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted, TA = +25°C for Typ, -40ºC to +85°C for Min and Max, TJ(MAX) = 125ºC, VIN = 3.7V, C1= C2 = 2.2μF, CIN = COUT = 4.7μF, (ESR = 0.03Ω)(1) Parameter Supply Specifications Input Supply Voltage Shutdown Current Symbol Conditions Min Typ Max Units VIN IQ(OFF) Shutdown, VIN = 4.2V Sleep (all LDOs off ), SPIF = VIN(2) Sleep (all LDOs on), SPIF = VIN (2) 2.9 0.1 90 300 2.5 4.3 5.1 5.5 2.0 135 V μA μA 450 Total Quiescent Current IQ 1x mode, IOUT = 2.5mA, IBLn(3) = 0.5mA, 5 LEDs on 1x mode, IOUT = 125mA, IBLn = 25mA, 5 LEDs on 1.5x or 2x mode, IOUT = 125mA, IBLn = 25mA, 5 LEDs on mA Charge Pump Electrical Specifications Maximum Total Output Current Backlight Current Setting Range Backlight Current Accuracy Backlight Current Matching(4) 1x Mode to 1.5x Mode Falling Transition Voltage 1.5x Mode to 1x Mode Hysteresis IOUT(MAX) IBL IBL_ACC IBL-BL V TRANS1x VHYST1x Sum of all active LED currents, VOUT ≤ 4.2V Nominal setting for BL1 – BL5 IBLn = 12mA IBLn = 12mA IOUT = 50mA, IBLn = 10mA, VOUT = 3.2V IOUT = 50mA, IBLn = 10mA, VOUT = 3.2V 125 0 -8 -3.5 ±1.5 ±0.5 3.22 250 25 8 +3.5 mA mA % % V mV 3 SC643 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Charge Pump Electrical Specifications (Cont.) 1.5x Mode to 2x Mode Falling Transition Voltage 2x Mode to 1.5x Mode Hysteresis Current Sink Off-State Leakage Current Pump Frequency LDO Electrical Specifications LDO1, LDO3, and LDO4 Voltage Setting Range LDO2 Voltage Setting Range Output Voltage Accuracy VLDOm(6) VLDO2 ΔVLDO VDm VD2 Current Limit ILIM ILDOm = 1mA, VIN = 2.9V to 4.2V, VLDOm = 2.8V ILDO2 = 1mA, VIN = 2.9V to 4.2V, VLDO2 = 1.8V VLDOm = 3.3V, ILDOm = 1mA to 100mA VLDO2 = 1.8V, ILDO2 = 1mA to 100mA 1.5V < VLDOm < 3.0V, f < 1kHz, CBYP = 22nF, ILDOm = 50mA, with 0.5VP-P supply ripple 1.2V < VLDO2 < 1.8V, f < 1kHz, CBYP = 22nF, ILDO2 = 50mA, with 0.5VP-P supply ripple 10Hz < f < 100kHz, CBYP = 22nF, CLDOm = 1μF, ILDOm = 50 mA, 1.5V < VLDOm < 3.0V 10Hz < f < 100kHz, CBYP = 22nF, CLDO2 = 1μF, ILDO2 = 50 mA, 1.2V < VLDO2 < 1.8V Nominal value for CLDOn 1 50 dB 60 Range of nominal settings Range of nominal settings ILDO = 1mA, TA = 25°C, 2.9V ≤ VIN ≤ 4.2V ILDO = 1mA to 100mA, 2.9V ≤ VIN ≤ 4.2V ILDOm = 150mA, VIN = VLDOm + VDm ILDO2 = 100mA, VIN = VLDO2 + VD2 200 2.1 7.2 mV 1.3 4.8 1.5 1.2 -3 -3.5 150 100 ±1.0 3.3 1.8 +3 +3.5 200 mV 150 mA V V % % V TRANS1.5x VHYST1.5x IBL/FL(OFF) fPUMP IOUT = 50mA, IBLn = 10mA, VOUT = 4.2V(5) IOUT = 50mA, IBLn = 10mA, VOUT = 4.2V(5) VIN = VBLn = 4.2V VIN = 3.2V 2.91 520 0.1 250 1 V mV μA kHz Dropout Voltage Line Regulation ΔVLINE 25 mV 20 Load Regulation ΔVLOAD PSRRm Power Supply Rejection Ratio PSRR2 en-LDOm Output Voltage Noise en-LDO2 75 μVRMS 50 Minimum LDO Capacitor (7) CLDO(MIN) μF 4 SC643 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Digital I/O Electrical Specifications (SPIF, ENL4) Input High Threshold (8) Input Low Threshold (8) Input High Current Input Low Current SemPulse Electrical Specifications (SPIF) SemPulse Start-up Time(9) Bit Pulse Duration (8) Duration Between Bits (8) Hold Time - Address (8) Hold Time - Data (8) Bus Reset Time (8) Shutdown Time(10) Fault Protection Output Short Circuit Current Limit IOUT(SC) TOTP Over-Temperature THYS Charge Pump Over-Voltage Protection VOVP VUVLO Under Voltage Lockout VUVLO-HYS 300 mV Notes: (1) Capacitors are MLCC of X5R type. Production tested with higher value capacitors than the application requires. (2) SPIF is high for more than 10ms (3) Subscript for all backlights (BLn), n = 1, 2, 3, 4 and 5. Subscripting for all LDOs (LDOn), n = 1, 2, 3, 4. (4) Current matching is defined as ± [IBL(MAX) - IBL(MIN)] / [IBL(MAX) + IBL(MIN)]. (5) Test voltage is VOUT=4.2V — a relatively extreme LED voltage — to force a transition during test. Typically VOUT=3.2V for white LEDs. (6) Subscript m = 1, 3, and 4 and applies only to LDO1, LDO3, and LDO4. (7) X5R or better “temperature stable” MLCC capacitor. (8) The source driver used to provide the SemPulse output must meet these limits. (9) The SemPulse start-up time is the minimum time that the SPIF pin must be held high to enable the part before commencing communication. (10) The SemPulse shutdown time is the minimum time that the SPIF pin must be pulled low to shut the part down. Hysteresis OUT pin open circuit, VOUT = VOVP Decreasing VIN 30 5.7 2.4 6.0 °C V V OUT pin shorted to GND Rising threshold 300 165 mA °C tSU tHI tLO tHOLDA tHOLDD tBR tSD SPIF is held high SPIF is held high SPIF is held high SPIF is pulled low 1 0.75 0.75 500 500 10 10 250 250 5000 ms μs μs μs μs ms ms VIH VIL IIH IIL VIN = 5.5V VIN = 2.9V VIN = 5.5V VIN = 5.5V -1 -1 1.6 0.4 +1 +1 V V μA μA 5 SC643 Typical Characteristics Battery Current (5 LEDs) — 25mA Each 200 VOUT = 3.65V, IOUT = 125mA, 25°C Backlight Efficiency (5 LEDs) — 25mA Each 100 VOUT = 3.65V, IOUT = 125mA, 25°C 180 Battery Current (mA) 90 % Efficiency 160 80 140 70 120 60 100 4.2 3.9 3.6 VIN(V) 3.3 3.0 2.7 50 4.2 3.9 3.6 VIN(V) 3.3 3.0 2.7 Battery Current (5 LEDs) — 12mA Each 100 VOUT = 3.45V, IOUT = 60mA, 25°C 100 Backlight Efficiency (5 LEDs) — 12mA Each VOUT = 3.45V, IOUT = 60mA, 25°C 90 Battery Current (mA) 90 % Efficiency 80 80 70 70 60 60 50 4.2 50 3.9 3.6 VIN(V) 3.3 3.0 2.7 4.2 3.9 3.6 VIN(V) 3.3 3.0 2.7 Battery Current (5 LEDs) — 5.0mA Each 60 VOUT = 3.28V, IOUT = 25mA, 25°C Backlight Efficiency (5 LEDs) — 5.0mA Each 100 VOUT = 3.28V, IOUT = 25mA, 25°C 50 90 Battery Current (mA) % Efficiency 3.9 3.6 3.3 3.0 2.7 40 80 30 70 20 60 10 4.2 50 VIN(V) 4.2 3.9 3.6 VIN(V) 3.3 3.0 2.7 6 SC643 Typical Characteristics (continued) PSRR vs. Frequency — 1.8V 0 -10 -20 VIN=3.7V, VOUT =1.8V, IOUT = 50mA 0 -10 -20 PSRR vs. Frequency — 2.8V VIN=3.7V, VOUT =2.8V, IOUT = 50mA PSRR (dB) PSRR (dB) -30 -40 -50 -60 -70 10 -30 -40 -50 -60 -70 10 100 Frequency (Hz) 1000 10000 100 Frequency (Hz) 1000 10000 Line Regulation (LDO2) 1 0.75 ILDO2 = 1mA, VLDO2 = 1.2V to 1.8V, 25°C 3 Line Regulation (LDOm) ILDOm = 1mA, 25°C, VLDOm = 1.5V to 3.3V, m = 1, 3, or 4 2 Output Voltage Variation (mV) 0.5 0.25 0 -0.25 -0.5 -0.75 -1 4.2 3.9 3.6 3.3 VIN (V) 3.0 Output Voltage Variation (mV) 1 2.8V 1.8V 1.2V 0 -1 -2 2.7 -3 4.2 3.9 3.6 VIN (V) 3.3 3.0 2.7 LDO Noise vs. Load Current — 1.8V 100 VLDO=1.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz LDO Noise vs. Load Current — 2.8V 100 VLDO=2.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz 80 80 Noise (μVRMS) Noise (μVRMS) 60 60 40 40 20 20 0 0 20 40 IOUT (mA) 60 80 100 0 0 30 60 IOUT (mA) 90 120 150 7 SC643 Typical Characteristics (continued) Load Regulation (LDO2) 0 VIN=3.6V, 25°C 0 Load Regulation (LDOm) VIN=3.6V, 25°C, m = 1, 3, or 4 Output Voltage Variation (mV) Output Voltage Variation (mV) -5 1.2V -10 -5 1.5V 1.8V -10 2.5V -15 2.8V -20 3.3V -25 1.5V -15 -20 1.8V -25 0 40 80 ILDO (mA) 120 160 200 -30 0 40 80 ILDO (mA) 120 160 200 LDO Load Transient Response (3.3V) VIN=3.7V, VLDO=3.3V, ILDO=1 to 100mA, 25°C LDO Load Transient Response (1.2V) VIN=3.7V, VLDO=1.2V, ILDO=1 to 100mA, 25°C VLDO (50mV/div) VLDO (50mV/div) ILDO (100mA/div) ILDO (100mA/div) Time (20μs/div) Time (20μs/div) LDO Load Transient Response (1.8V) VIN=3.7V, VLDO=1.8V, ILDO=1 to 100mA, 25°C Output Short Circuit Current Limit VOUT=0V, VIN=4.2V, 25°C VOUT (1V/div) VLDO (50mV/div) ILDO (100mA/div) IOUT (200mA/div) Time (20μs/div) Time (1ms/div) 8 SC643 Typical Characteristics (continued) Ripple — 1X Mode VIN=3.8V, 5 Backlights — 25 mA each, 25°C Ripple — 1.5X Mode VIN=3.6V, 5 Backlights — 25 mA each, 25°C VIN (50mV/div) VIN (50mV/div) VOUT (100mV/div) VOUT (100mV/div) IBL (20mA/div) IBL (20mA/div) Time (20μs/div) Time (20μs/div) Ripple — 2X Mode VIN=2.9V, 5 Backlights — 25 mA each, 25°C VBL (500mV/div) VIN (50mV/div) Output Open Circuit Protection VIN=3.7V, 25°C 5.42V VOUT (1V/div) VOUT (100mV/div) IBL (20mA/div) IBL (20mA/div) Time (20μs/div) Time (200μs/div) 9 SC643 Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T Pin Name IN PGND BL3 BL2 BL1 BL4 BL5 ENL4 AGND LDO4 LDO3 SPIF BYP LDO2 LDO1 OUT C2+ C1+ C1C2THERMAL PAD Pin Function Battery voltage input Ground pin for high current charge pump Current sink output for backlight LED 3 — leave this pin open if unused Current sink output for backlight LED 2 — leave this pin open if unused Current sink output for backlight LED 1 — leave this pin open if unused Current sink output for backlight LED 4 — leave this pin open if unused Current sink output for backlight LED 5 — leave this pin open if unused Enable pin for LDO4 — active high. See LDO4 Control Register Section and Programmable LDO Outputs Section to determine how to use this pin. Analog ground pin — connect to ground and separate from PGND current Output of LDO4 Output of LDO3 SemPulse single wire interface pin — used to enable/disable the device and to configure all registers (refer to Register Map and SemPulse Interface sections) Bypass pin for LDO reference — connect a 22nF ceramic capacitor to AGND Output of LDO2 Output of LDO1 Charge pump output — all LED anode pins should be connected to this pin Positive connection to bucket capacitor 2 Positive connection to bucket capacitor 1 Negative connection to bucket capacitor 1 Negative connection to bucket capacitor 2 Thermal pad for heatsinking purposes — connect to ground plane using multiple vias — not connected internally 10 SC643 Block Diagram C2+ 17 VIN IN 1 C1+ 18 C119 C220 Fractional Charge Pump (1x, 1.5x, 2x) 16 OUT SPIF 12 SemPulse Digital Interface and Logic Control Oscillator 5 4 3 Current Setting DAC 6 7 BL1 BL2 BL3 BL4 BL5 BYP 13 LDO Voltage Reference Voltage Setting DAC PGND 2 VIN LDO1 AGND 9 VIN 15 LDO1 LDO2 VIN 14 LDO2 LDO3 VIN 11 LDO3 LDO4 ENL4 8 10 LDO4 11 SC643 Applications Information General Description This design is optimized for handheld applications supplied from a single cell Li-Ion and includes the following key features: should be equal in value, with a nominal capacitance of 2.2μF to support the charge pump current requirements. The device also requires a 4.7μF capacitor on the IN pin and a 4.7μF capacitor on the OUT pin to minimize noise and support the output drive requirements. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. • • • • A high efficiency fractional charge pump that supplies power to all LEDs Five matched current sinks that control LED backlighting current, with 0mA to 25mA per LED. Four adjustable LDOs. LDO1 , LDO3, and LDO4 are adjustable with 15 settings from 1.5V to 3.3V. LDO2 is adjustable with 7 settings from 1.2V to 1.8V. An external enable pin for LDO4 allows it to be used as a motor driver with hard-wired control. LED Backlight Current Sinks The backlight current is set via the SemPulse interface. The current is regulated to one of 29 values between 0mA and 25mA. The step size varies depending upon the current setting. Between 0mA and 5mA, the step size is 0.5mA. The step size increases to 1mA for settings between 5mA and 21mA. Steps are 2mA between 21mA and 25mA. The variation in step size allows finer adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in LED brightness. A zero setting is also included to allow the current sink to be disabled by writing to either the enable bit or the current setting register for maximum flexibility. All backlight current sinks have matched currents, even when there is variation in the forward voltages (ΔVF ) of the LEDs. A minimum ΔVF of 1.2V is supported when the input voltage (VIN) is at 3.0V. Higher ΔVF LED mis-match is supported when VIN is higher than 3.0V. All current sink outputs are compared and the lowest output is used for setting the voltage regulation at the OUT pin. This is done to ensure that sufficient bias exists for all LEDs. The backlight LEDs default to the off state upon powerup. For backlight applications using fewer than five LEDs, any unused output must be left open and the unused LED must remain disabled. When writing to the backlight enable register, a zero (0) must be written to the corresponding bit of any unused output. High Current Fractional Charge Pump The backlight outputs are supported by a high efficiency, high current fractional charge pump output. The charge pump multiplies the input voltage by 1, 1.5 or 2 times. The charge pump switches at a fixed frequency of 250kHz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve efficiency. The mode selection circuit automatically selects the mode as 1x, 1.5x, or 2x based on circuit conditions such as LED voltage, input voltage, and load current. The 1x mode is the most efficient of the three modes, followed by 1.5x and 2x modes. Circuit conditions such as low input voltage, high output current, or high LED voltage place a higher demand on the charge pump output. A higher numerical mode (1.5x or 2x) may be needed momentarily to maintain regulation at the OUT pin during intervals of high demand. The charge pump responds to momentary high demands, setting the charge pump to the optimum mode to deliver the output voltage and load current while optimizing efficiency. Hysteresis is provided to prevent mode toggling. The charge pump requires two bucket capacitors for proper operation. One capacitor must be connected between the C1+ and C1- pins and the other must be connected between the C2+ and C2- pins as shown in the typical application circuit diagram. These capacitors 12 SC643 Applications Information (continued) Backlight Quiescent Current The quiescent current required to operate all five backlights is reduced when backlight current is set to 4.0mA or less. This feature results in higher efficiency under lightload conditions. Further reduction in quiescent current will result from using fewer than five LEDs. both the main and the sub displays. The state diagram in Figure 1 describes all possible conditions for a fade operation. More details can be found in the Register Map section. Immediate change to new bright level Write new bright level FADE=0 Write FADE=1 No change Main and Sub Backlight Bank Configuration The five LED backlight drivers can be configured as a single bank or as two independent banks — one dedicated for a main display and the other for a sub display. This feature allows the device to drive two sets of LEDs with different settings so different current and fade settings can be used. The Register Map contains two separate control registers for main and sub currents. Register 01h contains the current setting code for the main bank, and register 02h contains the setting code for the sub bank. There are also three bits in register 0Ah that control which drivers are assigned to each display. The default setting assigns all five LED drivers to the main display control register. In this scenario, the current control settings for each LED driver come from register 01h. Other settings are available that allow the groupings to be defined so that any number from 1 to 5 drivers can be grouped as the main display backlight drivers, with the remaining drivers assigned to the sub display backlight by default. See Table 8 of the Register Map section for more details. FADE=0 Write FADE=0 Immediate change to new bright level Write FADE=0 FADE=1 No change FADE=1 Write FADE=1 Write new bright level Fade ends Fade begins Fade is redirected toward the new value from current state Write new bright level Write new fade rate Note: (1) When the data in backlight enable register 00h is not 00h Fade=0 No change Write Fade=1 Fade processing(1) Continue fade using new rate Backlight Fade-in and Fade-out Function Register 09h contains bits that control the fade state of each display (main and sub). When enabled, the fade function causes the backlight settings to step from their current state to the next programmed state as soon as the new state is stored in its register. For example, if the backlight is set at 25mA and the next setting is the off state, the backlight will step from 25mA down to 0mA using all 29 settings at the fade rate specified by the bits in register 09h. The same is true when turning on or increasing the backlight current — the backlight current will step from the present level to the new level at the step rate defined in register 09h. This process applies for Figure 1 — State Diagram for Fade Function Fade-In from Off State When the initial state of the main or sub backlight current register is 00h (the data value for 0mA), fading to an on state is accomplished by following the steps listed in Table 1. Following these steps explicitly will ensure that the fade-in operation will proceed with no interruption at the rate specified in the Main/Sub Backlight Fade register (09h). This procedure must be followed regardless of which backlight grouping configuration is being used. Note that it is only necessary to set the BLEN bits for the main or sub display that is required to fade. 13 SC643 Applications Information (continued) Table 1 — Fade-In from Off State Command Sequence 1. Disable fade for the bank 2. Set the bank to 0.5mA 3. Enable fade Action Write to register 09h Write to register 01h and/or 02h(1) Write to register 09h Data 00h 04h Binary value xx1xx0, xx1xx1, or xx0xx1 Any value from 01h through 1Fh Any value from 05h through 1Fh steps explicitly will ensure that the fade-in/fade-out operation will proceed with no interruption at the rate specified in the Main/Sub Backlight Fade register (09h). This procedure must be followed regardless of the backlight grouping configuration. Table 3 — Fading between Different On States Command Sequence 1. Enable fade Action Data Any value from 01h through 3Fh (but not 00h) Any value from 05h through 1Fh 4. Set BLEN bits Write to register 00h Write to register 09h 5. Set new value of Write to register 01h backlight current and/or 02h for the bank Notes: (1) Write only to the banks which will fade 2. Set new value of backlight current Write to register 01h and/or 02h Fade-Out from any On State to Off State Fading the backlight LEDs from any active state to the off state follows a simple procedure. The sequence of commands for this action is shown in Table 2. Following these steps explicitly will ensure that the fade-out operation will proceed with no interruption at the rate specified in the Main/Sub Backlight Fade register (09h). This procedure must be followed regardless of the backlight grouping configuration. Table 2 — Fade-Out from any On State to Off State Command Sequence 1. Enable fade Additional Information For more details about the Fade-in/Fade-out function, refer to the SC643 Backlight Driver Software User’s Guide and SemPulse Interface Specification document and to the associated software drivers available for this device (contact your sales office for more details). Programmable LDO Outputs Four low dropout (LDO) regulators are included to supply power to peripheral circuits. Each LDO output voltage setting has ±3.5% accuracy over the operating temperature range. Output current greater than specification is possible at somewhat reduced accuracy (refer to the typical characteristic section of this datasheet for load regulation examples). LDO1, LDO3, and LDO4 have identical specifications, with a programmable output ranging from 1.5V to 3.3V. LDO2 is specified to operate with programmable output ranging from 1.2V to 1.8V. LDO2 also has lower noise specifications so that it can be used with noise sensitive circuits. LDO4 is controlled by both the enable pin ENL4 and the LDO4 control register. ENL4 may be permanently connected to VIN for software-only control. Alternately, power sequencing logic may be used to enable LDO4 via the ENL4 pin after writing to the LDO4 control register. Action Data Any value from 01h through 3Fh (but not 00h) Write to register 09h 2. Set Main and/or Sub backlights to 0mA Write to register 01h and/or 02h 00h Fading Between Different On States Fading from one backlight level to another (up or down) also follows a simple procedure. The sequence of commands for this action is shown in Table 3. Following these 14 SC643 Applications Information (continued) Shutdown Mode The device is disabled when the SPIF pin is held low for the shutdown time specified in the electrical characteristics section. All registers are reset to default condition at shutdown. Typical current consumption is this mode is 0.1μA device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. All register information is retained during thermal shutdown. Hysteresis of 30°C is provided to ensure that the device cools sufficiently before re-enabling. Charge Pump Output Current Limit The device limits the charge pump current at the OUT pin. When OUT is shorted to ground, the output current will typically equal 300mA. The output current is also limited to 300mA when over loaded resistively. LDO Current Limit The device limits the current at all LDO output pins. The minimum limit is 200mA, so load current of greater than the rated current can be used (with degraded accuracy) without tripping the current limit. LED Float Detection Float detect is a fault detection feature of the LED backlight outputs. If an output is programmed to be enabled and an open circuit fault occurs at any backlight output, that output will be disabled to prevent a sustained output OVP condition from occurring due to the resulting open loop. Float detect ensures device protection but does not ensure optimum performance. Unused LED outputs must be disabled to prevent an open circuit fault from occurring. Sleep Mode When all backlights are off the charge pump is disabled, and sleep mode is activated. This is a reduced current mode that helps minimize overall current consumption. In sleep mode, the S emPulse i nterface continues to monitor its input for commands from the host. Typical current consumption in this mode is 90μA. Protection Features The SC643 provides several protection features to safeguard the device from catastrophic failures. These features include: • • • • • Output Open Circuit Protection Over-Temperature Protection Charge Pump Output Current Limit LDO Current Limit LED Float Detection Output Open Circuit Protection Over-Voltage Protection (OVP) at the OUT pin prevents the charge pump from producing an excessively high output voltage. In the event of an open circuit between the OUT pin and all current sinks (no loads connected), the charge pump runs in open loop and the voltage rises up to the OVP limit. OVP operation is hysteretic, meaning the charge pump will momentarily turn off until VOUT is sufficiently reduced. The maximum OVP threshold is 6.0V, allowing the use of a ceramic output capacitor rated at 6.3V with no concern of over-voltage damage. Typical OVP voltage is 5.7V. Over-Temperature Protection The Over-Temperature (OT) protection circuit prevents the device from overheating and experiencing a catastrophic failure. When the junction temperature exceeds 165°C, the Thermal Management The device has the potential for peak power dissipation equal to 2.7W when all outputs are simultaneously operating at maximum rated current and powered by a fully charged Li-Ion cell equal to 4.2V. A calculation of the maximum power dissipation of the device should be done to identify if power management measures are needed to prevent overheating. The MLP package is capable of dissipating 1.85W when proper layout techniques are used. 15 SC643 Applications Information (continued) PCB Layout Considerations The layout diagram in Figure 2 illustrates a proper twolayer PCB layout for the SC643 and supporting components. Following fundamental layout rules is critical for achieving the performance specified in the Electrical Characteristics table. The following guidelines are recommended when developing a PCB layout: • • • • • • Place all bypass and decoupling capacitors — C1, C2, CIN, COUT, CLDO1, CLDO2, CLDO3, CLDO4, and CBYP as close to the device as possible. All charge pump current passes through IN, OUT, and the bucket capacitor connection pins. Ensure that all connections to these pins make use of wide traces so that the resistive drop on each connection is minimized. The thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer. The following capacitors — CLDO1, CLDO2, CLDO3, CLDO4, and CBYP should be grounded together. Connect these capacitors to the ground plane at one point near the AGND pin as shown in Figure 2. • • Figure 3 shows the pads that should be connected to the ground plane with multiple vias. Make all ground connections to a solid ground plane as shown in Figure 4. If a ground layer is not feasible, the following groupings should be connected: PGND — CIN, COUT AGND — Ground Pad, CLDO1, CLDO2, CLDO3, CLDO4, CBYP If no ground plane is available, PGND and AGND should be routed back to the negative battery terminal, separately, using thick traces. Joining the two ground returns at the terminal prevents large pulsed return currents from mixing with the low-noise return currents of the LDOs. All LDO output traces should be made as wide as possible to minimize resistive losses. Ground Plane C2 VOUT COUT PGND Figure 3 — Layer 1 VIN C2- C1 CLDO1 CIN IN OUT C1+ C2+ C1- PGND LDO1 CLDO2 PGND LDO2 PGND BL3 SC643 BYP CBYP BL2 SPIF BL1 LDO3 CLDO3 AGND ENL4 BL4 BL5 LDO4 CLDO4 AGND Figure 2 — Recommended PCB Layout Figure 4 — Layer 2 16 SC643 SemPulse® Interface Introduction SemPulse is a write-only single wire interface. It provides access to up to 32 registers that control device functionality. Two sets of pulse trains are transmitted to generate a complete SemPulse command. The first pulse set is used to set the desired address. After the bus is held high for the address hold period, the next pulse set is used to write the data value. After the data pulses are transmitted, the bus is held high again for the data hold period to signify the data write is complete. At this point the device latches the data into the address that was selected by the first set of pulses. See the SemPulse Timing Diagrams for descriptions of all timing parameters. tHOLDD when the pulse train is completed. If the proper hold time is not received, the interface will keep counting pulses until the hold time is detected. If the total exceeds 63 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. After the bus has been held high for tHOLDD, the bus will expect the next pulse set to be an address write. Note that this is the same effect as the bus reset that occurs when tHOLDA exceeds its maximum specification. For this reason, there is no maximum limit on tHOLDD — the bus simply waits for the next valid address to be transmitted. Multiple Writes It is important to note that this single-wire interface requires the address to be paired with its corresponding data. If it is desired to write multiple times to the same address, the address must always be re-transmitted prior to the corresponding data. If it is only transmitted one time and followed by multiple data transmissions, every other block of data will be treated like a new address. The result will be invalid data writes to incorrect addresses. Note that multiple writes only need to be separated by the minimum tHOLDD for the slave to interpret them correctly. As long as tHOLDA between the address pulse set and the data pulse set is less than its maximum specification but greater than its minimum, multiple pairs of address and data pulse counts can be made with no detrimental effects. Chip Enable/Disable The device is enabled when the SemPulse interface pin (SPIF) is pulled high for greater than tSU. If the SPIF pin is pulled low again for more than tSD, the device will be disabled. Address Writes The first set of pulses can range between 0 and 31 (or 1 to 32 rising edges) to set the desired address. After the pulses are transmitted, the SPIF pin must be held high for tHOLDA to signal to the slave device that the address write is finished. If the pulse count is between 0 and 31 and the line is held high for tHOLDA, the address is latched as the destination for the data word. If the SPIF pin is not held high for tHOLDA, the slave device will continue to count pulses. If the total exceeds 31 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. Note that if tHOLDA exceeds its maximum specification, the bus will reset. This means that the communication is ignored and the bus resumes monitoring the pin, expecting the next pulse set to be an address. Standby Mode Once data transfer is completed, the SPIF line must be returned to the high state for at least 10ms to return to the standby mode. In this mode, the SPIF line remains idle while monitoring for the next command. This mode allows the device to minimize current consumption between commands. Once the device has returned to standby mode, the bus is automatically reset to accept the address pulses as the next data block. This safeguard is intended to reset the bus to a known state (waiting for the beginning of a write sequence) if the delay exceeds the reset threshold. Data Writes After the bus has been held high for the minimum address hold period, the next set of pulses are used to write the data value. The total number of pulses can range from 0 to 63 (or 1 to 64 rising edges) since there are a total of 6 register bits per register. Just like with the address write, the data write is only accepted if the bus is held high for 17 SC643 SemPulse® Interface (continued) SemPulse Timing Diagrams The SemPulse single wire interface is used to enable or disable the device and configure all registers (see Figure 5). The timing parameters refer to the digital I/O electrical specifications. Address is set Up to 32 rising edges (0 to 31 pulses) Up to 64 rising edges (0 to 63 pulses) Data is written SPIF t = tSU t = tHOLDA tHI tLO t = tHOLDD Figure 5 — Uniform Timing Diagram for SemPulse Communication Timing Example 1 In this example (see Figure 6), the slave chip receives a sequence of pulses to set the address and data, and the pulses experience interrupts that cause the pulse width to be non-uniform. Note that as long as the maximum high and low times are satisfied and the hold times are within specification, the data transfer is completed regardless of the number of interrupts that delay the transmission. Address is set to register 02h SPIF Data written is 000011 t = tSU tHI t < tHImax t = tHOLDA t < tLOmax tLO t = tHOLDD Figure 6 — SemPulse Data Write with Non-Uniform Pulse Widths Timing Example 2 In this example (see Figure 7), the slave chip receives a sequence of pulses to set the address and data, but an interrupt occurs during a pulse that causes it to exceed the minimum address hold time. The write is meant to be the value 03h in register 05h, but instead it is interpreted as the value 02h written to register 02h. The extended pulse that is delayed by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. To avoid any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this datasheet. Address is set to register 02h Data written is 000010 Address is set to register 03h (address and data are now out of order) SPIF Interrupt duration t > tHImax t = tHOLDA t = tHOLDD Figure 7 — Faulty SemPulse Data Write Due to Extended Interrupt Duration 18 SC643 Register Map(1) Address(2) 00h 01h 02h 05h 06h 07h 08h 09h 0Ah D5 0(3) 0(3) 0(3) 0(3) 0(3) 0(3) 0(3) SFADE1 0(3) D4 BL5EN MBL4 SBL4 0(3) 0(3) 0(3) 0(3) SFADE0 0(3) D3 BL4EN MBL3 SBL3 LDO1V3 0(3) LDO3V3 LDO4V3 SFADE 0(3) D2 BL3EN MBL2 SBL2 LDO1V2 LDO2V2 LDO3V2 LDO4V2 MFADE1 MB2 D1 BL2EN MBL1 SBL1 LDO1V1 LDO2V1 LDO3V1 LDO4V1 MFADE0 MB1 D0 BL1EN MBL0 SBL0 LDO1V0 LDO2V0 LDO3V0 LDO4V0 MFADE MB0 Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h Description Backlight Enable Main Backlight Current Sub Backlight Current LDO1 LDO2 LDO3 LDO4 Main/Sub Backlight Fade Main/Sub Bank Select Notes: (1) all registers are write-only (2) Addresses 03h and 04h are not used (3) 0 = always write a 0 to these bits Definition of Registers and Bits BL Enable Control Register (00h) This register enables the backlight current sinks. Bit D5 This bit is unused and is always a zero. BL5EN through BL1EN [D4:D0] These bits are used to enable current sinks. These current sinks will then sink whatever current is set in the corresponding current control register. Main Backlight Current Control Register (01h) This register is used to set the currents for the LED drivers designated as main backlight current sinks. Note these current sinks can be disabled using register 00h or by writing the 0mA value into this register. Bit D5 This bit is unused and is always a zero. 19 SC643 Register Map (continued) MBL4 through MBL0 [D4:D0] These bits are used to set the current for the main backlight current sinks. All enabled current sinks will sink the same current as shown in Table 4. Table 4 — Main Backlight Current Settings MBL4 MBL3 MBL2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Sub Backlight Current Control Register (02h) This register is used to set the currents for the LED drivers designated as sub backlight current sinks. Note these current sinks can be disabled using register 00h or by writing the 0mA value into this register. Bit D5 This bit is unused and is always a zero. MBL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MBL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Backlight Current (mA) 0 See note (1) See note (1) See note (1) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25 (1) Reserved for future use. 20 SC643 Register Map (continued) SBL4 through SBL0 [D4:D0] These bits are used to set the current for the sub backlight current sinks. All enabled current sinks will sink the same current as shown in Table 5. Table 5 — Sub Backlight Current Settings SBL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LDO1 Control Register (05h) This register is used to enable LDO1 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. LDO1V3 through LDO1V0 [D3:D0] These bits set the output voltage of LDO1 as shown in Table 6. Table 6 — LDO1 Control Codes LDO1V3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SBL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SBL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SBL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SBL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Backlight Current (mA) 0 See note (1) See note (1) See note (1) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25 LDO1V2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LDO1V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LDO1V0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VLDO1 OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2V 1.8V 1.7V 1.6V 1.5V (1) Reserved for future use. 21 SC643 Register Map (continued) LDO2 Control Register (06h) This register is used to enable LDO2 and set its output voltage level. Bits [D5:D3] These bits are unused and are always zeroes. LDO2V2 through LDO2V0 [D2:D0] These bits are used to set the output voltage of LDO2 in accordance with Table 7. Table 7 — LDO2 Control Codes LDO2V2 0 0 0 0 1 1 1 1 LDO3V3 through LDO3V0 [D3:D0] These bits are used to set the output voltage of LDO3 as shown in Table 8. Table 8 — LDO3 Control Codes LDO3V3 0 0 0 0 LDO3V2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LDO3V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LDO3V0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VLDO3 OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2v 1.8V 1.7V 1.6V 1.5V LDO2V1 0 0 1 1 0 0 1 1 LDO2V0 0 1 0 1 0 1 0 1 VLDO2 OFF 1.8V 1.7V 1.6V 1.5V 1.4V 1.3V 1.2V 0 0 0 0 1 1 1 1 1 1 LDO3 Control Register (07h) This register is used to enable LDO3 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. 1 1 22 SC643 Register Map (continued) LDO4 Control Register (08h) This register is used to enable LDO4 and set its output voltage level. The ENL4 pin must be high for register 08h to control LDO4. ENL4 has a logical AND function with the register contents. Therefore, if ENL4 is low, V LDO4=0V regardless of the contents of register 08h. Bits [D5:D4] These bits are unused and are always zeroes. LDO4V3 through LDO4V0 [D3:D0] These bits are used to set the output voltage of LDO4 as shown in Table 9. Table 9 — LDO4 Control Codes LDO4V3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MFADE1 and MFADE0 [D2:D1] These bits are used to set the rise/fall rate between two backlight currents for the main display as show in Table 10. For the fade feature to be active, the MFADE bit must be set. The number of steps required to change the backlight current will be equal to the change in binary count of bits MBL4 through MBL0. Table 10 — Main Display Fade Control Bits MFADE1 0 0 1 MFADE0 0 1 0 1 Fade Feature Rise/ Fall Rate (ms/step) 32 24 16 8 LDO4V2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LDO4V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LDO4V0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VLDO4 OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2V 1.8V 1.7V 1.6V 1.5V 1 MFADE [D0] This bit is used to enable or disable the fade feature. When MFADE is enabled and a new main backlight current is set, this current will change from its existing value to the new value written in MBL[4:0] at the rate determined by MFADE1 and MFADE0 (in ms/step). A new setting cannot be written during an ongoing fade operation, but an on-going fade operation may be cancelled by writing 0 to the MFADE bit. Clearing the MFADE bit during an ongoing fade operation changes the current immediately to the value of MBL[4:0]. The number of counts to complete a fade operation equals the difference between the old and new MBL[4:0] settings. If MFADE is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically by writing new values to the MFADE1 and MFADE0 bits. The total fade time is given by the number of steps between old and new backlight values (see Table 4), multiplied by the rate of fade in ms/step. Fade Control Register (09h) This register contains the fade enables and rate controls for both the main display and sub display LED driver banks. 23 SC643 Register Map (continued) SFADE1 and SFADE0 [D5:D4] These bits are used to set the rise/fall rate between two backlight currents for the sub display as show in Table 11. For the fade feature to be active, the SFADE bit must be set. The number of steps required to change the backlight current will be equal to the change in binary count of bits SBL4 through SBL0. Table 11 — Sub Display Fade Control Bits SFADE1 0 0 1 1 Bank Selection Register (0Ah) This register contains the bits that determine which LED drivers are assigned to the main display and which are part of the sub display bank. Bits [D5:D3] These bits are unused and are always zeroes. MB2, MB1, and MB0 [D2:D0] These bits are used to set the number of LED drivers dedicated to a main backlight function. This allows the device to drive two different sets of LEDs with different settings for use in products like clamshell-style mobile phones that have a main display and a sub display with different lighting requirements. Note that any driver not selected for the main display will automatically be assigned to the sub display set. The code set by these three bits determines which LED drivers are dedicated to the main display according to the assignments listed in Table 12. Table 12 — Main Display Driver Assignment Codes MB2 0 0 0 1 1 SFADE0 0 1 0 1 Fade Feature Rise/ Fall Rate (ms/step) 32 24 16 8 SFADE [D3] This bit is used to enable or disable the fade feature. When SFADE is enabled and a new main backlight current is set, the current will change from its existing setting to the new setting written in SBL[4:0] at the rate determined by SFADE1 and SFADE0 (in ms/step). A new setting cannot be written during an ongoing fade operation, but an ongoing fade operation may be cancelled by writing 0 to the SFADE bit. Clearing the SFADE bit during an ongoing fade operation changes the current immediately to the value of SBL[4:0]. The number of counts to complete a fade operation equals the difference between the old and new SBL[4:0] settings. If SFADE is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically by writing new values to the SFADE1 and SFADE0 bits. The total fade time is given by the number of steps between old and new backlight values (see Table 5), multiplied by the rate of fade in ms/step. MB1 0 1 1 0 0 MB0 1 0 1 0 1 Main Display LED Drivers BL1 - BL5 BL1 - BL4 BL1 - BL3 BL1 - BL2 BL1 BL1 - BL5 (default) Sub Display LED Drivers none BL5 BL4 - BL5 BL3 - BL5 BL2 - BL5 000 and 110 through 111 none 24 SC643 Outline Drawing — MLPQ-UT-20 3x3 A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .020 .024 0.50 0.60 .000 .002 0.00 0.05 (.006) (0.152) .006 .008 .010 0.15 0.20 0.25 .114 .118 .122 2.90 3.00 3.10 .061 .067 .071 1.55 1.70 1.80 .114 .118 .122 2.90 3.00 3.10 .061 .067 .071 1.55 1.70 1.80 .016 BSC 0.40 BSC .012 .016 .020 0.30 0.40 0.50 20 20 .003 0.08 .004 0.10 PIN 1 INDICATOR (LASER MARK) E A2 A aaa C A1 e LxN E/2 E1 2 1 N D/2 bxN bbb NOTES: 1. 2. 3. CAB C D1 SEATING PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DAP IS 1.90 x 1.90mm. 25 SC643 Land Pattern — MLPQ-UT-20 3x3 K R DIM C G H K P R X Y Z (.114) .083 .067 .067 .016 .004 .008 .031 .146 DIMENSIONS INCHES MILLIMETERS (2.90) 2.10 1.70 1.70 0.40 0.10 0.20 0.80 3.70 (C) H G Z Y X P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 3. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 26