SC905MLTRT

CDMA Cellular Phone Power Management IC POWER MANAGEMENT Description The SC905 is a power management integrated circuit (PMIC) designed for the latest CDMA chip sets. The device provides four general purpose low dropout regulators (LDOs), and five low noise LDOs designed for analog circuits. The VMOT LDO can be used as a general purpose regulator or as an adjustable motor drive output that can supply up to 150mA to drive a vibrator motor. Each LDOs enable and output voltage are controlled via the I2C bus. An optional three-wire interface compatible with Semtech battery charger ICs is also controlled via the I2C bus. Initial power-on is achieved by activating either the ON or the HFPWR signal, and the PGOOD input is used by the microprocessor to latch power on or disable the device. The small and thermally efficient MLPQ-32 package and use of ceramic bypass capacitors, minimize the required PCB area making the SC905 ideal for space-conscious portable applications. SC905 Features 9 LDO Linear Regulators CORE: 1.35V - 2.90V @ 300mA ANA: 2.55V - 2.90V @ 200mA PAD: 1.35V - 2.90V @ 300mA RX: 2.55V - 2.90V @ 150mA TX: 2.55V - 2.90V @ 150mA TCXO: 2.55V - 2.90V @ 80mA PLL: 2.55V - 2.90V @ 80mA Camera: 1.35V - 2.90V @ 100mA Motor Drive: 1.35V - 2.90V @ 150mA I2C Interface for Microprocessor Control Less than 1μA Quiescent Current in Shutdown 65dB PSRR for Analog LDOs Over-Temperature Protection Power-On Control Optional Interface for Controlling Semtech Battery Chargers Small 5mm x 5mm 32-Pin QFN Package Applications CDMA Cellular Handsets Palmtop/Laptop Computers Battery Powered Equipment Typical Application Circuit VBAT SC905 Battery Charger Circuit ON/OFF Handsfree Option 0.1μF MOTOR VBAT IN1 IN2 IN3 IN4 IN5 IN6 ON DVIN HFPWR VCORE PGOOD VPAD SDA VANA SCL VTCXO PWRON VPLL RESB VTX VRX VMOT VCAM BP VPSEL VCSEL AGND DGND CPB CHRGB FAULTB 1μF 10μF BATTERY TCXO + Synthesiser PLL 1μF Transmitter Section 1μF 1μF 1μF PA Receiver Section Baseband Processor LNA 1μF 1μF 1μF Camera Module Audio Processing Keypad Digital Interface June 7, 2006 1 www.semtech.com SC905 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Input Supply Voltage Digital Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Peak IR Reflow Temperature Storage Temperature Thermal Resistance Junction to Ambient ESD Protection Level(2) (1) Symbol VIN VDIG TA TJ TLEAD TSTG θJA ESD Maximum -0.3 to +7 -0.3 to VIN+0.3 -40 to +85 -40 to +125 260 -60 to +150 26 2 Units V V °C °C °C °C °C/W kV (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted VIN = 3.7V, TA = -40 to +85°C. Typical values are at TA = +25°C. Parameter General Supply Voltage Shutdown Current Quiescent Supply Current Supply Bypass Capacitor Start-Up Time Under-Voltage Lockout Over-Temperature Digital Inputs Digital Input Voltage(1) Digital Input Current Digital Outputs Digital Output Voltage(2) LDO Regulator (CORE) - 300mA Output Voltage Accuracy(3) Current Limit Default At Start-Up: ON © 2006 Semtech Corp. Symbol Condition Min Typ Max Units VIN ISD ISU ISTBY CVCC tSU UVLO OT 2 2.7 ON = 0V, HFPWR = 0V, PGOOD = 0V Default Start-up Mode I C, VREF Active, All Outputs Disabled At Each Power Input Pin CBP = 0.1μF Descending, Hysteresis = 50mV Hysteresis = 20°C 300 30 1 25 2.5 160 5.5 1 V μA μA 60 μA μF ms V °C VIL VIH IDIG Logic Level High or Low 1.25 -0.2 0.4 V V 0.2 μA VOL VOH ISINK = 1.2mA ISOURCE = 0.5mA, VPAD ≥ 1.8V 90 2 98 10 %VPAD %VPAD ∆VOUT ILIM VOUT-HI VOUT-LO 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VCORE = 0V VCSEL - High VCSEL - Low 2 -75 350 1.80 1.35 +75 900 mV mA V V www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units LDO Regulator (CORE) - 300mA (Cont.) Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio LDO Regulator (PAD) - 300mA Output Voltage Accuracy(3) Current Limit Default at Start-up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio LDO Regulator (ANA) - 200mA Output Voltage Accuracy(4) Current Limit Default At Start-up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (TCXO) - 80mA Output Voltage Accuracy(4) Current Limit Default At Start-up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRTCXO IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 80mA VOUT = 2.90V, IOUT = 80mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VTCXO = 0V -75 250 2.85 2.5 -3 200 65 12 -20 250 +75 650 mV mA V mV mV mV dB ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRANA en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 200mA VOUT = 2.90V, IOUT = 200mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA f = 10Hz to 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VANA = 0V -75 250 2.60 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB μVRMS ∆VOUT ILIM VOUT-HI VOUT-LO REGLINE REGLOAD VDO PSRRPAD 1.35V ≤ VOUT ≤ 2.90V, IOUT =1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VPAD = 0V VPSEL - High VPSEL - Low IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 300mA VOUT = 2.90V, IOUT = 300mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA -75 350 2.60 1.80 2.5 -3 300 50 12 -30 350 +75 900 mV mA V V mV mV mV dB REGLINE REGLOAD VDO PSRRCORE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 300mA VOUT = 2.90V, IOUT = 300mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 2.5 -3 300 50 12 -30 350 mV mV mV dB © 2006 Semtech Corp. 3 www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units LDO Regulator (TCXO) - 80mA (Cont.) Output Voltage Noise LDO Regulator (TX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (RX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (CAM) - 100mA Output Voltage Accuracy(3) Current Limit Default At Start-up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRCAM IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 100mA VOUT = 2.90V, IOUT = 100mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA VOUT +0.35V ≤ VIN ≤ 5.5V VCAM = 0V -75 250 1.80 2.5 -3 200 50 12 -20 250 +75 650 mV mA V mV mV mV dB ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRRX en IOUT = 1mA, VOUT+0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 2.90V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA f = 10Hz - 100kHz, IOUT = 50mA, CBP= 0.1μF, COUT = 1μF 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VRX = 0V -75 250 2.85 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB μVRMS ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRTX en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 2.90V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VTX = 0V -75 250 2.85 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB μVRMS en f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 45 μVRMS © 2006 Semtech Corp. 4 www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter LDO Regulator (PLL) - 80mA Output Voltage Accuracy(4) Current Limit Default At Start Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (MOT) - 150mA Output Voltage Accuracy(3) Current Limit Default at Start Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRMOT IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 2.90V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VMOT = 0V -75 250 1.40 2.5 -3 200 50 12 -20 250 +75 650 mV mA V mV mV mV dB ∆VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRPLL en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 80mA VOUT = 2.90V, IOUT = 80mA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA f = 10Hz - 100kHz, I OUT = 50mA, CBP= 0.1μF, COUT = 1μF 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V VPLL = 0V -75 250 2.85 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB μVRMS Symbol Condition Min Typ Max Units © 2006 Semtech Corp. 5 www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units I2C Interface(5) Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January, 2000. VIL Digital Input Voltage SDA Output Low Level Digital Input Current Hysteresis of Schmitt Trigger Inputs Maximum Glitch Pulse Rejection I/O Pin Capacitance I2C Timing(5) Clock Frequency SCL Low Period SCL High Period Data Hold Time Data Setup Time Setup Time for Repeated START Condition Hold Time for Repeated START Condition Setup Time for STOP Condition Bus-Free Time Between STOP and START RESET Timeout Delay Power-up Delay Between CORE, ANA, PAD, TXCO Maximum Glitch Pulse Rejection Interface Start-up Time fSCL tLOW tHIGH tHD_DAT tSU_DAT tSU_STA tHD_STA tSU_STO tBUF tRD tDELAY tSP tEN Bus Start-up Time After EN Pin is Pulled High Delay Between Each Output Activating 1.3 0.6 0 100 0.6 0.6 0.6 1.3 75 100 100 50 350 125 400 440 kHz μs μs μs ns μs μs μs μs ms μs ns μs IDG VHYS tSP CIN VIH IDIN (SDA) ≤ 3mA -0.2 0.1 50 10 1.25 0.4 0.2 0.4 V V V μA V ns pF Notes: (1) Applies to pin names, CPB, CHRGB, FAULTB, ON, HFPWR, PGOOD, VCSEL, VPSEL. (2) Applies to pin names, PWRON, RESB. (3) For VOUT settings see Table A. (4) For VOUT settings see Table B. (5) Guaranteed by design. © 2006 Semtech Corp. 6 www.semtech.com SC905 POWER MANAGEMENT Pin Configuration VMOT VCAM IN5 VTCXO VANA VRX Ordering information DEVICE SC905MLTRT(1) 24 23 VTX IN6 VPLL AGND VBAT BP PGOOD RESB PACKAGE MLP 5x5 32L(2) Evaluation Board IN3 IN4 32 IN2 VCORE IN1 VPAD ON HFPWR SDA SCL 1 2 3 4 5 6 7 8 9 31 30 29 28 27 26 25 SC905EVB TOP VIEW 22 21 20 Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. T 19 18 17 10 11 12 13 14 15 16 FAULTB DGND DVIN MLPQ32: 5X5 32 Lead © 2006 Semtech Corp. PWRON CHRGB CPB VPSEL VCSEL 7 www.semtech.com SC905 POWER MANAGEMENT Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 T Pin Name IN2 VCORE IN1 VPAD ON HFPWR SDA SCL DGND DVIN CHRGB CPB FAULTB VPSEL VCSEL PWRON RESB PGOOD BP VBAT AGND VPLL IN6 VTX VTCXO IN5 VRX VANA IN4 VCAM IN3 VMOT Thermal Pad I/O Input Output Input Output Input Input Pin Function Input voltage terminal to VCORE LDO. 300mA LDO output for MSM core processor supply. Input voltage terminal to VPAD LDO. 300mA LDO PAD output to MSM I/O circuits. Active high power on/off key. When the push button is closed it is shorted to battery. Power on input from accessory, active high. Input/Output Bi-directional open drain digital I/O. I2C serial data. Input Digital input. I2C serial clock. Input Input Input Input Input Input Output Output Input Output Input Output Input Output Output Input Output Output Input Output Input Output Digital ground. Main digital input voltage terminal. Logic input. State is recorded in bit 1 of the status register. Logic input. State is recorded in bit 0 of the status register. Logic input. State is recorded in bit 2 of the status register. Default control for VPAD LDO supply. Ground for 1.80V default, tie high for 2.60V. Default control for VCORE LDO supply. Ground for 1.35V default, tie high for 1.80V. Logic OR output of ON, HFPWR and PGOOD. Active high. Reset output. Active low. Logic input signal from MSM to indicate power is good, latches the SC905 on. Low disables the SC905. LDO bypass output. Bypass with a 0.1μF capacitor. Main battery supply input terminal. Analog ground pin. LDO output for PLL power. Input voltage terminal for VPLL & VTX LDOs. LDO output for transmitter power. LDO output for TCXO power. Input voltage terminal for VTCXO & VRX LDOs. LDO output for receiver power. LDO output for analog power. Input voltage terminal to VANA LDO. LDO output for camera power. Input voltage terminal to VCAM & VMOT LDOs. LDO output voltage for vibrator motor power. Can also be a general purpose output. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally. © 2006 Semtech Corp. 8 www.semtech.com SC905 POWER MANAGEMENT Block Diagram 19 ON HFPWR PGOOD 5 6 18 BP PWRON logic VREF OT UVLO VPAD PWRON 16 VPAD RESB 17 RESET EN 3 IN1 VPAD PAD EN 4 1 2 IN2 VCORE EN REG EN CHRGB FAULTB CPB 11 13 12 EN CTRL CORE EN 31 IN3 VCAM CAM EN 30 VPSEL VCSEL 14 15 I2C Interface I2C Registers & Controls MOT EN 32 VMOT 29 IN4 VANA ANA EN 28 26 IN5 VTCXO SDA SCL 7 8 EN TCXO 25 RX VBAT DVIN 20 10 EN 27 VRX 23 IN6 VPLL PLL EN 22 DGND AGND 9 21 TX 24 VTX © 2006 Semtech Corp. 9 www.semtech.com SC905 POWER MANAGEMENT Applications Information General Description The SC905 includes 9 low dropout (LDO) voltage regulators to provide complete power regulation capability for CDMA handsets or other portable electronic equipment. Five of the LDOs are designed to be used with analog circuitry such as audio, radio frequency, or oscillator circuits. These devices have very low noise levels and high power supply rejection. The output voltage range for these LDOs is 2.55V to 2.9V in 50mV steps. The outputs for these LDOs are VANA, VTCXO, VPLL, VTX, and VRX. Three other LDOs are general purpose regulators designed to be used with digital circuits. The noise requirements for these LDOs are relaxed, but their voltage range is expanded to cover the wide range of voltages needed for different types of functions. The outputs for these LDOs are VCORE, VPAD, and VCAM. The VMOT output is specifically designed to drive a vibrator motor. This output can supply up to 150mA with voltage settings from 1.35V to 2.9V, allowing designers the flexibility to select the output voltage that provides maximum vibration. When not used in conjunction with a vibrator, this output can be used as a general purpose digital regulator. Power-On Control The SC905 is activated when the ON pin is pulled high, provided that the input voltage is within the specified operating range. The ON pin responds to logic-high edge triggering to power up the handset. The rising edge ON signal is latched when the CORE, PAD, ANA, and TCXO LDOs are turned on and PGOOD goes high. When the PAD LDO output voltage reaches 77% of its regulation point, the reset timer starts and the RESB signal transitions high after delay of typically 100ms. After a successful power up sequence, any subsequent condition that toggles RESB (e.g. VPAD short-circuit, over-temperature, under voltage lockout, I2C disable of VPAD) will see a delay in the RESB transition back to high of typically 250ms. The microprocessor then raises PGOOD high to keep the SC905 powered on. There is no time limit for the MSM to activate PGOOD. If the MSM fails to raise PGOOD before the ON switch is released, the SC905 will transition back into standby mode. Once the phone is powered on, the SC905 can only be directly powered off when the PGOOD signal goes low. Therefore, if the ON pin transitions high when the PGOOD signal is high, the LDOs and RESB signal will remain in their state until the microprocessor pulls the PGOOD signal low. Once the PGOOD signal is low, all the LDOs immediately power off and all the logic resets to the shutdown condition. The SC905 can be indirectly powered off by using the I2C command to turn off the core supply. This will result in a loss of power to the MSM causing PGOOD to go low, thus disabling the SC905. The HFPWR pin operates identically to the ON pin. This pin provides a second source for activating power so that remote devices such as battery chargers or system connector pins can be used to enable the device. LDO Programmable Output Voltage The output voltage of each LDO regulator is programmable. Each LDO has a program voltage register that can be accessed through the I2C interface and the output voltage adjusted as necessary. (See the Tables on page 14 and 15 for more information.) ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bits to 1 and disabled by setting the on/off bits to 0. This allows for on/off control with a single write command. When an on/off bit is toggled, the registered data is maintained. However, all programmed information will be lost when the PGOOD input goes low. VCSEL & VPSEL Pin The VCSEL & VPSEL pins set the default voltage of CORE and PAD LDOs respectively. When the VCSEL pin is set to VIN the default voltage for the CORE LDO is 1.80V. When this pin is set to GND the default voltage for the CORE LDO is 1.35V. Likewise, when the VPSEL pin is set to VIN the default voltage for the PAD LDO is 2.60V. When this pin is set to GND, the default voltage for the PAD LDO is 1.80V. In both cases the VCSEL and VPSEL pins must be tied to GND or VIN prior to the device being powered on. This voltage cannot change “on the fly” by switching the pin voltage between VIN or GND once the device is on. © 2006 Semtech Corp. 10 www.semtech.com SC905 POWER MANAGEMENT Applications Information (Cont.) The voltage can be changed from its default state after start-up by writing to the appropriate voltage code register. Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Register 7 is the active shutdown control register and is used to control the shutdown behavior. Each LDO has a specific shutdown bit assigned to it. When the active shutdown bit is enabled (set to 1), the output capacitance on the LDO output is discharged by an on-chip FET when the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default state for each LDO active shutdown bit is on. Default Status Bit In many multi-threaded environments it is necessary to maintain synchronization between the host micro-controller and the target IC. The SC905 has a default status bit (DSB) that will facilitate this task. The DSB can be useful in keeping the MSM and the SC905 synchronized. However, this is only useful if the MSM is powered by an external switching regulator such as the SC190. The DSB is bit 7 of register 0, and shares this register space with the PAD voltage control bits. The DSB is only set to 1 during power-up to indicate that the part is set to the default state. Moreover, the DSB cannot be written to a 1 through the I2C interface the way the other bits in this register can; it can only be cleared to 0 through the I2C interface. This feature prevents a software race condition by always writing to register 0 with bit 7 high when changing the PAD control voltage. To clear the bit simply write a 0 to bit 7. Applying the DSB Upon power-up, the SC905 LDOs and internal registers are set to their default state. The DSB is set to a 1 to indicate that the SC905 is in its default state. Upon reading this defaulted state condition, the MSM knows to perform whatever synchronization is needed to set the SC905 into a known user state. This user state is entered by a twostage process. 1) The MSM writes a 0 to the DSB indicating its desire to modify the state of the SC905. It then writes all of the correct register information to the SC905 to set it to the user state. 2) The MSM reads back all of the information to verify the data. Then it reads back the DSB again to ensure it is still set to 0. This verifies that no reset took place during the time that the multiple writes and read verifications happened. If the DSB has been reset to 1, this process needs to be repeated since the chip was reset sometime during the initialization. Once the MSM and the SC905 are synchronized, the DSB can be read back as a status check periodically, as needed. If it is ever set back to the default state, a new synchronization process is required. This handshake-style protocol makes sure that the MSM and SC905 are always synchronized. LDO Power-On Sequence When the SC905 first turns on, the four LDOs that default on are sequenced in the following fashion: CORE is the first to turn on, then PAD, then ANA and finally TCXO. During the power-on sequence, each LDO has a 100μs delay from one LDO turning on to the other. This process eliminates large voltage spikes across the battery supply during power-up. For further information on LDO power on sequencing, refer to the Timing Diagram on page 17. Protection Circuitry The SC905 contains protection circuitry that prevents the device from operating in an unspecified state. These include Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under-Voltage Lockout The SC905 provides an under-voltage lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, as defined in the Electrical Characteristics section, the LDOs are disabled and RESB is held low. When the battery voltage is increased above the hysteresis level, the LDOs are re-enabled into their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. When powering-up with a battery voltage below the UVLO threshold, RESB will be held low. © 2006 Semtech Corp. 11 www.semtech.com SC905 POWER MANAGEMENT Applications Information (Cont.) Over-Temperature Protection The SC905 provides an internal over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold as defined in the Electrical Characteristics section, the OT protection disables all the LDO outputs, holds the RESB signal low and sets the OTF bit low in the status register. When the junction temperature drops below the hysteresis level, the OT protection resets the OTF bit high and re-enables all the LDOs in their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. This is only useful if the MSM is not powered by the SC905, since during an OT fault the MSM will lose power. An external switching regulator such as the SC190A could power the MSM in the case where monitoring the OTF bit is desired. Short-Circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed. Interfacing to Semtech Battery Chargers The SC905 is designed to interface with Semtech battery chargers by providing three control inputs that map the state of the controls to register bits so the host processor can monitor the charger’s status via the I2C interface. For open-drain control outputs from the charger, pull-up resistors must be connected to the lines for the SC905 registers to display the correct status. Status Register The status register monitors these inputs for changes, and the MSM can periodically poll this register to determine the status of the charger. This is a read-only register. This register is useful when the MSM needs to determine charging status before performing an LCD update. The MSM can control other aspects of the charger with general purpose I/O. These include enable/disable and charge time-out functions. Many of the chargers functions can be statically set and do not need MSM intervention. The amount of MSM intervention is determined by the intended application. The following table is a summary of the status register inputs and their functions: CONDITION FAULTB is Low CPB is Low CHRGB is Low CHRGB & FAULTB is Low FUNCTION Charger Fault USB or AC Charger Present Charging in Progress Battery Fault Layout Considerations The PCB layout associated with the SC905 is straight forward, with the main consideration being given to the value and position of the input bypass capacitors. The device itself has eight input voltage pins which can be powered from a single supply or from a number of individual supplies depending on how much copper is available on the input voltage feed track and how much real estate is available on the PCB for components. If all the supply inputs are fed from one single supply trace or from a power plane, a 10μF low ESR capacitor or two 4.7μF low ESR capacitors should be used. Larger input capacitance and lower ESR provide better supply noise rejection and line transient response. The copper trace to the inputs should be fairly thick in order to keep trace inductance to a minimum and the capacitors should be located as close to the SC905 as possible. If the supply trace is thin then the inputs should be treated as if they were powered from individual supplies, each input should be bypassed by at least one 1μF low ESR capacitor located very close to each input pin. The SC905 is designed to have excellent stability with a minimum output capacitance of 1μF. Low ESR ceramic capacitors are recommended and should be located as close to the LDO output pins as possible. © 2006 Semtech Corp. 12 www.semtech.com SC905 POWER MANAGEMENT Register Map Register Name VPAD Register Address 0 1 Default State VCORE VMOT 1 2 X VMOT_EN 1 ON VANA/VCAM VTCXO/VRX VPLL/VTX ON/OFF CONTROL 3 4 5 6 0 OFF Bit 7 DSB (1) Bit 6 X 0 Bit 5 X Bit 4 VPAD4 Bit 3 VPAD3 Bit 2 VPAD2 Bit 1 VPAD1 Bit 0 VPAD0 User State X VMOT Active SHDN 1 ON 0 OFF VANA0 VRX1 VTX1 VANA_EN 1 ON 0 OFF VCAM4 VRX0 VTX0 VCAM_EN 1 ON 0 OFF VCAM3 X X VTCXO_EN 1 ON 0 OFF VCAM2 VTCXO2 VPLL2 VPLL_EN 1 ON 0 OFF VCAM1 VTCXO1 VPLL1 VTX_EN 1 ON 0 OFF VCAM0 VTCXO0 VPLL0 VRX_EN 1 ON 0 OFF X X VCORE4 VMOT4 VCORE3 VMOT3 VCORE2 VMOT2 VCORE1 VMOT1 VCORE0 VMOT0 VANA2 X X VPAD_EN 1 ON 0 OFF VANA1 VRX2 VTX2 VCORE_EN 1 ON 0 OFF ACTIVE(2) SHUTDOWN 7 VPAD Active SHDN 1 ON 0 OFF X VCORE Active SHDN 1 ON X 0 OFF VANA Active SHDN 1 ON X 0 OFF VCAM Active SHDN 1 ON X 0 OFF VTCXO Active SHDN 1 ON OTF 1 OK 0 FAULT 0 OFF VPLL Active SHDN 1 ON 0 OFF VTX Active SHDN 1 ON 0 OFF VRX Active SHDN 1 ON CPB 0 OFF STATUS (READ ONLY) 8 FAULTB 1 OK 0 FAULT CHRGB 1 OFF 0 ON 1 OFF 0 ON Defaults are indicated in BOLD. SC905 Slave Address: DEVICE ADDRESS 0 0 0 1 0 0 0 R/W X Notes: (1) The default status bit (DSB) is set to 1 only when the SC905 is enabled by either the HFPWR pin or the ON pin being pulled high, and it cannot be set to one through the I2C interface. When changing the VPAD control voltage, always write to register 0 with bit seven high. Set bit seven low only when the DSB is to be cleared by the MSM. This will prevent any software race condition in a multi-tasking environment. See the applications section for more information on using the DSB. (2) The Active Shutdown defaults ON at power-up, but the registers maintain their settings as the LDOs are enabled and disabled during normal operation. © 2006 Semtech Corp. 13 www.semtech.com SC905 POWER MANAGEMENT Register Map (Cont.) Digital LDO Voltage Table A A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages. TABLE A - Output Voltage Code Bits for VCORE, VPAD, VMOT and VCAM X4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LDO Output Voltage 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.10V 2.15V 2.20V 2.25V 2.30V 2.35V 2.40V 2.45V 2.50V 2.55V 2.60V 2.65V 2.70V 2.75V 2.80V 2.85V 2.90V © 2006 Semtech Corp. 14 www.semtech.com SC905 POWER MANAGEMENT Register Map (Cont.) Analog LDO Voltage Table B The bit code controls the output voltage of each LDO. The LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table B for the bitcodes and their corresponding voltages. TABLE B - Output Voltage Code Bits for LDOs VANA, VTCXO, VTX, VRX, VPLL X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 LDO Output Voltage 2.55V 2.60V 2.65V 2.70V 2.75V 2.80V 2.85V 2.90V The I2C General Specification The SC905 is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January, 2000. The SC905 has eight user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC905 enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SC905 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC905 Limitations to the I2C specifications: Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SC905. The SC905 is not CBUS compatible. The SC905 can operate in standard mode (100kbit/s) or fast mode (400kbit/s). Supported Formats: Direct Format - Write The simplest format for an I2C write is given below. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. © 2006 Semtech Corp. 15 www.semtech.com SC905 POWER MANAGEMENT Using the I2C Serial Port I2C Direct Format - Write S Slave Address W A Register Address A Data AP S: Start Condition W: Write = ‘0’ A: Acknowledge (sent by slave) P: Stop condition Slave Address: 7 bit Register Address: 8 bit Data: 8 bit Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. I2C Combined Format - Read S Slave Address W A Register Address A Sr Slave Address R A Data NACK P S: Start Condition W: Write = ‘0’ R: Read = ‘1’ A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition Slave Address: 7 bit Register Address: 8 bit Data: 8 bit Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC905 then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC905 with a read command. The SC905 acknowledges this request and returns the data from the register location that had previously been set up. I2C Stop Separated Format - Read Register Address Setup Access Master Addresses other Slaves Register Read Access S/Sr Slave Address A R A Data NACK P S Slave Address W A Register Address A P S Slave Address B S: Start Condition W: Write = ‘0’ R: Read = ‘1’ A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition Slave Address: 7 bit Register Address: 8 bit Data: 8 bit © 2006 Semtech Corp. 16 www.semtech.com SC905 POWER MANAGEMENT Timing Diagram Power On-Off Timing Diagram ON or HFPWR MSM DETERMINED DSB BP 25ms 25ms 77% 100μs 77% 100μs 77% VCORE VPAD 100μs 100μs VANA 100μs 100μs VTCXO 100ms 100ms RESB PGOOD MSM DETERMINED MSM DETERMINED PWRON © 2006 Semtech Corp. 17 www.semtech.com SC905 POWER MANAGEMENT Typical Characteristics Dropout Voltage vs. Load Current (Analog LDOs) 200 175 225 200 Dropout Voltage vs. Load Current (Digital LDOs) Dropout Voltage (mV) T = 85˚C T = 85˚C Dropout Voltage (mV) 150 125 100 75 T = 25˚C 175 150 125 100 75 T = 25˚C 50 25 0 80 100 120 140 160 180 200 T = -40˚C 50 25 0 100 T = -40˚C 125 150 175 200 225 250 275 300 Load Current (mA) Load Current (mA) Load Regulation (Analog LDOs) VIN = 3.7V 0 0 Load Regulation (Digital LDOs) VIN = 3.7V Output Voltage Variation (mV) T = 85˚C Ouptut Voltage Variation (mV) T = 85˚C -3 -3 -6 -6 -9 T = -40˚C -9 -12 T = -40˚C -15 T = 25˚C -12 T = 25˚C -18 0 25 50 75 100 125 150 175 200 -15 0 50 100 150 200 250 300 Load Current (mA) Load Current (mA) Line Regulation (Analog LDOs) Load Current = 1mA 5 Line Regulation (Digital LDOs) Load Current = 1mA 6 Output Voltage Variation (mV) Output Voltage Variation (mV) 4 T = 85˚C 5 T = 85˚C 4 T = 25˚C 3 T = 25˚C 3 2 2 1 T = -40˚C 1 T = -40˚C 0 3 3.5 4 4.5 5 5.5 0 3 3.5 4 4.5 5 5.5 Input Voltage (V) © 2006 Semtech Corp. 18 Input Voltage (V) www.semtech.com SC905 POWER MANAGEMENT Typical Characteristics (Cont.) PSRR vs. Frequency (Analog LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA 0 PSRR vs. Frequency (Digital LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA 0 Power Supply Rejection (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000 10000 Power Supply Rejection (dB) -10 -20 -30 -40 -50 -60 -70 -80 10 100 1000 10000 Frequency (Hz) Frequency (Hz) Safe Operating Limits 1.6 Output Noise vs. Load Current (Analog LDOs) VOUT = 2.90V, VIN = 3.7V 45 40 35 30 25 20 T = 85˚C T = -40˚C T = 25˚C Maximum Output Current (A) 1.4 1 0.8 0.6 0.4 0.2 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VOUT = 1.35V VOUT = 2.90V Maximum Recommended Input Voltage Output Noise (μV) 5.9 1.2 15 10 5 0 5.5 0 25 50 75 100 125 150 175 200 Input Voltage (V) Load Current (mA) © 2006 Semtech Corp. 19 www.semtech.com SC905 POWER MANAGEMENT Outline Drawing - MLPQ-32 5x5 Marking Information Top Marking yyww = Date Code (Example: 0552) xxxxx = Semtech Lot Number (Example: E90101-100) © 2006 Semtech Corp. 20 www.semtech.com SC905 POWER MANAGEMENT Land Pattern - MLPQ-32 5x5 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804 © 2006 Semtech Corp. 21 www.semtech.com