SC908MLTRT

SC908 Power Management IC for Single-Cell Li-Ion Devices POWER MANAGEMENT Features Single Cell Li-Ion battery charger — CC/CV charging with current soft start Charger regulated output voltage — 4.2V ±1% over temperature with Kelvin sense of battery voltage Charger input protection withstands 28V indefinitely Charger max constant current setting — 500mA Adjustable charge termination current down to 10mA Battery NTC interface disables charging if battery temperature out of range Programmable low battery detector threshold Four status indicators Programmable charge completion timer Buck converter with enable — output programmable from 1V to 3V, 150mA max output Buck converter efficiency — 88% at 50mA General purpose low noise LDO regulator with fast enable, active shutdown 4x4x0.9 (mm) MLPQ package WEEE and RoHS compliant Description The SC908 is a complete power management system designed for use in Bluetooth wireless headsets, portable media players, and other battery-powered electronics where size is critical. Included are a full featured standalone Li-Ion battery charger with a programmable low-battery monitor, a low noise LDO regulator, and a DCDC buck converter. Battery charging features include programmable precharge, fast-charge, and termination current settings. Charge termination is controlled by a programmable timer and by a resistor that sets the termination current. The 28V max input voltage protects against hotplug overshoot and faulty adapters without additional protection circuitry. The battery voltage Kelvin sense input eliminates errors due to high charging currents. A battery thermistor interface disables charging when the battery temperature exceeds safe-to-charge limits. The step-down switching regulator (buck converter) improves system efficiency and extends battery life. The LDO regulator can be powered directly from the battery or from the buck converter output when efficiency is critical. The fast-starting low noise LDO regulator is suitable for audio, RF, or general purpose regulation required by peripheral devices, such as a vibrating alert motor. The low battery detector warns when the battery level is below 3.3V, and when the battery has discharged below a lower programmable voltage limit. Applications Bluetooth headsets MP3 players Low cost mobile phones Typical Application Circuit Charging Adapter CVAD CVSYS RNPU Charging RNTC (Battery Pack NTC Thermistor) VAD VSYS BAT BSEN RTIME RRTIME RITERM CBAT Li-Ion BATTERY ITERM RIPRGM IPRGM EN_NTC SC908 CHRGB CPB FLTB LBATB RLBAT VREF AGND DGND LEN LVIN Can supply LDO from battery or from DC-DC converter CLVIN To Audio Circuits or vibrator motor RL1 Charger Present LVOUT LFB SEN SLX CSFB LS SVOUT, To Bluetooth Processor CLVOUT RS1 CSVOUT RL2 RRLBAT CVREF SFB PGND CSFG RS2 US Patent: 6,836,095 January 24, 2008 © 2008 Semtech Corporation 1 SC908 Pin Configuration EN_NTC CHRGB PGND Ordering Information Device Package MLPQ-24 Evaluation Board BSEN BAT SLX SC908MLTRT(1,2) SC908EVB 24 VAD VSYS IPRGM ITERM RTIME RLBAT 1 2 3 4 5 6 7 23 22 21 20 19 18 17 16 15 14 13 SEN CPB LBATB FLTB SFB LEN Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free package only. Device is WEEE and RoHS compliant. TOP VIEW T 8 9 10 11 12 LVOUT LFB VREF AGND LVIN MLP-24; 4x4, 24 LEAD θJA = 29°C/W Marking Information SC908 yyww xxxxx xxxxx yy = year of manufacture ww = week of manufacture xxxx = lot number DGND 2 SC908 Absolute Maximum Ratings(1) VAD (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +28.0 BAT, VSYS, CHRGB, FLTB, LBATB (V) . . . . . . . . . . -0.3 to +5.5 CPB (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V (2) SRC Recommended Operating Conditions Ambient Temperature Range (°C) . . . . . . . . . . . . . -40 to +85 Charger Input Voltage Range (V) . . . . . . . . . . . . 4.45 to 7.05 LDO Regulator Input Voltage Range (V) . . . . . . . . 2.2 to VBAT Switching Regulator Input Voltage (V) . . . . . . . . . . . . . . . VBAT + 0.3 SLX, LVIN, LEN, SEN (V) . . . . . . . . . . . . . . . . . . . . . . . VBAT + 0.3 LVOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLVIN + 0.3 AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +0.3 Pin Voltage — All Other Pins (V) . . . . . . . . . . . . -0.3 to +6.5 BAT Output Current (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 BAT Short Circuit Duration (s) . . . . . . . . . . . . . . . .Continuous DC-DC Converter Output Current (mA)(3) . . . . . . -265, +180 DC-DC Converter Output Current (mA)(4) . . . . . . . . . . . ±600 Total Power Dissipation (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ESD Protection Level (kV) (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal Information Thermal Resistance, Junction to Ambient (°C/W)(6) . . . . . 29 Junction Temperature Range (°C) . . . . . . . . . . . . .-40 to +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) All absolute maximum ratings are with respect to DGND unless otherwise noted. (2) VSRC = larger of VBAT and VVSYS (3) Continuous (4) Peak (5) Tested according to JEDEC standard JESD22-A114-B. (6) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Test Conditions: VVAD = 4.75V to 5.25 V; VBAT = 3.7V; VLEN = VVAD; Typ values at 25°C; Min and Max at -40°C < TA < 85°C, unless specified. Parameter Charger Symbol Conditions Min Typ Max Units VADOP(1) VADUVLO-R VADUVLO-F VAD Input Voltage VADUVLO-H VADOVP-R VADOVP-F VADOVP-H Battery Leakage Current (2) lleakBAT Operating Voltage UVLO Rising Threshold UVLO Falling Threshold UVLO Hysteresis (VADUVLO-R - VADUVLO-F) OVP Rising Threshold OVP Falling Threshold OVP Hysteresis (VADOVP-R - VADOVP-F) VVAD=VSEN=VLEN=0V, VBAT=4.2V 4.45 4.05 3.8 150 5 4.25 4 7.05 4.45 4.2 V V V mV 7.5 7.05 50 0.1 7.3 7.80 V V mV 2 μA 3 SC908 Electrical Characteristics (continued) Parameter Charger (continued) Charging Adapter Operating Current VADICCQ VEN_NTC = 0.5 × VVSYS, ICPB = ICHRGB = IFLTB = ILBATB = IITERM = IIPRGM = 0mA, VSEN = VLEN = 0V Measured at BSEN pin 20mA < IBAT < 500mA 0°C < TJ < 125°C Measured at BSEN pin VCV - VBSEN VVAD ≥ 5V, IVSYS ≤ 5mA 4.16 1.5 mA Symbol Conditions Min Typ Max Units CV Regulation Voltage VCV 4.2 4.24 V Precharge Threshold (Rising) Recharge Threshold (Falling) VSYS output voltage (3) VSYS output current ITERM Programming Resistor IBAT Pre-Charge Current IBAT Termination Current IPRGM Programming Resistor IBAT Fast-Charge Current VAD - BAT Dropout Voltage IPRGM Regulated Voltage ITERM Regulated Voltage RTIME Regulated Voltage VTPreQ VTReQ VVSYS IVSYS RITERM IPreQ ITERM RIPRGM IFQ VDO VIPRGM VITERM VRTIME tPreQF 2.7 65 2.8 113 4.7 2.9 160 V mV V 5 Nominal 1%-tol Standard Value RITERM = 4.99kΩ to GND RITERM = 4.99kΩ to GND Nominal 1%-tol Standard Value RIPRGM = 6.04kΩ, VBAT = 3.7V IBAT = 500mA, 0°C ≤ TJ ≤ 85°C RIPRGM = 6.04kΩ to GND RITERM = 4.99kΩ to GND RRTIME = 37.4kΩ to GND RRTIME = 37.4kΩ to GND 1.45 1.45 1.475 38 32 2.50 2.10 9 27.5 74 1.5 1.5 1.56 47 42 3.10 2.67 10 30 75 45 500 2.67 27 27 2.15 167 173 39 39 17.4 52 52 15.0 179 0.8 1.55 1.55 1.625 57 53 3.70 3.50 11.5 31.5 76.5 mA kΩ mA mA kΩ mA V V V V mins mins hrs hrs %VVSYS %VVSYS %VVSYS mV ns Precharge Fault Time-Out RRTIME connected to VSYS RRTIME = 37.4kΩ to GND Charge Complete Time-Out tQComp RRTIME connected to VSYS VTNTC_DIS EN_NTC Thresholds VTNTC_HF VTNTC_CR EN_NTC Hysteresis EN_NTC Disable/Reset Hold Time Charger Over-Temperature Shutdown Temperature (Rising) VTNTC_HYS tNTC_DIS_H TCHRGR_OT Charger Disable/Reset (Falling) NTC Hot (Falling) NTC Cold (Rising) VVAD = 5V Momentary disable resets charger Hysteresis = 10°C typical 145 °C 4 SC908 Electrical Characteristics (continued) Parameter Core Functions (Excluding Charger) Core Circuits Quiescent Current (4) VREF Reference Voltage VREF Power Supply Rejection IQ-Core VVREF PSRRREF VBAT = 3.7V with 0.5VP-to-P ripple, f ≤ 10kHz, CVREF = 10nF Delay from first of SEN high LEN high, VBAT = 3.7V CVREF = 10nF VREF from 0V to 95% of final VVAD = VSEN = 0V, VLEN = VBAT = 4.2V 100 0.75 70 μA V dB Symbol Conditions Min Typ Max Units VREF Reference Voltage Start-Up Time (5, 10) tSU_REF 0.4 ms DC-DC Buck Converter Buck Converter Input Voltage Buck Converter Under-Voltage Lockout Rising Threshold Buck Converter Under-Voltage Lockout Falling Threshold Buck Converter Under-Voltage Lockout Hysteresis Buck Converter Quiescent Current (2) Buck Converter Minimum On-Time Buck Converter Maximum Duty Cycle (10) Buck Converter Program Output Voltage Minimum (6,10) Buck Converter Program Output Voltage Maximum(6,7,8,10) Buck Converter Feedback Regulation Voltage VSVIN VTSUVLO-R VTSUVLO-F VTSUVLO-HYS IBAT-Q tSON_MIN SDCMAX VSVOUT_MIN VSVOUT_MAX VSFB VBAT = 3.7V, L = 4.7μH ISVOUT = 100mA RS1 = 340kΩ, RS2 = 100kΩ Buck Converter Line Regulation(6) VSVOUT_LINE 2.8V ≤ VBAT ≤ 4.5V ISVOUT = 100mA RS1 = 340kΩ, RS2 = 100kΩ 5mA ≤ ISVOUT ≤ 150mA VSVOUT_LOAD VBAT = 3.7V RS1 = 340kΩ, RS2 = 100kΩ 0.002 %/mA -0.3 0.3 %/V VBAT ≥ VSVOUT_MAX/SDCMAX+150mV 3 92 VSEN = VBAT, ISVOUT = 10mA Low IQ mode of PSAVE 2.55 BAT pin is also the switching regulator supply input VBAT 2.8 V V V 84 mV 115 μA 60 ns % 1 V V 0.480 0.500 0.520 V Buck Converter Output Voltage(6) VSVOUT 2.2 V Buck Converter Load Regulation (6) 5 SC908 Electrical Characteristics (continued) Parameter DC-DC Buck Converter (continued) Buck Converter P-Channel Peak Current Limit Buck Converter P-Channel On-Resistance Buck Converter N-channel On-Resistance Buck Converter Oscillator Frequency ILIM_P RDS(ON)P RDS(ON)N fOSC ISVOUT = 150mA, VSVOUT to 95% VSVOUT = 1V VSVOUT = 1.8V VSVOUT = 2.2V VSVOUT = 3.0V ISVOUT = 150mA ISVOUT = 150mA 0.85 410 440 470 mA Symbol Conditions Min Typ Max Units 0.75 Ω 1.05 Ω 1.00 1.15 MHz Buck Converter Start-Up Time (5,10) tSU-SVOUT 0.3 1.3 1.45 1.8 ms 2 Linear Low Drop-Out (LDO) Regulator LDO Input Voltage LDO Under Voltage Lockout Rising Threshold LDO Under Voltage Lockout Falling Threshold LDO Under Voltage Lockout Hysteresis LDO Nominal Output Voltage Minimum (10) LDO Nominal Output Voltage Maximum (10) LDO Feedback Regulation Voltage LDO Output Voltage VLVIN VTLUVLO-R VTLUVLO-F VTLUVLO-HYS VLVOUT_MIN VLOUT_MAX VLFB VLVOUT VLVIN > VLVOUT +300mV VLVIN > VLVOUT +300mV VLVIN = 3.7V, ILVOUT = 1mA RL1 = 54.9kΩ, RL2 = 39.2kΩ VLVIN = 3.7V, ILVOUT = 1mA VLVOUT = 2.2V, ILVOUT = 100mA LDO Dropout Voltage VL_DO VLVOUT = 3.0V, ILVOUT = 150mA RL1 = 54.9kΩ, RL2 = 39.2kΩ LDO Load Regulation (with respect to 1mA load) (9) (VLVOUT = 1.8V), VLVIN = 2.2V 1mA ≤ ILVOUT ≤ 100mA RL1 = 54.9kΩ, RL2 = 39.2kΩ (VLVOUT = 1.8V), VLVIN = 3.7V 1mA ≤ ILVOUT ≤150mA -10 10 mV -10 10 mV 130 225 mV 1.73 3.3 1.75 VBAT ≥ 2.8V 2.2 1.95 VBAT 2.05 V V 1.85 V 120 mV 1.5 V V 0.75 V 1.8 115 1.85 200 V mV ΔVLVOUT_LOAD 6 SC908 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Linear Low Drop-Out (LDO) Regulator (continued) LDO Line Regulation (9) ΔVLVOUT_LINE 2.2V ≤ VLVIN ≤ 4.2V referenced to 3.7V, ILVOUT = 1mA, RL1 = 54.9kΩ, RL2 = 39.2kΩ VLVIN = 3.7VDC with 0.5V P-to-P Ripple, PSRRLLVIN f ≤ 10kHz, VBAT = 3.7VDC VLVOUT = 1.8V, ILVOUT = 30mA VLVIN = VBAT = 3.7VDC with 0.5V P-to-P PSRRLBAT Ripple, f ≤ 10kHz VLVOUT = 1.8V, ILVOUT = 30mA 10Hz ≤ f ≤ 100kHz LDO Output Noise Voltage (9) -5 5 mV LDO LVOUT/LVIN Power Supply Rejection Ratio 60 dB LDO LVOUT/(BAT and LVIN) Power Supply Rejection Ratio 60 dB VL_NOISE CLVOUT = 1μF, VLVOUT = 3.0V VLVIN = 3.7V, ILVOUT = 50mA VLVIN = VLEN = VBAT = 4.2V, VVAD = 0V, ILVOUT = 1mA VLVOUT = 0V, VLEN = VBAT Time from LEN (with VSEN = VBAT, disregard tSU_REF), VLVOUT from 0V to 95% of final Time from LEN (with VVAD = VSEN = 0, tSU_REF dominates) VLVOUT from 0V to 95% of final Time from LEN = 0, VLVOUT from 100% to 10% of regulation 300 50 μVRMS LDO Quiescent Current (ILVIN - ILVOUT ) (4) LDO Current Limit ILQ IL_LIM 91 380 450 μA mA 0.1 ms LDO Start-Up Time (5, 10) tSU-LVOUT 0 ms LDO Turn-Off Time Battery Voltage Detector Battery Detector Minimum Operating Voltage Battery Detector Maximum Operating Voltage Battery Detector Voltage Warning, Decreasing Battery Detector Voltage Fault, Decreasing Battery Detector Threshold Hysteresis, Warning or Fault tTO-LVOUT 0.5 ms VDET_MINOP VDET_MAXOP VWARN VDET VDET_HYS VDET_MINOP ≤ VBattery ≤ VDET_MAXOP RRLBAT = 309kΩ VDET_MINOP ≤ VBattery ≤ VDET_MAXOP 150 4.5 2.3 V V 3.21 3.28 3.35 V 2.92 V 200 250 mV 7 SC908 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Logic Control Inputs & Status Outputs Battery Detector Sense Leakage (BSEN Current) Battery Detector Activation Delay(10) Logic Input Low Logic Input High Logic Input Current High Logic Input Current Low CPB, CHRGB, FLTB, LBATB Outputs IBSEN_DET VDET_DEL VIL VIH IIL IIH VOL IOH VVAD > VADUVLO, or SEN or LEN high, VBSEN = 4.2V Time from first of LEN or SEN high until LBATB/FAULTB valid, VVAD = 0V LEN, SEN; VBAT = 2.7V LEN, SEN; VBAT = 2.7V LEN, SEN; VBAT = 2.7V LEN, SEN; VBAT = 2.7V ISINK = 2mA V = 5V (VVAD = 8V for CPB) 0.4 1.5 1 1.5 0.5 1 5 10 μA 70 μs V V μA μA V μA Notes: (1) VADOP is the “Maximum Vsupply” as defined in EIA/JEDEC Standard No. 78, paragraph 2.11. (2) The value of the buck converter disabled battery leakage current is included in the charger section battery leakage since it cannot be independently measured (because SVIN is tied to BAT internally). The buck converter contribution to this value is also included in the Buck Converter section for design guidance only. (3) VSYS regulation voltage assumes that VVAD exceeds VVSYS by the VSYS regulator dropout (typically 0.5V at 5mA, for a minimum regulator RDS = 71Ω). If this condition is not met, then VVSYS = VVAD minus the VSYS regulator dropout. (4) IQ-Core is the supply current from the battery for common reference circuits into the BAT pin when either the buck converter or LDO or charger are enabled. (5) tSU_REF is the start-up time of the voltage reference buffer for both the DC-DC buck converter and the LDO, and should be added to the start-up time (tSU-SVOUT or tSU-LVOUT respectively) of the first regulator enabled. In the case of the LDO start-up with the switcher disabled, the LDO start-up time tSU-LVOUT is concurrent with the reference start-up time tSU_REF, and so tSU-LVOUT is specified as typically zero. (6) SVOUT is the buck converter output node, which is the node at which the output inductor is connected to the load. It is the top of the feedback resistor divider network. See the Typical Application Circuit. (7) To guarantee positive load threshold hysteresis for PSAVE-to-PWM mode switching with SVOUT > 2.2V, contact your Semtech representative for application assistance. (8) If VBAT < VSVOUT_Max / SDCMAX + 150mV, then the maximum output setting is VBAT x SDCMAX + 150mV. Higher output voltage settings are feasible, but are subject to load-dependent dropout. (9) Specified with VBAT = VLVIN. (10) Guaranteed by design. 8 SC908 Typical Characteristics Charger CV Line Regulation TA = 25 C, IBAT = 50mA 4.19 4.189 4.188 4.187 4.19 4.189 4.188 4.187 ο ο Charger CV Load Regulation TA = 25 C, VVAD = 5V VBAT (V) 4.185 4.184 4.183 4.182 4.181 4.18 4.5 5 5.5 6 6.5 7 VBAT (V) 4.186 4.186 4.185 4.184 4.183 4.182 4.181 4.18 0 50 100 150 200 250 300 350 400 450 500 VVAD (V) IBAT (mA) Charger CV Temperature Regulation VVAD = 5V, IBAT = 50mA 4.186 4.184 182 4.182 4.18 4.178 4.176 4.174 175 4.172 -40 -20 0 20 40 60 80 o Charger CC Line Regulation VBAT = 3.75V, RIPRGM = 6.04kΩ 184 183 181 0C ο IBAT (mA) VBAT (V) 180 179 178 177 176 ο ο 85 C -40 C TA = 25 C ο 100 120 140 174 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 Junction Temperature ( C) VVAD (V) Charger CC VBAT Regulation VVAD = 5V, RIPRGM = 6.04kΩ 179 178.75 178.5 178.25 178 0C ο Charger CC IFQ Programming TA = -40, 0, 25, 85 C, VVAD = 5V, VBAT = 3.75V 500 450 ο 85 C ο 400 ο 350 IBAT (mA) IBAT (mA) 4 4.1 177.75 177.5 177.25 177 176.75 176.5 176.25 176 3.5 3.6 3.7 3.8 TA = 25 C ο 300 250 200 150 100 50 2 -40 C 3.9 4 6 VBAT (V) RIPRGM (kΩ ) 8 10 12 14 16 9 SC908 Typical Characteristics (continued) PreQ VBAT = 2.6V, RITERM = 4.99kΩ 41.5 -40 C 41 60 40.5 0C ο ο Charger I Line Regulation 70 Charger IPreQ Programming VVAD = 5V, VBAT = 2.6V 50 IBAT (mA) 40 39.5 39 85 C 38.5 38 4.5 ο IBAT (mA) 40 30 20 ο TA = 25 C ο -40 C TA = 85 C 25 C ο ο 10 0 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 2 4 6 8 VVAD (V) RITERM (kΩ ) 10 12 14 16 18 20 Charging Cycle Battery Voltage and Current ο 700mAhr battery, RIPRGM = 2.15kΩ , RITERM = 3.48kΩ , VVAD = 5.0V, TA = 25 C 550 5.5 Pre-Charging Battery Voltage and Current 700mAhr battery, RIPRGM = 2.15kΩ , RITERM = 3.48kΩ , VVAD = 5.0V, TA = 25 C 550 5.5 ο VBAT (V), Internal Power Dissipation (W) VBAT (V), Internal Power Dissipation (W) 5 4.5 4 3.5 3 2.5 2 1.5 1 PWR 0.5 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 IBAT VBAT 500 450 400 350 5 4.5 4 3.5 3 2.5 2 1.5 PWR 1 0.5 0 0 2 4 6 8 10 12 14 16 18 VBAT IBAT 500 450 400 350 300 250 200 150 100 50 0 20 300 250 200 150 100 50 0 2.5 IBAT (mA) Time (hrs) Time (s) CC-to-CV Battery Voltage and Current 700mAhr battery, RIPRGM = 2.15kΩ , RITERM = 3.48kΩ , VVAD = 5.0V, TA = 25 C 510 5.1 5 4.9 4.8 500 490 480 IBAT ο Re-Charge Cycle Battery Voltage and Current 4.5 700mAhr battery, RITERM = 3.48kΩ , VVAD = 5.0V, TA = 25 C, Load = 10mA ο 450 400 350 300 250 200 150 VBAT (V), Internal Power Dissipation (W) 4 3.5 3 2.5 2 1.5 1 0.5 PWR 0 0.0 0.5 IBAT VBAT IBAT (mA) 4.6 4.5 4.4 4.3 VBAT 4.2 4.1 56 56.5 57 57.5 58 58.5 59 59.5 460 450 440 430 420 410 60 100 50 0 4.0 1.0 1.5 2.0 2.5 3.0 3.5 Time (min) Time (hrs) 10 IBAT (mA) VBAT (V) 4.7 470 IBAT (mA) SC908 LDO Line Regulation RL1 = 54.9kΩ , RL2 = 39.2kΩ , TA = 25 C 1.799 ILVOUT = 10mA 1.798 ILVOUT = 100mA 1.799 ο LDO Load Regulation RL1 = 54.9kΩ , RL2 = 39.2kΩ , TA = 25 C, VLVIN = 3.75V ο ILVOUT = 50mA 1.7985 VLVOUT (V) VLVOUT (V) 1.797 ILVOUT = 150mA 1.796 1.798 1.7975 1.795 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 1.797 0 20 40 60 80 100 120 140 VLVIN (V) ILVOUT (mA) LDO Temperature Regulation RL1 = 54.9kΩ , RL2 = 39.2kΩ , VLVIN = 3.75V 1.8 ILVOUT = 10mA 1.795 ILVOUT = 100mA 1.79 ILVOUT = 50mA -50 -55 -60 -65 -70 -75 1.775 -80 1.77 -40 -85 10 -45 ο LDO PSRR, LVIN to LVOUT TA = 25 C, VLVOUT = 1.8V, VLVIN = 3.7VDC + 0.5VAC, VBAT = 3.7V ILVOUT = 150mA 1.785 1.78 LDO PSRR LLVIN (dB) VLVOUT (V) -20 0 20 40 60 o 80 100 120 100 1000 10000 Junction Temperature ( C) Frequency (Hz) LDO PSRR, BAT to LVOUT TA = 25 C, VLVOUT = 1.8V, VLVIN = 3.7VDC, VBAT = 3.7VDC + 0.5VAC -45 -50 -55 -60 -65 -70 -75 -80 -85 10 -45 -50 -55 -60 -65 -70 -75 -80 -85 10 ο LDO PSRR, LVIN and BAT to LVOUT TA = 25 C, VLVOUT = 1.8V, VLVIN = VBAT = 3.7VDC + 0.5VAC ο 100 1000 10000 LDO PSRR LBAT (dB) LDO PSRR BAT (dB) 100 1000 10000 Frequency (Hz) Frequency (Hz) 11 SC908 Typical Characteristics (continued) DC/DC Converter Line Regulation VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), TA = 25 C 2.23 ISVOUT = 35mA 2.22 ISVOUT = 10mA PSAVE Mode 2.22 2.25 2.24 2.23 ο DC/DC Converter Load Regulation VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), TA = 25 C, VBAT = 3.7V ο VSVOUT (V) VSVOUT (V) 2.21 2.21 Decreasing Load 2.2 2.19 2.18 2.17 Increasing Load 2.2 ISVOUT = 100mA 2.19 ISVOUT = 150mA 2.18 PWM Mode 2.16 3.6 3.8 4 4.2 2.15 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 3 3.2 3.4 VBAT (V) ISVOUT (mA) DC/DC Converter Temperature Regulation VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), VBAT = 3.7V 2.23 ISVOUT = 35mA 2.22 ISVOUT = 10mA PSAVE Mode 70 100 90 80 DC/DC Converter Efficiency VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), VBAT = 3.6V, L = 4.7 μH PSAVE Mode PWM Mode Efficiency (%) ISVOUT = 100mA PWM Mode ISVOUT = 150mA VSVOUT (V) 2.21 60 50 40 30 20 10 2.2 2.19 2.18 -40 -20 0 20 40 60 o 80 100 120 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Junction Temperature ( C) ISVOUT (mA) DC/DC Converter Efficiency Detail VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), VBAT = 3.6V, L = 4.7 μH 93 92 91 PSAVE Mode PSAVE Mode PWM Mode 100 90 80 70 DC/DC Converter Efficiency — Low Loads VSVOUT = 2.2V (RS1 = 340kΩ , RS2 = 100kΩ ), VBAT = 3.6V, L = 4.7 μH Efficiency (%) 90 89 88 87 PWM Mode Efficiency (%) 60 50 40 30 20 86 85 0 10 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 1 10 100 ISVOUT (mA) ISVOUT (mA) 12 SC908 Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name VAD VSYS IPRGM ITERM RTIME RLBAT LVIN LVOUT LFB VREF AGND DGND LEN SFB FLTB LBATB CPB SEN Pin Function Charger input pin Adapter input internal-regulation node which also serves as supply for EN_NTC, RTIME, and all input-referenced (vs. battery-referenced or regulated output-referenced) pull-ups; load must not exceed 5mA. Pin for setting constant current charging current — connect resistor to ground to set current. Pin for setting termination and precharge current — connect resistor to ground to set current. Charge timer pin — connect a resistor to ground to set timer, ground to disable the timer. Timer enabled with internally programmed default time is selected with RTIME tied to VSYS. Resistor is connected to ground to set Low Battery voltage threshold. LDO voltage input — can be connected to either the battery supply (BAT) or the switching regulator output (SVOUT). No other connections are permitted. LDO voltage output LDO feedback voltage input Bandgap reference bypass pin — connected to a 10nF capacitor to analog ground. No other connections are permitted. Analog ground pin — refer to grounding considerations in application section. Digital ground pin — refer to grounding considerations in application section. LDO enable pin — active high DC-DC converter feedback input — connect voltage divider from output to this pin to set output voltage. Charging Fault indicator — open drain output is active low when a charging fault has occurred. Also, together with LBATB, indicates when battery discharges below a programmable voltage set by RLBAT resistor. Low Battery indicator — open drain output is active low when battery discharges below 3.3V, and, together with LBATB, indicates when battery discharges below a programmable voltage set by RLBAT resistor. Charger Present indicator — open drain output is active low when a valid VAD input voltage is present. DC-DC converter enable pin — active high Charging-In-Progress indicator — open drain output is active low when charging until charging current drops below the programmed termination current, or until charging is disabled by charge timeout or EN_NTC disable or NTC temperature fault. DC-DC converter power ground pin — No other connection is permitted. DC-DC converter output — connect to an inductor between this point and SVOUT (the DC-DC converter load connection). Charger output pin, also DC-DC converter input pin — connect to the positive battery terminal. NTC thermistor input — charger is enabled if voltage is between 0.3 × VSYS and 0.75 × VSYS. Charger is disabled if voltage is below 1V. Battery temperature fault otherwise. Battery Kelvin sense pin — independent connection is tied directly to the battery positive terminal. Connect to ground plane with thermal vias directly under pad. 19 CHRGB 20 21 22 23 24 T PGND SLX BAT EN_NTC BSEN Thermal Pad 13 SC908 Block Diagram With Typical Application Circuit Charging Adapter 2 VSYS VSYS Regulation VSYS 4.2V Reference Voltages VREF Qterm Qpass VAD 1 CVSYS CVAD 10 VREF BSEN 24 Fast Charge Ref Pre-Charge Ref CVREF VTH-cold (0.75VCC) VTH-hot (0.3VCC) RNPU 23 EN_NTC NTC Interface Control Pre-Charge On Fast Charge On Over Temp Under Voltage Over Voltage BAT 22 Pre-Charge Ref CVOUT RNTC RRTIME 5 ITERM RTIME Timer Fast Charge Ref CPB CHRGB VREF LVIN LDO IPRGM 4 RITERM 3 RIPRGM 17 CLVIN 7 19 15 16 FLTB LBATB LVOUT 8 LDO Supply from battery or SVOUT LFB 9 RL1 CLVOUT AGND RRLBAT 6 RL2 11 RLBAT SVIN 13 18 LEN SEN Buck Converter Control Block SLX 21 PGND DGND SFB 14 20 LS 12 RS2 CSFG RS1 CSFB SVOUT CSVOUT 14 SC908 Applications Information Charger Operation The SC908 Li-Ion battery charger can be configured independently with respect to fast-charge, termination current, and timing. The charging and battery voltage status are indicated by the four status outputs. A charge cycle is initiated when the power adapter is connected to the device and the SC908 VAD pin voltage is between the Under-Voltage LockOut (UVLO) rising threshold and the input Over Voltage Protection (OVP) threshold. If the battery voltage is less than the pre-charge threshold, the output current is regulated to the programmed precharge current. When the pre-charge threshold voltage is exceeded, the fast-charge Constant Current (CC) mode begins, with the charge current rising to the programmed fast-charge current in three soft-start current steps. The charger enters the Constant Voltage (CV) mode when the battery voltage rises to its final value (VCV ), typically 4.2V. In the CV mode the BAT voltage is regulated to VCV, and as the battery continues to charge it accepts decreasing current. The CHRGB output turns off when IBAT drops below the programmed termination current. If the charge timer is active, the battery is held in the CV charge mode until the timer cycle ends. The charger then enters the monitor mode, where the output remains off until the voltage at BAT drops by VTReQ, and a new charge cycle is initiated. If the charge timer is disabled, the monitor mode is immediately entered upon charge termination. when VAD is cycled off and on, or when the EN_NTC pin is forced low to disable the charger. Fast-Charge Constant Current Mode The fast-charge CC mode is active when the battery voltage is above VTPreQ and less than VCV. The current can be set to a maximum of 0.5A and is selected by the program resistor on the IPRGM pin. The voltage on this pin represents the charger output current. This allows the charging current to be measured by sensing the IPRGM pin voltage using a general purpose Analog-toDigital Converter (ADC) and the host microporocessor. The fast-charge current is determined by VIPRGM _ Typ RIPRGM IFQ 697 Excellent fast-charge current accuracy is obtained by the use of a patented polarity-switched current sense amplifier (US Patent 6,836,095). This nullifies current measurement offset errors, leaving only a small gain error. The range of expected fast-charge output current versus programming resistance RIPRGM is shown in Figures 1a and 1b. 520 500 480 460 440 Fast Charge Current (mA) Pre-Charge Mode The pre-charge mode is automatically entered when the battery voltage is below the pre-charge threshold voltage, which preconditions the battery for fast charging. The pre-charge current value is set by the resistor on the ITERM pin, and is programmable from 14mA to 65mA. The precharge current is determined by VITERM _ Typ 130 RITERM 420 400 380 360 340 320 300 280 260 240 220 200 180 2 2.5 3 3.5 4 4.5 5 5.5 IPr eQ RIPRGM (kΩ ) where VITERM_Typ designates the typical value of VITERM. (See the Termination Current section for precharge current accuracy.) When the timer is enabled, there is a maximum allowed pre-charge duration. If the pre-charge time exceeds 25% of the total charge cycle, the charger will turn off due to a pre-charge fault. This fault is cleared Figure 1a — Fast-charge Current Variation vs. IPRGM Resistance, Low Resistance Range 15 SC908 Applications Information (continued) 200 180 Fast Charge Current (mA) 160 140 120 100 80 60 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 RIPRGM (kΩ ) Figure 1b — Fast-charge Current Variation vs. IPRGM Resistance, High Resistance Range The figures show the nominal current versus nominal RIPRGM resistance as the center plot and two theoretical limit plots indicating maximum and minimum current versus nominal programming resistance. These plots are derived from models of the expected worst-case contribution of error sources depending on programmed current. The current range includes the uncertainty due to 1% tolerance resistors. The dots on each plot indicate the currents obtained with standard value 1% tolerance resistors. The figures show low and high resistance ranges. Termination current can be programmed from 14mA to 65mA, and must be less than IFQ for correct operation of the charge cycle. Pre-charge and termination current regulation accuracy is dominated by offset error. The range of expected pre-charge output current and termination threshold current versus programming resistance RITERM is shown in Figures 2a and 2b. The figures show the nominal pre-charge and termination current versus nominal resistance as the center plot. Two theoretical limit plots indicate maximum and minimum current versus nominal programming resistance. These plots are derived from models of the expected worst-case contribution of error sources depending on programmed current. The current range includes the uncertainty due to 1% tolerance resistors. The dots on each plot indicate the currents obtained with standard value 1% tolerance resistors. The figures show low and high resistance ranges. A sufficient separation between IFQ and ITERM must be maintained to ensure proper operation of the constant current regulator and charge termination detector. RIPRGM and RITERM must be chosen to nominally satisfy IFQ > ITERM + 90mA 75 70 65 Precharge/Termination Current (mA) 60 55 50 45 40 35 30 25 20 Termination Current When the battery voltage reaches VCV, the SC908 transitions from constant current mode to constant voltage mode. As the output holds the voltage measured at the BSEN pin constant, the current through the battery will decrease as the battery becomes fully charged. CHRGB is disabled when the output current drops below the programmed termination current. If the timer is enabled, the output will continue to float-charge in CV mode until the charge timer expires. If the timer is disabled, the output will turn off as soon as the termination current level is reached. The termination current is determined by VITERM _ Typ 130 RITERM 3 3.5 4 4.5 5 5.5 6 6.5 RITERM (kΩ ) Figure 2a — Pre-charge and Termination Current Variation vs. ITERM Resistance, Low Resistance Range ITERM IPr eQ 16 SC908 Applications Information (continued) 40 35 Precharge/Termination Current (mA) 30 the battery voltage falls below the recharge threshold (VCV - VReQ), the charger will clear the charge timer and initiate a charge cycle. The status of the charger output as a function of the Charge Complete timer status and IBAT is shown in Table 1. Table 1 — Charger Output Status 25 20 Timer 15 Iout N/A N/A < Itermination Output State On Off Off t < Timeout 10 t > Timeout Disabled 5 0 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 RITERM (kΩ ) Remote Kelvin Sensing at the Battery The BSEN pin provides for Kelvin sensing of the battery positive terminal voltage. This prevents feedback error due to charging, battery load, and switching regulator input currents flowing over resistive PCB traces. Optimal PCB layout routes the BSEN trace directly to the battery positive terminal connection on the PCB to achieve the most accurate sensing of battery cell voltage. Connecting BSEN to BAT directly at the SC908 will introduce battery voltage measurement error that can cause an improper transition from CC to CV regulation, lengthening the charge time. This error could also raise or lower the final battery voltage, and may alter the final state-of-charge. Figure 2b — Pre-charge and Termination Current Variation vs. ITERM Resistance, High Resistance Range Charge Timer The timer provides over-charging protection in the event of a faulty battery and maximizes charging capacity. The RTIME pin is connected to VSYS to select the internal (default) time duration of three hours, and to GND to disable the timer. Connecting a resistor between RTIME and GND will program the Charge Complete Time-Out, in hours, according to the equation t QComp RRTIME 3.334 1 3600 The timer is programmable over the range of 2 to 6 hours. The output is automatically turned off when the charge timer cycle ends. If the charge cycle remains in precharge for longer than one fourth of the Charge Complete Time-Out period, a charging fault is detected and the charger turns off. The Precharge Fault Time-Out period, in minutes, is t QComp 4 EN_NTC Interface The EN_NTC pin is the interface to a battery pack temperature sensing Negative Temperature Coefficient (NTC) thermistor, which can be used to suspend charging if the battery pack temperature is outside of a safe-to-charge range. It is also the charger-disable input. The typical EN_NTC network is a fixed resistor from VSYS to the EN_NTC pin, and the battery pack EN_NTC thermistor from the EN_NTC pin to ground. In this configuration, an increasing battery temperature produces a decreasing NTC pin voltage. When VEN_NTC is greater than the high (cold) threshold or less than the low (hot) threshold, the charge cycle is suspended by turning off the output. This suspends but does not reset the charge timer, and indicates a fault on the FLTB pin. Hysteresis is included for both high and low 17 tPr eQF 60 Monitor Mode When a charge cycle is complete (termination if the timer is disabled, charge timeout if the timer is enabled), the output turns off and the device enters monitor mode. If SC908 Applications Information (continued) NTC thresholds to avoid chatter at the NTC fault thresholds. When VEN_NTC returns to the valid range, the charge timer resumes and the charge cycle continues. The charge timer will expire when the output on-time exceeds the timer setting, regardless of how long it has been disabled due to an NTC fault. Using the recommended NTC external network, the EN_NTC pin voltage and the internal hot and cold NTC thresholds are all ratios of VVSYS, rather than absolute voltages. This ensures that the hot and cold OK-to-charge thresholds are insensitive to the VSYS pin output voltage. The ratiometric thresholds are given by the parameters RTNTCH and RTNTCC. EN_NTC pin voltage VEN_NTC between RTNTCH×VVSYS and RTNTCC×VVSYS enables charging. When VEN_NTC is outside this range, charging is suspended and the FLTB output is asserted (pulled low). When VEN_NTC < VTNTCDIS (nominally 0.6V), the SC908 charger is disabled. The EN_NTC pin can be pulled to ground by an external n-channel FET or microprocessor GPIO to asnychronously disable or reset the device. When VEN_NTC < VTNTC_DIS, the charger is turned off, the charge timer is reset, and the CHRGB status output is turned off. While disabled, the VAD input UVLO and OVP threshold detectors remain active, and the CPB pin continues to indicate whether the VAD input voltage is valid for charging. The response of the SC908 to an EN_NTC pin voltage above the high threshold or below the low threshold (but above VTNTCDIS) is the same. Therefore the EN_NTC network can be configured with the battery pack thermistor between EN_NTC and VSYS, and a fixed resistor between EN_NTC and ground. This configuration may be used to reset the charge timer (and the CHRGB output) when the battery pack is removed; the fixed resistor pulls the NTC pin to ground to disable the charger without indicating a fault. sheet for the proposed NTC thermistor, the Mitsubishi TH11-3T223F, indicates that RNTC = 11.93kΩ at 40°C, and R NTC = 6 9.41k Ω a t 0°C, with a dissipation constant DC = 3.0mW/°C. So RHOT = 11.93kΩ and RCOLD = 69.41kΩ. Step 1 S elect RNPU to obtain one of the desired temperature thresholds. This example will solve for the hot threshold for the normal (NTC thermistor to ground) configuration, then evaluate the cold threshold. Solve the NTC network voltage divider for R NPU t o place the NTC voltage at RTNTC_HF × VVSYS when RNTC = RHOT. RTNTC _ HF VVSYS VVSYS RHOT RNPU RHOT or, solving for RNPU, RNPU 1 RTNTC _ HF RHOT RTNTC _ HF Using RTNTC_HF = 0.3, we obtain RNPU = 27.837kΩ exactly. The closest 1% standard nominal value is RNPU = 28.0kΩ. Step 2 Evaluate the NTC network at the cold threshold. Compute the NTC network resistor divider voltage as a function of VVSYS at the desired cold threshold. NTC COLD VVSYS R COLD R NPU R COLD 0.7126 VVSYS The value 0.7126 should be close to the nominal value of RTNTC_CR = 0.75. To evaluate the significance of the discrepancy, an estimate of the actual cold threshold is obtained by evaluating the value of R NTC_Cold_Actual t hat produces the nominal value of RT NTC_CR = 0 .75. RTNTC _ CR RNTC _ Cold _ Actual RNTC _ Cold _ Actual RNPU NTC Design Example This example uses the conventional NTC network configuration shown in the block diagram. A fixed resistor (RNPU) is connected between EN_NTC and VSYS, and a battery NTC thermistor (RNTC) is connected between the EN_NTC pin and ground. The battery temperature range over which charging is permitted is from 0°C to 40°C. The data- The solution shows RNTC_Cold_Actual = 84.0kΩ. Examination of the thermistor specification resistance versus temperature data indicates that the resulting actual cold threshold is approximately -4°C, compared to the target of 0°C. 18 SC908 Applications Information (continued) Step 3 With the example thermistor, there is no choice of RNPU that will yield the specified results at both hot and cold limits. A more sensitive thermistor, one with a wider percentage variation in resistance at the desired threshold temperatures, may provide a better solution. Steps 1 and 2 are repeated using other devices from the same vendor, seeking a closer match at the cold threshold. The Mitsubishi TH11-4C153F was the final selection. Its characteristics are: RHOT is 7.73kΩ (at 40°C), RCOLD is 53.94kΩ (at 0°C). Its dissipation constant DC = 3.0mW/°C. Step 1 yields RNPU = 18.2kΩ, with the result that NTCCOLD/VVSYS = 0.748 ≈ RTNTC_CR, NTCHOT/VVSYS = 0.298 ≈ RTNTC_HF. The NTC resistances that give the exact cold and hot thresholds RTNTC_CR and RTNTC_HF are 54.6kΩ (which is RNTC at approximately -0.5°C) and 7.80kΩ respectively, closely matching the resistance of the thermistor at the targeted threshold temperatures. Step 4 Verify acceptable thermistor self heating. The dissipation constant is the power rating of the thermistor resulting in a 1°C self heating error. Since accuracy is important only at the thresholds, self heating is assessed only at 0°C and 40°C. For VVSYS = 4.6V, the 0°C NTC network current is INTC_COLD = VVSYS/(RNPU + RCOLD) = 63.8μA Power dissipation in the thermistor at this temperature is PCOLD = RCOLD × (INTC_COLD)2 = 0.219mW The self heating error is TSH _ COLD 0.219mW 3 mW C 0.073 C for self heating of approximately 0.081°C. The actual cold and hot thresholds will be 0.073 and 0.081 degrees lower than designed, respectively, which are negligible errors. Logical CC-to-CV Transition The SC908 differs from most monolithic linear single cell Li-Ion chargers, which implement a linear transition from CC to CV regulation. The linear transition method uses two simultaneous feedback signals — output voltage and output current — to the closed-loop controller. When the output voltage is sufficiently below the CV regulation voltage, the influence of the voltage feedback is negligible and the output current is regulated to the desired current. As the battery voltage approaches the CV regulation voltage (4.2V), the voltage feedback signal begins to influence the control loop, which causes the output current to decrease although the output voltage has not reached 4.2V. The output voltage limit dominates the controller when the battery reaches 4.2V and eventually the controller is entirely in CV regulation. This system may be characterized as a dual-constraint (voltage and current) controller, with a soft transition between constraints. The soft transition effectively reduces the charge current below that which is permitted for a portion of the charge cycle, which increases charge time. In the SC908, a logical transition is implemented from CC to CV to recover the charge current lost due to the soft transition. The controller regulates only current until the output voltage exceeds the transition threshold voltage. It then asynchronously switches to CV regulation. The transition voltage from CC to CV regulation is typically less than 10mV higher than the CV regulation voltage, which provides a sharp and clean transition free of chatter between regulation modes. The difference between the transition voltage and the regulation voltage is the CC/CV overshoot. While in CV regulation, the output current is limited to approximately 105% of the fast-charge current programmed by the IPRGM pin or the IPUSB pin, depending on the charging input selected, providing mode transition hysteresis. If the output current exceeds this current limit threshold, the controller asynchronously reverts to current regulation. The logical transition from CC to CV results in the fastest possible charging cycle that is compliant with the speci19 The 40°C NTC network current INTC_HOT = VVSYS/(RNPU + RHOT ) = 0.177mA Power dissipation in the thermistor at this temperature is PHOT = RHOT × (INTC_HOT )2 = 0.243mW SC908 Applications Information (continued) fied current and voltage limits of the Li-Ion cell. The output current is constant at the CC limit, then decreases abruptly when the output voltage steps from the overshoot voltage to the regulation voltage at the transition to CV control. This can be compared to voltage and current trajectories for other monolithic charger devices to show the softness of the linear crossover. This explains the charge-time advantage of the SC908 logical crossover method. Input Over-Voltage Protection The VAD input is protected from adapter over-voltage to at least 28V above VDGND. When VVAD exceeds its OVP rising threshold VADOVP-R the charger turns off its output while the charge timer continues to run, and the FLTB status indicator is asserted. When VVAD subsequently falls below the VAD OVP falling threshold VADOVP-F, charging continues normally and FLTB is released. Thermal Protection The charger’s internal over-temperature (OT) threshold is set to approximately 145°C. If the temperature exceeds this threshold prior to termination, the charger output is turned off. All other functions remain active, the charger logical state is preserved, and no fault is indicated. This allows thermal pulse charging in conditions of high power dissipation. Following termination, a charger OT condition will be indicated as a fault. Refer to the Indicator Flags subsection for more information. A second high OT threshold is set to approximately 165°C. Should the die temperature exceed this threshold, all SC908 functions are disabled, and the status outputs indicate an exceptional condition fault. Refer to the Indicator Flags subsection for more information. Charger Protection Features The protection features are: • • • • Short Circuit Protection Over Current and Max Temperature Protection Input Overvoltage Protection Thermal Protection Short Circuit Protection The BAT output can tolerate an indefinite short circuit to ground. The current into a ground short will be equal to the precharge current. The ITERM pin voltage prior to termination, and the IPRGM pin voltage while in CC mode, are regulated to 1.5V. Precharge current and termination current are proportional to the resulting ITERM current, and CC current is proportional to the resulting IPRGM current. High battery current is prevented by pinshort detectors on both programming pins. Pinshort detection asynchronously forces the charger into reset, turning off the output and clearing the charge timer. When the pinshort condition is removed, the charger begins normal operation automatically. Over Current and Max Temperature Protection Over current protection is provided in all modes of operation. When the device is in the charge mode the output is current-limited to either the programmed pre-charge current or the programmed fast charge current, depending on the voltage at the output. Junction over-temperature protection allows operation with maximum power dissipation by disabling the charger output current when the die temperature reaches the maximum operating temperature. This results in operation as a pulse charger in extreme power dissipation applications, delivering the maximum allowable output current while limiting the internal die temperature to a safe level. Low Battery Detector Operation The low battery detector provides two low battery detection voltage thresholds: a fixed warning threshold and a resistor programmable detection (shutdown request) threshold. The low battery detector is enabled when either the buck converter is enabled (SEN is high) or the LDO regulator is enabled (LEN is high). The warning and shutdown request are provided by the status output pins FLTB and LBATB, as described in the Status Outputs subsection. When a charging adapter is present (V VAD > VADUVLO-x), the FLTB and LBATB outputs are redefined to reflect the interaction of battery voltage and charging state. The low battery detector warning threshold is fixed at 3.28V ± 70mV. The battery voltage fault threshold is programmable, with a resistor from the RLBAT pin to ground, 20 SC908 Applications Information (continued) from 2.77V to 2.98V, ±10%. The low battery fault threshold is set by the relationship VDET = 3.9 μA × RRLBAT × 2.42 RRLBAT must satisfy the condition 294kΩ ≤ RRLBAT ≤ 316kΩ Connect RLBAT to GND to disable the Low Battery Detector fault. The Low Battery Detector warning remains active. The CHRGB output indicates the battery charging status. The charger-present status output states are described in Table 3. When pre-charging or when the output current is greater than ITERM, CHRGB is low. The CHRGB output is latched off (high) when the output current becomes less than ITERM during the charge cycle (and the battery voltage is above the recharge threshold, VBSEN > VCV - V TReQ). This latch is reset when the battery enters a recharge cycle (VBSEN < VCV - V TReQ), or for any NTC_EN range other than OK-to-charge, or if VVAD is above or below the VAD validto-charge range, allowing CHRGB to become active again when charging resumes. When a charging adapter is present, the FLTB and LBATB outputs are redefined to reflect the interaction of the battery voltage, charging state, and charging faults, as described in Table 3. The FLTB output is activated when the device experiences a charger fault condition, or (together with LBATB output) when the battery voltage is less than the resistor-programmed low-battery detector threshold, VDET. This output can be used to notify the system controller of a fault condition when connected to an interrupt input, or it can be used like CPB and CHRGB to drive an indicator LED. When VVAD is between its UVLO and OVP thresholds, VVAD is valid to charge, and the CPB output is low indicating that a charging adapter is present. Status Outputs Four charger status outputs/LED drivers are provided. • • • • CPB (Charger Present) CHRGB (Charge Active) FLTB (Fault) LBATB (Low Battery Warning) These outputs are active-low, open drain NMOS drivers capable of sinking up to 2mA each. The state of each, in various operating conditions, is defined in Tables 2, 3, and 4. When the VAD voltage is below its UVLO threshold (no charging adapter is present), the CPB and CHRGB outputs are off (high impedance). The FLTB and LBATB outputs indicate the battery voltage as defined in Table 2. Table 2 — Status Output State, Charging Adapter Absent Conditions Status Pins Output State (on = low) Adapter Voltage (mutually exclusive) VADUVLO < VVAD < VADOVP Description and Comments VWARN > VBSEN > VDET Battery Voltage (mutually exclusive) VVAD < VADUVLO VVAD > VADOVP VBSEN ≥ VWARN VDET ≥ VBSEN T on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition No Charging Adapter, Battery Voltage Good CHRGB off off off off off off off off on off on on LBATB FLTB CPB T T T T T No Charging Adapter, Low Battery Voltage Warning No Charging Adapter, Low Battery Shutdown Request 21 SC908 Applications Information (continued) The fault modes signaled by FLTB are: • • • • When any of these conditions occurs the FLTB output goes low; otherwise it remains high impedance. The LBATB output is active when the battery voltage is below the low-battery warning voltage, VWARN, if the charging adapter is absent. If CPB and CHRGB outputs are both active, LBATB indicates when the charger is in precharge mode. However, LBATB and FLTB active together always input over-voltage battery NTC temperature out of range pre-charge timeout. charger-only over-temperature (low OT, posttermination only) Table 3 — Status Output State, Charging Adapter Present Conditions Status Pins Output State (on = low) Adapter Voltage (mutually exclusive) VADUVLO < VVAD < VADOVP Battery Voltage (mutually exclusive) EN_NTC (mutually exclusive) Charging State, Charging Faults (Internal signals) Description and Comments Pre-Charge Timeout F F F F F F F F Pre-Term Charging VWARN > VBSEN > VDET BAT Short-to-GND NTC Hot or Cold VVAD < VADUVLO Pre-Charging VVAD > VADOVP VBSEN ≥ VWARN Charger OT VDET ≥ VBSEN on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition T on off off off T T F T on off off on T T T T on off on off T F T T T on off on on T T T F on on on on on on on on off off on on off on off on T T T T F F F T T T T T - NTC OK Disable CHRGB LBATB FLTB CPB F - F - F - F - VVAD valid, Charger Disable/Reset OR Charging Done (Die Temperature OK) VVAD valid and Low Battery Warning, Charger Disable/Reset OR Charge Cycle Pending (about to begin) VVAD valid, Battery Temperature Fault OR Charger Over-Temp Fault (Die Temp > TCHRGR_OT ) VVAD valid, Low Battery Detected, with either Charger Disable/Reset OR Battery Temperature Fault OR Charger Over-Temp Fault OR BAT short-to-ground VVAD valid, Pre-termination Charging, Battery Voltage > VDET VVAD valid, Pre-Charging (trickle charging), Battery Voltage > VDET VVAD valid, Pre-Charging with Charger Over-Temp Fault, Battery Voltage > VDET VVAD valid, Battery Voltage < VDET Pre-Charging or Pre-Termination Charging F T T F T T F F F F F F T T - F T T T T 22 SC908 Applications Information (continued) indicates that the battery voltage is below the low-battery detect threshold, VDET. Table 3 gives a comprehensive description of all combinations of status output states while the adapter input is valid for charging. Exceptions to these charging conditions occur when certain events happen in combination. Table 4 describes status condition exceptions. These exceptions include VVAD > OVP threshold; a high over temperature condition, in which device temperature exceeds the higher of two over-temperature thresholds, causing charging and both regulators to be disabled; a precharge timeout, which may indicate a faulty battery. The load on VSYS should not exceed 5mA. If CHRGB is used to operate an indicator LED, it is recommended that the CHRGB status pin be pulled up to the battery or to a battery-powered regulated supply. Since CHRGB is asserted only while charging the battery, the current sunk by CHRGB will be sourced by the charger output and will not discharge the battery. Because VSYS is powered from VAD, it is unsuitable as a pullup source for the FLTB and LBATB status pins. These status pins must be powered from the battery or batterypowered regulated supply to function as battery level indicators when the charging adapter is not present. VSYS pin The voltage of the VSYS pin is regulated from the VAD input and is present only when VAD is powered. VSYS provides an external voltage reference and supply for the NTC network, and a pull-up supply voltage for the CPB status indicator. A capacitor of at least 0.1uF should be connected from VSYS to ground near the pin. Capacitor Selection Low cost, low ESR ceramic capacitors such as the X5R and X7R dielectric material types are recommended. The BAT pin capacitor, CBAT, range is 1μF to 22μF. This capacitor functions as both the charger output capacitor and as the switching regulator input capacitor. The VAD pin input capacitor CVAD is typically between 0.1μF to 2.2μF; however, larger values will not degrade performance. Table 4 — Status Output State, Exception Conditions Conditions Status Pins Output State (on = low) Adapter Voltage (mutually exclusive) VADUVLO < VVAD < VADOVP Battery Voltage (mutually exclusive) EN_NTC (mutually exclusive) Charging State, Charging Faults (Internal signals) Description and Comments Charger OT, (High OT) Pre-Charge Timeout F F T Pre-Term Charging VWARN > VBSEN > VDET BAT Short-to-GND NTC Hot or Cold on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition VAD Overvoltage, Battery Voltage Good or Warning VAD Overvoltage, Low Battery Detect High-Over-Temperature Detection (die temperature > TOT; all functions shutdown.) Pre-charge Timeout, NTC Not Disable, Adapter Voltage Good or OVP VVAD < VADUVLO off off off off off off on on on on on on off on off on F - T T - T T T - F - - Hi OT - - Pre-Charging - VVAD > VADOVP VBSEN ≥ VWARN VDET ≥ VBSEN NTC OK Disable CHRGB LBATB FLTB CPB - 23 SC908 Applications Information (continued) LDO Regulator The low-noise low-dropout (LDO) voltage regulator operates from an LVIN pin input voltage range of 2.2V up to the battery voltage (VBAT ), and an output voltage from 1.5V to 3.3V, programmable with external resistors. The SC908 has a VREF bypass pin to enable the user to capacitively decouple the bandgap reference (10nF recommended) for very low output noise (50μVRMS typically). The output voltage of the LDO regulator is divided externally using a resistor divider and compared to the buffered bandgap voltage, typically 0.75V. The error amplifier drives the gate of a low RDS(ON) P-channel MOSFET pass device. 1.5V to 3.3V by an external resistor divider network from LVOUT to LFB. The output voltage is set by LFB is a high impedance input, so large value resistors, even on the order of 500kΩ, may be used to meet the noise specification. When considering the effect of LDO load current on performance specifications, the current flowing in the feedback divider network should be included in the load. The LDO is internally compensated. No feedback capacitor is required for stability. LDO Dropout The LDO dropout voltage is the product of the minimum RDS(ON) of the P-channel MOSFET pass device and the LDO output current. As VLVIN decreases, the achievable sourceto-gate voltage of the pass device decreases, so the minimum achievable RDS(ON) becomes larger. This is the reason for the two-tier dropout specification. Minimum RDS(ON) increases with die temperature, which is affected not only by LDO power dissipation, but also by switching regulator and charger power dissipation. The maximum dropout is specified for a temperature of 85°C. Enabling the LDO The LDO has an independent enable input pin (active high). The LDO can be enabled only if VLVIN ≥ V TLUVLO, typically 2.0V, although performance specifications are guaranteed for VLVIN ≥ 2.2V. The LDO output will settle to within 5% of its final value in 0.1ms (typically) when the bandgap reference buffer has already settled (when the switching regulator is already enabled, or when the charging adapter is present). A fast start-up circuit is used to speed the initial charging time of the VREF pin bypass capacitor. This is done so that the LDO output voltage will settle to within 5% of its final value in 0.4ms (typically) when the LDO is the first resource enabled. When the battery charger is in its precharge mode of operation (trickle charging of a deeply discharged battery), the LDO enable signal will be disregarded until fast-charging begins (at a battery voltage of 2.8V typically). An exception occurs when either the LDO or switching regulator are already enabled. At this time when a charging source is applied and the charger enters precharge mode, the LDO will remain enabled (or can become enabled). Precharge mode is indicated by the status outputs. (Refer to Table 3.) The LDO provides active shutdown. The capacitance on LVOUT will be discharged by an on-chip FET when the LDO is disabled. LDO Reference Voltage The internal bandgap reference voltage must be externally bypassed to meet the LDO noise specification. A 10nF ceramic capacitor from the VREF pin to AGND is recommended to bypass the bandgap reference buffer. Increasing this capacitor to 100nF will improve power supply rejection, but at the cost of slower turn-on settling time. All noise and turn-on settling time specifications assume that the VREF bypass capacitor is 10nF. Low cost, low ESR ceramic capacitors such as the X5R and X7R dielectric material types are recommended. The bandgap reference is trimmed and buffered to obtain 0.75V typically at the LFB pin with respect to AGND while the LDO is operating. VVREF is the reference voltage for LFB, so VVREF will be equal to VLFB within the offset error of the LDO feedback error amplifier. The bandgap reference and reference buffer are powered from the greater of V VSYS (derived from VAD, when present) and VBAT (the battery voltage). The PSRRREF specification is with respect to VBAT. It is evaluated while the charging adapter is not present. 24 Programming the LDO Output Voltage The LDO regulates its output to obtain 0.75V at the LFB pin. The output can be programmed to any voltage from SC908 Applications Information (continued) VREF power supply rejection with respect to VAD will be similar. The VREF pin is a high impedance source. Any load on VREF will degrade LDO and switching regulator voltage accuracy. Note that the 10MΩ impedance of a typical oscilloscope probe is not large enough to prevent loading of the VREF pin. improving overall load transient response, and may also improve input supply rejection. Switching Regulator The SC908 contains a synchronous step-down Pulse Width Modulated (PWM), DC-DC converter (also referred to as a Buck Converter or Switcher) with integrated power devices. The switching frequency is set nominally to 1MHz, allowing the use of small inductors and capacitors. The current limit of the internal PMOS switch (ILIM_P), allows a DC output current of at least 150mA with appropriate external components. For maximum efficiency over the full load range, the switcher will automatically operate in Power Save (PSAVE) mode with light loads, and in PWM (normal switching) mode for heavier loads. The voltage feedback loop uses an external feedback divider. An internal synchronous NMOS low side switch is used. An external Schottky diode on the LX pin is not required. LDO Power Supply Rejection Power supply rejection must be considered with respect to two inputs. The buffered bandgap reference is powered by the greater of two possible sources, VVSYS (an internal/ external supply voltage, derived from VAD when present) and VBAT. The LDO is powered from the LVIN pin. PSRRL is defined as the power supply rejection from LVIN to LVOUT with the reference and reference buffer powered from BAT as DC voltage. The reference voltage VREF power supply rejection specification (PSRRREF) is with respect to BAT. Any reference voltage power supply noise or ripple is seen in the LDO as noise on the LFB reference voltage. This noise is then gained-up to the output by the reciprocal of the LFB divider network, or by the gain (1 + RL1/RL2). In the special case VLVIN = VBAT (the LVIN pin is connected directly to the battery), the power supply rejection of the LDO, PSRRLBAT, is determined by PSRRLBAT 20 log10 1 RL1 RL 2 10 PSRR REF 20 Switcher Programmable Output Voltage The buck converter regulates its output to obtain 0.5V at the SFB pin. The output can be programmed to any voltage from 1.0V to 3.0V by an external resistor divider network from the external circuit node SVOUT to the SFB pin. The equation for setting the output voltage is 10 PSRR L 20 LDO Current Limit and Short-Circuit Protection The LDO regulator has current limit circuitry to ensure that the output current will not damage the device during output short-circuit to ground, overload, or start-up. The current limit is guaranteed to be greater than 200mA to allow fast charging of the output capacitor and for high transient load currents. SFB is a high impedance input, therefore the magnitude of resistances used will be determined by a trade off between feedback network current and product design practice. A 25pF feedback capacitor, designated CSFB, is required for stability in PWM mode. When considering the effect of buck converter load current on performance specifications, the current flowing in the feedback divider network should be included in the load. In most situations, PSAVE mode operation will require a capacitor from SFB to AGND. Refer to the PSAVE mode description. LDO Input and Output Capacitor A minimum LDO input and output capacitance of 1μF with a maximum equivalent series resistance (ESR) of less than 1Ω over temperature is recommended. Increasing the output capacitance will further reduce output noise and improve load transient response. A larger input capacitor will reduce input droop due to load transients, Switcher Power Save (PSAVE) Mode Operation The PSAVE mode is automatically activated or deactivated with light to heavy loads, maximizing efficiency across the 25 SC908 Applications Information (continued) full load range. The SC908 automatically detects the load current at which it should enter PSAVE mode. This detection is based on the minimum peak current in the PMOS high side switch in PWM mode. This will vary with input voltage, output voltage, and the converter external inductance (LS). PSAVE entry DC load current will decrease with decreasing LS. In a PSAVE mode burst cycle, VSVOUT rises from a lower to an upper voltage threshold with a switching burst (see Figure 3). Within the burst, the PMOS switch is turned on until the PMOS current reaches a current limit. It is then turned off for a fixed duration, and then turned on again (cycle may be repeated). The low-side NMOS switch is turned on whenever the high-side switch is off. When the upper threshold (1.5% above the programmed regulation voltage) is reached, the switching burst is halted. This reduces the quiescent current by turning off both highside and low-side switches. VSVOUT decays to the lower threshold (0.8% above the programmed regulation voltage) due to the load current discharging the output capacitor, which initiates another switching burst. The burst-time to off-time ratio in PSAVE will decrease with decreasing load current. PSAVE Mode at Moderate Load BURST OFF BURST lope frequency will exceed 20kHz for any load greater than 3mA, if external component recommendations have been followed. The envelope minimum frequency will decrease with increasing CSVOUT capacitance. The SC908 automatically detects when to exit PSAVE mode by monitoring VSFB, and thus VSVOUT. If the switching burst output current is insufficient to supply the output load, VSVOUT will not rise to the upper threshold during a switching burst, but will instead decrease. If VSVOUT droops to 2% below the programmed regulation voltage, PSAVE mode will be deactivated, and the buck converter will revert immediately to PWM mode. To prevent rapid PWM/ PSAVE mode cycling, the PSAVE entry and exit criteria are chosen to provide load hysteresis. After reverting to PWM mode the switcher will remain in PWM mode for 128 switching cycles (approximately 128μs) before it is permitted to re-enter PSAVE mode. Proper operation of PSAVE mode requires the addition of a capacitor from the SFB pin to ground, designated CSFG, of value CSFG = CSFB × RS1 / RS2. Higher Load Applied OFF Switcher Efficiency PSAVE Mode at High Load BURST PWM Mode at High Load PWM Mode +1.6% VSVOUT +0.8% Prog’d Voltage Switcher efficiency is affected by input voltage, output voltage, temperature, and choice of inductor. It also varies with load, and on which mode, PWM or PSAVE, is active. The mode selection depends not only on the instantaneous load, but also on the immediate past load, since transitions between PSAVE and PWM modes are load dependent, with hysteresis. For high loads (those that unconditionally place the switcher in PWM mode), the efficiency typically exceeds 90%. For low loads (those that unconditionally place the switcher in PSAVE mode), efficiency can vary from 88 to 92% over all conditions. As the load decreases further, the SC908 quiescent current eventually becomes significant, and efficiency drops off sharply. At intermediate modes, the switcher could select either PSAVE or PWM mode depending on whether the recent past load was higher or lower, due to load hysteresis. Within the hysteresis load range, efficiency can vary from 86% to 92%, over all conditions. 26 -2% Inductor Current 0A Time Figure 3 Power Save Operation The PSAVE switching burst is designed so that the inductor current ripple is similar to that of PWM mode. To prevent audible noise, the PSAVE mode parameters have been chosen such that the minimum PSAVE burst enve- SC908 Applications Information (continued) Switcher Protection Features The protection features are: The inductor should have a low DCR to minimize the conduction losses and maximize efficiency. As a minimum requirement, the DC current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple as shown by the equation IL S (Peak ) IOUT(MAX ) IL S 2 • • • Current limit Over-voltage protection Soft-start Current Limit The PMOS power device in the buck switcher stage is protected by a current limit function. If a short to ground on the output occurs, the part enters frequency foldback mode, which causes the switching frequency to divide by a factor determined by the output voltage. This prevents the inductor current from stair-casing. Over-Voltage Protection In the event of over-voltage on the output in PWM mode, the PWM drive is disabled. When disabled, the SLX output becomes high impedance (both high-side and low-side switches are turned off ). The switcher will not resume switching until the output voltage has fallen to 2% below the programmed regulation voltage. Soft-Start The soft-start mode is enabled after every shutdown cycle to limit in-rush current. This controls the maximum current during start-up. The PMOS current limit is stepped up using three soft-start levels to the full value by a timer driven from the internal oscillator. During soft-start, the switching frequency is stepped by 1/8, 1/4, and 1/2 of the internal oscillator frequency up to the full value, under control of three output voltage thresholds. When the output voltage rises to 98% of the regulation voltage, softstart mode is disabled. Final inductor selection will depend on various design considerations such as efficiency, EMI, PSAVE entry, size and cost. CBAT Selection CBAT functions as both the charger output capacitor and as the switching regulator input capacitor. The source input current to a buck converter is non-continuous. To prevent large input voltage ripple a low ESR ceramic capacitor is required. A minimum value of 10μF should be used for sufficient input voltage filtering and a 22μF should be used for improved input voltage filtering. CSVOUT Selection The internal compensation is designed to operate with a minimum output capacitor value of 10μF. Larger output capacitor values will improve transient performance. Output voltage ripple is a combination of the voltage ripple from the inductor current charging and discharging the output capacitor and the voltage created from the inductor current ripple through the output capacitor ESR. Selecting an output capacitor with a low ESR will reduce the output voltage ripple component, as can be seen in the equation VSVOUT (ESR ) ILS ( ripple ) ESR CSVOUT Switcher External Components The SC908 is designed for use with the inductor LS = 4.7μH, although other values can be used. The magnitude of the inductor current ripple is dependent on the inductor value and can be determined by the equation VSVOUT VSVOUT 1 L S fosc VVOUT Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. When selecting an output capacitor, it is essential that CSVOUT capacitance be evaluated at the VSVOUT programmed voltage. The specified capacitance of 0402, and even 0603, package size devices is often severely derated at just 27 ILS This equation demonstrates the relationship between input voltage, output voltage, and inductor ripple current. SC908 Applications Information (continued) a few volts of bias. This is especially true of inexpensive dielectrics. Insufficient SVOUT capacitance can cause rapid decay of output voltage between PSAVE bursts, resulting in poor low-load efficiency, PSAVE/PWM mode cycling, and other erratic behaviors. Charger Grounding and PCB Layout Considerations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. Switcher Grounding and PCB Layout Considerations Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce and resistive voltage losses. Poor regulation and instability can result. A few simple design rules can be implemented to ensure good layout: • • • • • • • • Place the inductor and filter capacitors as close to the device as possible and use short wide traces between the power components. Route the output voltage feedback path away from the inductor and LX node to minimize noise and magnetic interference. Maximize ground metal on the component side to improve the return connection and thermal dissipation. Separation between the SLX node and GND should be maintained to avoid coupling of switching noise to the ground plane. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. • • Attaching the part to a larger copper footprint will enable better heat transfer from the device, especially on PCBs with internal ground and power planes. Place the input, output and bypass capacitors close to the device for optimal transient response and device behavior. Connect all ground connections directly to the ground plane. If there is no ground plane, connect to a common local ground point before connecting to board ground. The DGND pin and PGND pin should be connected directly to the PCB ground plane as close to the part as possible. The thermal pad should be connected to the ground plane with thermal vias under the SC908. The nodes indicated as AGND in the Block Diagram should be connected together and to the AGND pin. The AGND pin should be tied to the DGND pin at a single point close to the SC908. Route the BSEN trace directly to the battery positive terminal connection on the PCB. 28 SC908 Outline Drawing — MLPQ-24 4x4 DIMENSIONS MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A .031 .035 .039 0.80 0.90 1.00 A1 .000 .001 .002 0.00 0.02 0.05 (.008) (0.20) A2 .010 .012 0.18 0.25 0.30 b .007 D .152 .157 .163 3.85 4.00 4.15 D1 .100 .106 .110 2.55 2.70 2.80 E .152 .157 .163 3.85 4.00 4.15 E1 .100 .106 .110 2.55 2.70 2.80 e 0.50 BSC .020 BSC L .012 .016 .020 0.30 0.40 0.50 N 24 24 aaa 0.10 .004 .004 0.10 bbb A D B PIN 1 INDICATOR (LASER MARK) E A2 A aaa C A1 D1 LxN E/2 E1 2 1 N bxN e bbb C SEATING PLANE CAB D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 29 SC908 Land Pattern — MLPQ-24 4x4 K DIMENSIONS DIM C G H K P X Y Z INCHES (.156) .122 .106 .106 .020 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80 (C) H G Z X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 30