SFC3.3-4.BCT

PROTECTION PROTECTION PRODUCTS Description The SFC3.3-4 is a quad flip chip TVS diode array. They are state-of-the-art devices that utilize solid-state EPD TVS technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latch-up due to electrostatic discharge (ESD) and other voltage induced transient events. The SFC3.3-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures approximately 1.5 by 1.0 mm. It has a very low profile of < 0.65 mm. This is a crucial specification for many portable applications. Each device will protect up to four data or I/O lines. The flip chip design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. The devices are constructed using Semtech’s proprietary EPD process technology. The EPD process provides low standoff voltages with significant reductions in leakage currents and capacitance over siliconavalanche diode processes. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). Low Voltage ChipClampΤΜ Flip Chip TVS Diode Array Features 150 Watts peak pulse power (tp = 8/20µs) Transient protection for data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20µs) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 3.3V Solid-state EPD TVS technology SFC3.3-4 Mechanical Characteristics JEDEC MO-211, 0.50 mm Flip Chip Package Non-conductive top side coating Marking : Marking Code Packaging : Tape and Reel Applications Cell Phone Handsets and Accessories Personal Digital Assistants (PDAs) Notebook and Hand Held Computers Portable Instrumentation Pagers Smart Cards MP3 Players Device Dimensions Schematic & PIN Configuration B A 1 2 3 SFC3.3-4 Maximum Dimensions (mm) 3 x 2 Grid Flip Chip TVS (Bottom View) Revision 11/13/2008 1 www.semtech.com SFC3.3-4 PROTECTION PRODUCTS Absolute Maximum Rating R ating Peak Pulse Power (tp = 8/20µs) Peak Pulse Current (tp = 8/20µs) ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) Operating Temperature Storage Temperature Symbol Pp k IP P VESD TJ TSTG Value 150 15 >25 >15 -55 to +125 -55 to +150 PRELIMINARY Units Watts A kV °C °C Electrical Characteristics (T=25oC) Parameter Reverse Stand-Off Voltage Punch-Through Voltage Snap -Back Voltage Reverse Leakage Current Clamp ing Voltage Clamp ing Voltage Clamp ing Voltage Forward Clamp ing Voltage Junction Cap acitance Symbol VRWM V PT VSB IR VC VC VC VF Cj IPT = 2µA ISB = 50mA VRWM = 3.3V, T=25°C IPP = 1A, tp = 8/20µs Any I/O to Ground IPP = 5A, tp = 8/20µs Any I/O to Ground IPP = 15A, tp = 8/20µs Any I/O to Ground IPP = 1A, tp = 8/20µs Ground to any I/O Each I/O p in and Ground VR = 0V, f = 1MHz 75 3.5 2.8 0.05 0.5 4.5 6.8 9.5 1.7 100 Conditions Minimum Typical Maximum 3.3 Units V V V µA V V V V pF  2008 Semtech Corp. 2 www.semtech.com SFC3.3-4 PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time 10 Peak Pulse Power - Ppk (kW) PRELIMINARY Power Derating Curve 110 100 % of Rated Power or PP I 90 80 70 60 50 40 30 20 10 1 0.1 0.01 0.1 1 10 Pulse Duration - tp (µs) 100 1000 0 0 25 50 75 100 125 150 Ambient Temperature - TA (oC) Pulse Waveform 110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 Time (µs) 20 25 30 td = IPP/2 e -t Clamping Voltage vs. Peak Pulse Current 12.00 Waveform Parameters: tr = 8µs td = 20µs L to L Clamping Voltage - VC (V) 10.00 L to G 8.00 6.00 4.00 2.00 0.00 0 5 10 Peak Pulse Current - IPP (A) 15 20 Waveform Parameters: tr = 8µs td = 20µs Forward Voltage vs. Forward Current 4.00 Normalized Junction Capacitance vs. Reverse Voltage 1.5 1.4 1.3 Clamping Voltage - VC (V) 3.00 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 2.00 Waveform Parameters: tr = 8µs td = 20µs 1.00 CJ(VR) / CJ(VR=0) 0.00 0 5 10 Peak Pulse Current - IPP (A) 15 20 f = 1 MHz 0 1 0 Reverse Voltage - VR (V) 2 3 4  2008 Semtech Corp. 3 www.semtech.com SFC3.3-4 PROTECTION PRODUCTS Applications Information Device Connection Options The SFC3.3-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 and B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Due to the “snap-back” characteristics of the low voltage TVS, it is not recommended that any of the I/O bumps be directly connected to a DC source greater than snap-back votlage (VSB) as the device can latch on as described the EPD TVS characteristics section. Flip Chip TVS Flip chip TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC3.3-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.225 ± 0.010 mm with a solder mask opening of 0.350 ± 0.025 mm. Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems PRELIMINARY Device Schematic and Pin Configuration 6 B 5 4 A 1 2 3 Layout Example To Protected IC Ground To Protected IC To Connector NSMD Package Footprint  2008 Semtech Corp. 4 www.semtech.com SFC3.3-4 PROTECTION PRODUCTS and should be avoided. Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using the reflow requirements for IPC/JEDEC standard J-STD-020 for assembly of small body components. During reflow, the component will self-align itself on the pad. EPD TVS Characteristics The SFC3.3-4 is constructed using Semtech’s proprietary EPD technology. The structure of the EPD TVS is vastly different from the traditional pn-junction devices. At voltages below 5V, high leakage current and junction capacitance render conventional avalanche technology impractical for most applications. However, by utilizing the EPD technology, the SFC3.3-4 can effectively operate at 3.3V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in traditional silicon-avalanche TVS diodes. Since the EPD TVS devices use a 4-layer structure, they exhibit a slightly different IV characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage (VRWM). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage (VPT) is exceeded. Unlike a conventional device, the low voltage TVS will exhibit a slight negative resistance characteristic as it conducts current. This characteristic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. When the TVS is conducting current, it will exhibit a slight “snap-back” or negative resistance characteristics due to its structures. This point is defined on the curve by the snap-back voltage (VSB) and snap-back current (ISB). To return to a non-conducting state, the  2008 Semtech Corp. 5 PRELIMINARY Stencil Design Assembly Guideline for Pb-Free Soldering The following are recommendations for the assembly of this device: Assembly Parameter Solder Ball Composition Solder Stencil Design Solder Stencil Thickness Solder Paste Composition Solder Paste Type Solder Reflow Profile PCB Solder Pad Design PCB Pad Finish R ecommendation 95.5Sn/3.8Ag/0.7Cu Same as the SnPb design 0.100 mm (0.004") Sn Ag (3-4) Cu (0.5-0.9) Type 4 size sphere or smaller per JEDEC J-STD-020 Same as the SnPb Design OSP or AuN i current through the device must fall below the ISB (approximately