SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
GENERAL DESCRIPTION
FEATURES
The SGM58031 is a low-power, 16-bit, precision,
● Single-Supply Voltage Range: 3V to 5.5V
delta-sigma (ΔΣ) analog-to-digital converter (ADC). It
operates from a 3V to 5.5V supply.
The SGM58031 contains an on-chip reference and
2
oscillator. It has an I C-compatible interface, and it can
2
select four I C slave addresses. The data rate of the
filter is up to 960SPS. The SGM58031 has an on-chip
PGA, which can provide input ranges to as low as
±256mV from the power supply.
The input multiplexer supports 4 single-ended inputs or
2
I C Bus Voltage Range: 3V to 5.5V
● Low Quiescent Current:
Continuous Mode: 255μA (TYP)
Power-Down Mode: 0.8μA (TYP)
● Selectable Data Rates: 6.25SPS to 960SPS
● Input Multiplexer
4 Single-Ended Inputs or 2 Differential Inputs
● Internal Programmable Gain Amplifier (PGA)
● Internal Voltage Reference and Oscillator
● Selectable Digital Comparator
2 differential inputs configuration.
● I C-Compatible Serial Interface
The SGM58031 is available in Green MSOP-10 and
● Available in Green MSOP-10 and TDFN-3×3-10L
TDFN-3×3-10L packages. It operates over an ambient
2
Packages
temperature range of -40℃ to +125℃.
APPLICATIONS
Portable Devices
Process Control
Battery Monitoring System
Temperature Measurement
SG Micro Corp
www.sg-micro.com
JUNE 2022 – REV. A. 2
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
PACKAGE/ORDERING INFORMATION
MODEL
PACKAGE
DESCRIPTION
SPECIFIED
TEMPERATURE
RANGE
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MSOP-10
-40℃ to +125℃
SGM58031XMS10G/TR
SGM58031
XMS10
XXXXX
Tape and Reel, 4000
TDFN-3×3-10L
-40℃ to +125℃
SGM58031XTD10G/TR
SGM
58031D
XXXXX
Tape and Reel, 4000
SGM58031
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
XXXXX
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
Voltage Range (with Respect to GND)
VDD .................................................................. -0.3V to 5.5V
Analog Input Voltage....................................... -0.3V to 5.5V
SDA, SCL, ADDR, ALERT/RDY Voltage ........ -0.3V to 5.5V
Input Current (Momentary).......................................... 100mA
Input Current (Continuous) ........................................... 10mA
Junction Temperature .................................................+150℃
Storage Temperature Range ........................ -65℃ to +150℃
Lead Temperature (Soldering, 10s) ............................+260℃
ESD Susceptibility
HBM ............................................................................. 4000V
CDM ............................................................................ 1000V
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range ..................... -40℃ to +125℃
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failure to observe proper handling and installation procedures
can cause damage. ESD damage can range from subtle
performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
JUNE 2022
2
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
PIN CONFIGURATIONS
(TOP VIEW)
(TOP VIEW)
ADDR
1
10
SCL
ALERT/RDY
2
9
SDA
GND
3
8
AIN0
4
AIN1
5
ADDR
1
10
SCL
ALERT/RDY
2
9
SDA
VDD
GND
3
8
VDD
7
AIN3/VREFIN
AIN0
4
7
AIN3/VREFIN
6
AIN2
AIN1
5
6
AIN2
MSOP-10
EP
TDFN-3×3-10L
PIN DESCRIPTION
PIN
(1)
NAME
TYPE
1
ADDR
DI
I C Address Selection Pin.
2
2
ALERT/RDY
DO
Digital Comparator Output/Conversion Ready Pin.
3
3
GND
G
Ground.
4
4
AIN0
AI
Positive Input of Differential Channel 1 or Input of
Single-Ended Channel 1.
5
5
AIN1
AI
Negative Input of Differential Channel 1 or Input of
Single-Ended Channel 2.
6
6
AIN2
AI
Positive Input of Differential Channel 2 or Input of
Single-Ended Channel 3.
7
7
AIN3/VREFIN
AI
Negative Input of Differential Channel 2 or Input of
Single-Ended Channel 4, or External Reference Input.
8
8
VDD
P
Power Supply Pin. It can be operated from 3V to 5.5V.
9
9
SDA
DIO
10
10
SCL
DI
Serial Clock Input Pin.
‒
Exposed Pad
EP
‒
Exposed pad should be soldered to PCB board and
connected to GND.
MSOP-10
TDFN-3×3-10L
1
FUNCTION
2
Serial Data Pin.
NOTE:
1. AI = Analog Input, DI = Digital Input, DO = Digital Output, DIO = Digital Input and Output, P = Power, G = Ground.
SG Micro Corp
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JUNE 2022
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, Full-Scale (FS) = ±2.048V, maximum and minimum specifications apply from TA = -40℃ to +125℃, typical values
are at TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input
Full-Scale Input Voltage (1)
VIN = AINP - AINN
Analog Input Voltage
AINP or AINN to GND
±4.096/PGA
GND
Differential Input Impedance
V
VDD
V
See Table 1
System Performance
Resolution
No missing codes
Data Rate
16
Bits
DR
Data Rate Variation
See Table 5
All data rates
-6
Output Noise
INL
DR = 8SPS, FS = ±2.048V,
best fit (99% of full-scale)
1
%
4
LSB
differential inputs
1
5
single-ended inputs
2
8.5
0.005
0.06
Offset Error
FS = ±2.048V
Offset Drift
FS = ±2.048V
Offset Power-Supply Rejection
FS = ±2.048V
1.2
Gain Error (2)
FS = ±2.048V at +25℃
0.03
(3)
FS = ±0.256V
30
FS = ±2.048V
30
FS = ±6.144V (1)
30
Gain Power-Supply Rejection
PGA Gain Match
6
See Table 6 and Table 7
Integral Nonlinearity
Gain Drift
SPS
50
(2)
LSB
LSB/℃
LSB/V
0.3
%
70
ppm/℃
200
ppm/V
Match between any two PGA gains
0.1
0.28
%
Gain Match
Match between any two inputs
0.01
0.08
%
Offset Match
Match between any two gains
1
8.5
LSB
50/60Hz Rejection
FS = ±2.048V
95
dB
Channel-to-Channel Crosstalk
At DC and FS = ±2.048V, differential or
single-ended inputs adjacent channels
90
dB
At DC and FS = ±0.256V
110
Common-Mode Rejection Ratio
CMRR
At DC and FS = ±2.048V
At DC and FS = ±6.144V
110
(1)
dB
110
Internal Clock
Frequency
386
410
434
kHz
NOTES:
1. The full-scale range of the ADC scaling. In any event, it should not exceed VDD + 0.3V be applied to this device.
2. It includes all errors from on-chip PGA and reference.
3. Gain temperature drift is defined as the maximum change of gain error measured over the specified temperature range. The
gain error drift is calculated using the box method, as described by Equation: Gain Error Drift = (GEMAX - GEMIN)/(TMAX - TMIN).
Where:
• GEMAX and GEMIN are the maximum and minimum gain errors, respectively.
• TMAX and TMIN are the maximum and minimum temperatures, respectively, over the temperature range -40℃ to +125℃.
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JUNE 2022
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, Full-Scale (FS) = ±2.048V, maximum and minimum specifications apply from TA = -40℃ to +125℃, typical values
are at TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference
Internal Reference
2.048
External Reference
0.5
External Reference Input
Current
Digital Input/Output
High Input Voltage (4)
Low Input Voltage
(4)
VREFIN = 2.5V, continuous mode
V
2.5
V
0.45
VIH
μA
0.7 × VBUS
V
VIL
0.3 × VBUS
V
Low Output Voltage
VOL
IOL = 3mA
0.07
0.4
V
High Input Leakage Current (5)
IIH
VIH = 5.5V
0.1
1
μA
Low Input Leakage Current (5)
IIL
VIL = GND
0.1
1
μA
5.5
V
Power-Supply Requirements
Power-Supply Voltage
VDD
3
Power-down current at +25℃
Supply Current
Power Dissipation
IDD
PD
VDD = 5.5V
(6)
Power-down current up to +125℃
0.8
(6)
1
1.8
3.8
Operating current at +25℃
255
320
Operating current up to +125℃
270
340
VDD = 5V
1.05
VDD = 3.3V
0.6
μA
mW
NOTES:
4. There are 2 scenarios: VDD = 5V, VBUS can be 3V to 5V; VDD = 3.3V, VBUS should be 3.3V. Note that VBUS = 3V may cause
leakage in some extreme conditions, and it's better to make it higher than 3.1V. For VBUS = VDD, VIL/VIH = 30%/70% of VBUS. For
VBUS = 3.3V and VDD = 5V, VIL/VIH = 20%/80% of VBUS.
2
5. Meet the "loss of VDD" requirement of I C fast mode. When VDD is lost, the leakage drawn from the pin is controlled.
6. Power-down current increases to 2.3μA at +25℃ and 3.5μA at +125℃ when Config1 BUS_FLEX bit is set to '1'.
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
TIMING CHARACTERISTICS
PARAMETER
SYMBOL
SCL Operating Frequency
STANDARD MODE
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
MIN
MAX
0.1
0.01
0.4
0.01
3.4
UNITS
fSCL
0.01
Bus Free Time between START and STOP
Condition
t1
4700
600
160
ns
Hold Time after Repeated START Condition.
After This Period, the First Clock is Generated
t2
4000
600
160
ns
SCL Clock Low Time
t3
4700
1300
160
ns
SCL Clock High Time
t7
4000
600
60
ns
Repeated START Condition Setup Time
t9
4700
600
160
ns
Stop Condition Setup Time
t10
4000
600
160
ns
Data Hold Time
t5
0
0
0
ns
Data Setup Time
t8
250
100
10
ns
Clock/Data Fall Time
(1)
Clock/Data Rise Time
MHz
t6
300
300
160
ns
t4
1000
300
160
ns
NOTE:
1. t6 (MIN) for SDA output is 20ns for normal/fast mode and 10ns for high-speed mode. Glitch filter capability is 50ns for
normal/fast mode and 10ns for high-speed mode.
S
t8
t3
S
t6
P
t2
SCL
t2
t7
t9
t4
t10
SDA
t1
t5
2
Figure 1. I C Timing Diagram
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JUNE 2022
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
Gain Error Histogram
2000
Offset Error Histogram
3500
3926 Units
3030
Samples
From a Production Lot
1
FSProduction
= ±2.048VLot
3000
Number of Occurrences
Number of Occurrences
2500
1500
1000
500
2500
2000
1500
1000
500
0
-0.040
-0.035
-0.030
-0.025
-0.020
-0.015
-0.010
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0
Operating Current vs. Temperature
-2
-1
0
1
2
3
4
5
1.4
200
150
100
VDD = 3V
VDD = 3.3V
VDD = 5.5V
50
0
Power-Down Current (μA)
Operating Current (μA)
-3
1.6
250
1.2
1.0
0.8
0.6
0.4
VDD = 3V
VDD = 3.3V
VDD = 5.5V
0.2
0.0
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
Temperature (℃)
Temperature (℃)
Single-Ended Offset Error vs. Temperature
Differential Offset Error vs. Temperature
0.5
VDD = 3.3V
VDD = 5V
Differential Offset Error (LSB)
Single-Ended Offset Error (LSB)
-4
Power-Down Current vs. Temperature
300
0.0
-5
Offset Error (LSB)
Gain Error (%)
0.5
3926
From
3030 Units
Samples
a1 Production Lot
FS = ±2.048V,
Differential Inputs
-0.5
-1.0
-1.5
-2.0
0.0
-0.5
-1.0
-1.5
VDD = 3.3V
VDD = 5V
-2.0
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
Temperature (℃)
Temperature (℃)
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
INL vs. Temperature
1.0
0.5
VDD = 3.3V
VDD = 5V
Internal Oscillator Frequency (kHz)
Integral Nonlinearity (LSB)
1.5
0.0
Internal Oscillator Frequency vs. Temperature
412.5
2.0
412.0
411.5
411.0
410.5
410.0
409.5
408.5
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
VDD = 3.3V
CVDD = 100nF
CIN = 100nF
409.0
-40 -20
0
Temperature (℃)
0.3
0.2
0.15
0.1
0.05
-20
0
Data Rate = 6.25
20
40
60
80
-40
-60
-80
-100
VDD = 3.3V
VDD = 5V
0
-40
-120
100 120 140
0
10
20
30
40
50
60
Filter Response
80
90 100
Filter Response
0
0
70
Frequency (Hz)
Temperature (℃)
Data Rate = 25
Data Rate = 12.5
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
100 120 140
-20
0.25
-0.05
80
Filter Response
Magnitude (dB)
Gain Error (%)
0.35
60
0
FS = ±2.048V
CVDD = 100nF
CIN = 100nF
0.4
40
Temperature (℃)
Gain Error vs. Temperature
0.45
20
-60
-80
-100
-60
-80
-100
-120
-120
0
10
20
30
40
50
60
Frequency (Hz)
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70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
JUNE 2022
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
Filter Response
0
Data Rate = 50
Magnitude (dB)
-20
-40
-60
-80
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
FUNCTIONAL BLOCK DIAGRAM
VDD
Comparator
Oscillator
MUX
AIN0
ALERT/RDY
Gain = 2/3, 1, 2, 4, 8
or 16
ADDR
AIN1
16-Bit ΔΣ
ADC
PGA
2
IC
Interface
SCL
SDA
AIN2
AIN3/VREFIN
Voltage
Reference
SGM58031
GND
Figure 2. Functional Block Diagram
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION
Overview
For example, writing to the configuration register 0x01 sets
the SGM58031 to continuous conversion mode, we need the
following order:
The SGM58031 supports both differential inputs and
single-ended inputs.
1. First byte, 0b1001000 (first 7-bit is I C address), the 8 bit
is read/write bit which is low writing now
2. Second byte, 0b00000001 (points to Config register 0x01)
3. Third byte, 0b10000100 (MSB of the Config register to be
written, Bit[8] = 0 means the continuous mode)
4. Fourth byte, 0b10000011 (LSB of the Config register to be
written, Bit[7:5] = '100' means data rate 100Hz)
The SGM58031 is a low-power, 16-bit, delta-sigma (ΔΣ)
analog-to-digital converter (ADC).
2
The SGM58031 has two working modes: single-shot mode
and continuous conversion mode.
In single-shot mode, the ADC performs one conversion and
gives full settled data, no data needs to be discarded. Once
ADC completes the conversion, it then goes to low-power
shutdown mode.
th
For example, to read the conversion result from SGM58031,
the following order can be followed:
In continuous modes, the ADC begins a new conversion
automatically after a previous conversion is completed. Every
conversion result is given out. The data rate is equal to the
configured data rate.
2
th
1. First byte, 0b1001000 (first 7-bit is I C address), the 8 bit
is read/write bit which is low writing now
2. Second byte, 0b00000000 (points to Conversion register
0x00)
2
th
3. Third byte, 0b10010001 (first 7-bit is I C address), the 8
bit is read/write bit which is high reading now
4. Fourth byte, the SGM58031 answer with the MSB of the
Conversion register
5. Fifth byte, the SGM58031 answer with the LSB of the
Conversion register
Quickstart Guide
The basic connection of ADC is shown in Figure 3. The
2
communication interface is I C compatible. The SGM58031
2
works in slave mode. The I C address is configured as
0b1001000 (ADDR is connected to GND).
Figure 4 and Figure 5 show a demo read and write operation
sequence.
+3.3V
VDD
AIN0
AIN1
AIN2
AIN3/VREFIN
GND
100nF
+3.3V
ADDR
SGM58031
10kΩ
10kΩ
10kΩ
I2C-Capable Master
SCL
SCL
SDA
SDA
ALERT/RDY
VDD
GND
+3.3V
100nF
INT (Optional)
Figure 3. Basic Hardware Configuration
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
DETAILED DESCRIPTION (continued)
Frame 2
Frame 1
1
9
9
1
SCL
1
SDA
0
0
1
0
A1(1) A0(1)
0
ACK by
Device
Byte#1 I2C Slave Address Byte
START by
Master
0
W
0
0
0
P2
P1
P0
Byte#2 I2C Point Address Byte
Frame 3
ACK by
Device
STOP by
Master
Frame 4
1
1
9
9
SCL
(Continued)
SDA
(Continued)
1
0
0
1
0
A1(1) A0(1)
Byte#3 I2C Slave Address Byte
START by
Master
D15
R
ACK by
Device
D14
D13
D12
D11
D10
D9
Byte#4 Data Byte 1 from Device
D8
ACK by
Master (2)
Frame 5
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
Byte#5 Data Byte 2 from Device
D0
ACK by
Master (3)
STOP by
Master
NOTES:
1. The A0 and A1 values depend on the ADDR pin.
2. SDA can be set high by master to terminate a single-byte read operation.
3. SDA can be set high by master to terminate a two-byte read operation.
Figure 4. Timing Diagram for Read Word Register
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
DETAILED DESCRIPTION (continued)
Frame 2
Frame 1
1
9
1
9
SCL
1
SDA
0
0
1
0
A1(1) A0(1)
Byte#1 I2C Slave Address Byte
START by
Master
0
W
0
0
0
0
P2
P1
P0
Byte#2 I2C Point Address Byte
ACK by
Device
ACK by
Device
Frame 4
Frame 3
1
1
9
9
SCL
(Continued)
SDA
(Continued)
D15
D14
D13
D12
D11
D10
Byte#3 Data Byte 1 to
SGM58031 Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Byte#4 Data Byte 2 to
SGM58031 Register
ACK by
Device
ACK by
Device
STOP by
Master
NOTE:
1. The A0 and A1 values depend on the ADDR pin.
Figure 5. Timing Diagram for Write Word Register
The SGM58031 has a flexible input multiplexer. It can be
configured as 2 differential inputs or 4 single-ended inputs.
Whether the input is configured as differential inputs or
single-ended inputs, the absolute voltage on any inputs pin
must be in the range from GND to VDD.
Analog Inputs
The SGM58031 has a switched capacitor input stage. There
are charge and discharge current when ADC is working. The
equal effective input impedance can be estimated by REFF =
VIN/IAVERAGE.
The differential input impedance is ZDIFF in Figure 6. Table 1
shows the typical differential input impedance.
S1
AINP
S
Equivalent
Circuit
2
AINP
ZDIFF
CB
AINN
fCLK = 61.4kHz
S2
Multiplexer
AINN
S1
Figure 6. Simplified Analog Input Circuit
Table 1. Differential Input Impedance
FS (V)
Differential Input Impedance
±6.144V
(1)
±4.096V
(1)
37.5MΩ
25MΩ
±2.048V
12.5MΩ
±1.024V
6.25MΩ
±0.512V
6.25MΩ
±0.256V
6.25MΩ
NOTE:
1. FS = Full-scale range of the ADC scaling. In any event, it should
not exceed VDD + 0.3V be applied to this device.
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
Full-Scale Input
The SGM58031 has an internal PGA. The PGA can be set to
gains of 2/3, 1, 2, 4, 8 or 16. Table 2 and Table 3 show the
corresponding full-scale (FS) ranges.
Analog input voltages can never exceed the analog input
voltage limits.
Table 2. PGA Gain Full-Scale Range with Internal Reference
PGA Setting
FS (V)
2/3
±6.144V (1)
1
±4.096V (1)
2
±2.048V
4
±1.024V
8
±0.512V
16
±0.256V
Aliasing
For some applications, an RC external filtering is recommended.
Operating Modes
The SGM58031 has two working modes, continuous mode
and single-shot mode.
In continuous mode, the ADC begins a new conversion
automatically after a previous conversion is completed. Every
conversion result is given out.
In single-shot mode, if OS bit is written to '1', a single-shot
conversion is started, during the conversion process, the OS
bit is kept '0', and the chip doesn't response to OS bit
operation. If conversion data is ready, the OS bit is set to '1'
and the chip goes power-down automatically, and user can
write '1' to OS bit to call a single-shot conversion again.
NOTE:
1. FS = Full-scale range of the ADC scaling. In any event, it should
not exceed VDD + 0.3V be applied to this device.
Power-Up and Reset
Table 3. PGA Gain Full-Scale Range with External Reference
The SGM58031 supports I C general call reset command.
2
Details see I C General Call section.
PGA Setting
FS (V)
2/3
±3×VREF
1
±2×VREF
2
±VREF
4
±VREF/2
8
±VREF/4
16
±VREF/8
When the SGM58031 is powered up, all registers are reset to
default values.
2
Duty Cycling for Low Power
In some power sensitive application, the SGM58031 can work
in sampling and power-down mode periodically. The duty
cycle of working time and power-down time can be controlled
by microcontroller flexibly.
Data Format
The SGM58031 conversion result data is in binary two's
complement format.
Table 4 shows the ideal output codes for different input
signals.
For example, if the SGM58031 is configured as sample data
rate at 960Hz, we can operate it with 125ms duty cycle. It
means that we call the chip do single-shot conversion every
125ms, it will take the chip 3.2ms for sampling and then stay
in power-down mode for 121.8ms. Under this working mode,
it will reduce 39/40 power consumption compare with 960Hz
operation in continuous mode.
Table 4. Ideal Output Code for Different Input Signals
Input Signal VIN (AINP - AINN)
Ideal Output Code (1)
≥ FS (215 - 1)/215
7FFFh
15
+FS/2
0
0001h
0
15
-FS/2
≤ -FS
FFFFh
8000h
NOTE:
1. Except for effects of INL, noise, offset, and gain errors.
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
DETAILED DESCRIPTION (continued)
Data Rate
Input
Signal
Table 5. ADC Output Data Rate (SPS)
Low_Threshold
DR_SEL Bit in Config1 Register
DR[2:0] Bits
in Config Register
DR_SEL = 0
DR_SEL = 1
000
6.25Hz
7.5Hz
001
12.5Hz
15Hz
010
25Hz
30Hz
011
50Hz
60Hz
100
100Hz
120Hz
101
200Hz
240Hz
110
400Hz
480Hz
111
800Hz
960HZ
High_Threshold
Time
SMBus Alert
Response
Completed
Latching
Comparator
Output
Time
Non-Latching
Comparator
Output
Comparator
The SGM58031 has an inside comparator that can be used to
check ADC conversion results with high threshold and low
threshold. When the result exceeds the limited setting, the
chip can give an alert on the ALERT/RDY pin.
The comparator has two workings modes: traditional mode
and window comparator mode. These modes are
configurable. Under both working modes, the comparator can
be configured as latch output or no-latch output (COMP_LAT
bit in Config register). In latch output mode, the latched
comparator output can be cleared by issuing an SMBus alert
response or by reading the Conversion register. The
ALERT/RDY pin output active polarity (low or high) can be
configured by COMP_POL bit in Config register. Demos are
shown in Figure 7 and Figure 8.
The comparator output trigger waiting times can be set by
COMP_QUE[1:0] in Config register. It means comparator
output can wait until the ADC results beyond the threshold
configured times (which can be one, two, or four times).
Details see Config Register section.
Time
Figure 7. Alert Pin Timing Diagram when Configured as A
Traditional Comparator
Input
Signal
High_Threshold
Low_Threshold
Time
Latching
Comparator
Output
SMBus Alert
Response
Completed
SMBus Alert
Response
Completed
Time
Non-Latching
Comparator
Output
Time
Figure 8. Alert Pin Timing Diagram when Configured as A
Window Comparator
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
DETAILED DESCRIPTION (continued)
ADC Noise
Table 6. ADC Noise with Internal Reference (RMS in μV)
DR
FS
6.144
800
400
200
100
50
25
12.5
6.25
187.5
187.5
187.5
187.5
187.5
187.5
187.5
187.5
4.096
125
125
125
125
125
125
125
125
2.048
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
1.024
31.25
31.25
31.25
31.25
31.25
31.25
31.25
31.25
0.512
15.62
15.62
15.62
15.62
15.62
15.62
15.62
15.62
0.256
7.81
7.81
7.81
7.81
7.81
7.81
7.81
7.81
Table 7. ADC ENOB (ENOB = (20log (FS/Noise_RMS) - 1.76)/6.02)
DR
FS
6.144
800
400
200
100
50
25
12.5
6.25
16
16
16
16
16
16
16
16
4.096
16
16
16
16
16
16
16
16
2.048
16
16
16
16
16
16
16
16
1.024
16
16
16
16
16
16
16
16
0.512
16
16
16
16
16
16
16
16
0.256
16
16
16
16
16
16
16
16
Conversion Ready Pin
If ALERT/RDY pin is used as a conversion ready pin, we need
the following operations, firstly set the MSB (Most Significant
Bit) of the high threshold register to '1', secondly set the MSB of
the low threshold register to '0', and select COMP_QUE[1:0] in
'00' mode. It should be noted that COMP_QUE[1:0] can
disable this pin function. COMP_MODE and COMP_LAT have
no affection on this function.
The ALERT/RDY pin is an open-drain output, it needs a pull-up
resistor outside.
When the SGM58031 works in continuous mode, the
ALERT/RDY pin gives a pulse (~8μs) at the end of every
conversion completion.
When the SGM58031 works in single-shot mode, the
ALERT/RDY pin goes low (COMP_POL is set to '0') when the
conversion data is ready, and keeps low until the next
conversion starts. Please see demos in Figure 9 and Figure 10.
Digital Filter
The devices offer digital filter for filtering the digital data
stream coming from the delta-sigma modulator. The
implementation of the digital filter is determined by the ADC
data rate setting. When data rate is configured as 120, 100,
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60, 50, 30, 25, 15, 12.5, 7.5 and 6.25, the device uses a
3
third-order Sinc filter (Sinc ). When data rate is configured as
200, 240, 400, 480, 800 and 960, the device uses a
4
fourth-order Sinc filter (Sinc ).
When ALERT/RDY is used as the conversion completed
indication pin, its default logic state is high (pulled up by the
external resistor) during the conversion. When the device
works in continuous mode, the ALERT/RDY pin will go low
and remain low for about 8μs, generating an 8μs logic low
pulse at the end of each conversion cycle. When the device
3
works in single-shot mode and the Sinc filter is used, the
ALERT/RDY pin will go logic low after the third data
conversion is finished and remain low until the device begins
the next new conversion (OS bit is set to '1' again), and the
ALERT/RDY pin goes logic high again during the new
conversion. When the device works in single-shot mode and
4
the Sinc filter is used, the ALERT/RDY pin will go low after
the fourth data conversion is finished and remain low until the
device begins the next new conversion (OS bit is set to '1'
again), and the ALERT/RDY pin goes logic high again during
the new conversion. Please see ALERT/RDY examples in
Figure 9 and Figure 10.
JUNE 2022
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
DETAILED DESCRIPTION (continued)
SMBus Alert Response
2
command (0b00011001) to I C bus. Any SGM58031 on the
2
bus will response with their own address, the lowest I C
address chip will occupy the bus and it will clear itself
2
ALERT/RDY pin, the chip which loses I C bus will keep alert
on ALERT/RDY pin. The master will repeat SMBus alert
command until all salve chips clear their alert.
The ALERT/RDY pin can output as an SMBus alert. When it’s
in latch mode, COMP_LAT is set to '1'. If an ADC result is
above the upper threshold or below the lower threshold, this
pin is set (active low or active high). And the pin output is
latched, it can be cleared by reading ADC conversion data, or
by issuing an SMBus alert response (reading the alerting
2
device I C address).
The ALERT/RDY pin is an open-drain output, it needs a
pull-up resistor.
When ALERT/RDY pin is configured as window comparator
mode, if ADC result is higher than upper threshold or ADC
result is below the lower threshold, the pin is set (active low or
active high).
If an alert is output at the ALERT/RDY pin and latched, the
master controller accepts the alert, it sent an SMBus alert
Timing diagram for SMBus alert response is shown in Figure
11.
1 conversion cycle
RDY
8μs
Figure 9. RDY in Continuous Mode
3 or 4 Conversion Cycles
RDY
Previous data is ready
New conversion start
and 'OS' is set to '1'
Data is ready
Figure 10. RDY in Single-Shot Mode
ALERT
Frame 2
Frame 1
1
9
9
1
SCL
0
SDA
START by
Master
0
0
1
1
0
0
1
R/W
Byte#1 SMBus Alert Response Address Byte
ACK by
Device
0
0
1
0
A1
A0 Status
Byte#2 Slave Address from Device
NACK by
Master
STOP by
Master
NOTE: 1. The A0 and A1 values depend on the ADDR pin.
Figure 11. Timing Diagram for SMBus Alert Response
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SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
I2C Interface
2
The SGM58031 communication interface is an I C interface.
2
The SGM58031 can only act as slave devices. An I C timing
diagram is shown in Figure 1.
I2C Address Selection
The SGM58031 has a separate address setting pin ADDR,
which can be connected to GND, VDD, SDA and SCL. Table 8
shows the four available addresses.
Table 8. ADDR Pin Connection and Corresponding Slave
Address
ADDR Pin
Slave Address
GND
1001000
VDD
1001001
SDA
1001010
SCL
1001011
I2C General Call
2
The SGM58031 supports I C general call address (0000000)
and the eighth bit must be '0'. The device acknowledges the
general call address. And if the second byte is 00000110
(06h), the SGM58031 resets all registers and goes to
power-down.
I2C Speed Modes
2
The I C bus operation supports three speed modes: Standard
mode, fast mode, and high-speed mode. See more details in
Electrical Characteristics section.
To enter standard and fast mode, it needs no special
operation.
To enter high-speed mode, send a special address byte of
2
00001XXX following the I C start condition. The SGM58031
doesn't give an ACK (acknowledge) to this byte, the
SGM58031 switches to high-speed mode after receiving this
byte. The SGM58031 quits high-speed mode with the next
STOP condition.
Slave Mode Operations
The SGM58031 works in slave mode and doesn't drive the
SCL line.
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
REGISTER MAPS
Register Address
Table 9. Register Address
The SGM58031 has seven pointer registers. Table 9 and
Table 10 shows these register maps. Figure 4 shows how to
access this pointer registers.
Address
Register
0x0
Conversion Register
0x1
Config Register
0x2
Low_Thresh Register
0x3
High_Thresh Register
0x4
Config1 Register
0x5
Chip_ID Register
0x6
GN_Trim1 Register for EXT_REF
Pointer Register
Table 10. Pointer Register Byte (Write-Only)
MSB
LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
0
Bit 2
Bit 1
Bit 0
Register Address
Conversion Register
The ADC conversion result is 16-bit two's complement format. Table 11 shows the data format. Its reset default value is '0'.
Table 11. 16-Bit Conversion Register (Read-Only)
MSB
LSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOTE: Default Value = 0000h.
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
REGISTER MAPS (continued)
Config Register
The configuration register (Config Register) is shown in Table 12.
Table 12. Config Register Details (Read/Write)
BITS
D[15]
NAME
MUX[2:0]
D[11:9]
PGA[2:0]
D[8]
MODE
D[7:5]
DR[2:0]
D[3]
D[2]
D[1:0]
Working Status/Single-Shot Conversion Start
For a write status:
0 = No effect
1 = Start a single conversion (when in single-shot
mode)
OS
D[14:12]
D[4]
DESCRIPTION
For a read status:
0 = The chip is doing a conversion
1 = The chip isn’t doing a conversion
Input Multiplexer (MUX) Configuration
000 = AINP = AIN0 and AINN = AIN1 (default)
001 = AINP = AIN0 and AINN = AIN3
010 = AINP = AIN1 and AINN = AIN3
011 = AINP = AIN2 and AINN = AIN3
100 = AINP = AIN0 and AINN = GND
101 = AINP = AIN1 and AINN = GND
110 = AINP = AIN2 and AINN = GND
111 = AINP = AIN3 and AINN = GND
Programmable Gain Amplifier (PGA) Configuration
000 = FS = ±6.144V (1)
001 = FS = ±4.096V (1)
010 = FS = ±2.048V (default)
011 = FS = ±1.024V
100 = FS = ±0.512V
101 = FS = ±0.256V
110 = FS = ±0.256V
111 = FS = ±0.256V
Device Operating Mode
0 = Continuous conversion mode
1 = Power-down single-shot mode (default)
Data Rate
COMMENT
DEFAULT
VALUE
This bit reports the status of the chip.
This bit can only be written when the chip is in
power-down.
000
010
1
These bits control the data rate setting.
See Table 5.
Comparator Mode
COMP_MODE 0 = A traditional comparator with hysteresis (default)
1 = A window comparator
Comparator Polarity
This bit sets the active polarity of the
COMP_POL
0 = Active low (default)
ALERT/RDY pin.
1 = Active high
This bit sets whether the ALERT/RDY pin
Latching Comparator
latches once its outputs sets or resets when
COMP_LAT
0 = Non-latching comparator (default)
ADC conversion result is within the upper and
1 = Latching comparator
lower threshold limitations.
Comparator Queue and Disable Function
These bits can disable the comparator.
00 = Assert after one conversion
These bits can set the required times of
COMP_QUE[1:0] 01 = Assert after two conversions
successive ADC conversion beyond the
10 = Assert after four conversions
threshold before an alert output on
11 = Disable comparator (default)
ALERT/RDY pin.
100
0
0
0
11
NOTES:
1. Default Value = 8583h.
2. This is a theoretical full-scale range of the ADC scaling. The real input must be within the electrical limitation (0V ~ VDD + 0.3V).
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
REGISTER MAPS (continued)
Low_Thresh and High_Thresh Registers
The lower (Low_Thresh) and upper (High_Thresh) threshold registers are in 16-bit two's complement format. Table 13 shows
these two register format.
Table 13. Low_Thresh and High_Thresh Registers (Read/Write)
Low_Thresh Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Low_Thresh[15:8]
Bit 3
Low_Thresh[7:0]
High_Thresh Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 11
High_Thresh[15:8]
Bit 3
High_Thresh[7:0]
NOTE: Low_Thresh Default Value = 8000h, High_Thresh Default Value = 7FFFh.
Config1 Register
Table 14. 16-Bit Config1 Register Details
BITS
NAME
D[15:9]
N/A
D[8]
PD
D[7]
DR_SEL
D[6]
BURNOUT
D[5]
Reserved
DESCRIPTION
COMMENT
DEFAULT
VALUE
Writing '1' to PD powers down this part, and this PD bit is automatically cleared
internally. Another continuous/single conversion can be carried out again without
the need to clear this bit.
0
0 = DR[2:0] = 000 ~ 111 for conversion rate of 6.25Hz, 12.5Hz, 25Hz, 50Hz, 100Hz,
200Hz, 400Hz and 800Hz (default)
1 = DR[2:0] = 000 ~ 111 for conversion rate of 7.5Hz, 15Hz, 30Hz, 60Hz, 120Hz,
240Hz, 480Hz and 960Hz
0
0 = No current sourced (default)
1 = Source a pair of 2μA current to selected pair of AINs
0
0
2
D[4]
BUS_FLEX
D[3]
EXT_REF
D[2:0]
N/A
0 = Disable leakage blocking circuit for the scenario that I C bus voltage is lower
than VDD of the part. The I2C interface is still functional but VDD sees leakage when
VBUS < VDD - 0.3V (default)
1 = Bus voltage can be lower than VDD without causing leakage. The VDD range is
3V to 5.5V and the I2C bus voltage should be limited to 3V to 5.5V
0
0 = None (default)
1 = Use AIN3 as external reference for ADC
0
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Ultra-Small, Low-Power, 16-Bit
Analog-to-Digital Converter with Internal Reference
SGM58031
REGISTER MAPS (continued)
Chip_ID Register
Table 15. 16-Bit Chip_ID Register for Identifying Chip ID and Its Subversions (Read-Only)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
N/A
N/A
N/A
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
VER[2:0]
1
0
0
Bit 10
Bit 9
Bit 8
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
ID[4:0]
GN_Trim1 Register (When Using EXT_REF)
ADC gain coefficient for user selecting Config1 register EXT_REF bit as reference. We provide a default value and user is
responsible for writing proper value to the register if they want to compensate external reference error. This register does not take
effect when EXT_REF = 0 and internal reference is selected.
Table 16. GN_Trim1 Format
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
N/A
N/A
N/A
N/A
N/A
GN10
GN9
GN8
0
0
0
0
0
0
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GN7
GN6
GN5
GN4
GN3
GN2
GN1
GN0
1
1
1
1
1
0
1
0
ADC GN_Trim1 register is an unsigned value. Default value used for final trimming is 1.3333 to compensate default ADC gain of
3/4. The value of GN[10:0] adds a constant to get the final gain trimming value.
GN_Trim1 + CONST = GN_Trim. The binary value of CONST is 1010011010110000, corresponding to a gain factor of 1.30225.
After adding the default value of GN_Trim1 register (01111111010), the final default gain trimming value is 1.3333. The MAX final
gain trimming value is 1.3547 when trimming register is all '1'; MIN value is 1.30225 when register is all '0'. This gives GN
trimming a ±3% range and 32ppmFS step.
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
JUNE 2022 ‒ REV.A.1 to REV.A.2
Page
Updated Detailed Description section ................................................................................................................................................................ 16
MARCH 2020 ‒ REV.A to REV.A.1
Page
Updated Detailed Description section ................................................................................................................................................................ 12
Changes from Original (DECEMBER 2019) to REV.A
Page
Changed from product preview to production data ............................................................................................................................................. All
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22
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
MSOP-10
b
E1
4.8
E
1.02
e
0.5
0.3
RECOMMENDED LAND PATTERN (Unit: mm)
D
L
A
θ
c
A1
A2
Symbol
Dimensions
In Millimeters
MIN
MAX
A
0.820
1.100
A1
0.020
A2
0.750
b
0.180
Dimensions
In Inches
MIN
MAX
0.032
0.043
0.150
0.001
0.006
0.950
0.030
0.037
0.280
0.007
0.011
c
0.090
0.230
0.004
0.009
D
2.900
3.100
0.114
0.122
E
2.900
3.100
0.114
0.122
E1
4.750
5.050
0.187
e
0.500 BSC
0.199
0.020 BSC
L
0.400
0.800
0.016
0.031
θ
0°
6°
0°
6°
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
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TX00015.000
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TDFN-3×3-10L
D
e
N10
D1
k
E
E1
N1
N5
b
L
BOTTOM VIEW
TOP VIEW
2.4
1.7
A
2.8
A1
A2
0.6
SIDE VIEW
0.24
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
Symbol
Dimensions
In Millimeters
MIN
MAX
A
0.700
A1
0.000
A2
Dimensions
In Inches
MIN
MAX
0.800
0.028
0.050
0.000
0.203 REF
0.031
0.002
0.008 REF
D
2.900
3.100
0.114
0.122
D1
2.300
2.600
0.091
0.103
E
2.900
3.100
0.114
0.122
E1
1.500
1.800
0.059
0.071
0.300
0.007
k
b
0.200 MIN
0.180
e
L
0.008 MIN
0.500 TYP
0.300
0.012
0.020 TYP
0.500
0.012
0.020
NOTE: This drawing is subject to change without notice.
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TX00060.000
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
W
P0
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
B0
Reel Diameter
A0
P1
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel
Diameter
Reel Width
W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
W
(mm)
Pin1
Quadrant
MSOP-10
13″
12.4
5.20
3.30
1.20
4.0
8.0
2.0
12.0
Q1
TDFN-3×3-10L
13″
12.4
3.35
3.35
1.13
4.0
8.0
2.0
12.0
Q1
SG Micro Corp
www.sg-micro.com
TX10000.000
DD0001
Package Type
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
DD0002
Reel Type
TX20000.000
工商网监
湘ICP备2023018690号
